fixed debug output of unary x87 nodes

[libfirm] / ir / be / ia32 / ia32_spec.pl

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index ab0ef59..6faef6a 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -18,7 +18,7 @@ $comment_string = "/*";
 #
 # <op-name> => {
 #   "op_flags"  => "N|L|C|X|I|F|Y|H|c|K",
-#   "irn_flags" => "R|N|I"
+#   "irn_flags" => "R|N|I|S"
 #   "arity"     => "0|1|2|3 ... |variable|dynamic|any",
 #   "state"     => "floats|pinned|mem_pinned|exc_pinned",
 #   "args"      => [
@@ -33,6 +33,7 @@ $comment_string = "/*";
 #   "attr"      => "attitional attribute arguments for constructor"
 #   "init_attr" => "emit attribute initialization template"
 #   "rd_constructor" => "c source code which constructs an ir_node"
+#   "latency"   => "latency of this operation (can be float)"
 # },
 #
 # ... # (all nodes you need to describe)
@@ -57,6 +58,7 @@ $comment_string = "/*";
 #   R   rematerializeable
 #   N   not spillable
 #   I   ignore for register allocation
+#   S   modifies stack pointer
 #
 # state: state of the operation, OPTIONAL (default is "floats")
 #
@@ -89,6 +91,9 @@ $comment_string = "/*";
 #      return res
 #
 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
+#
+# latency: the latency of the operation, default is 1
+#
 
 # register types:
 #   0 - no special type
@@ -246,6 +251,7 @@ $comment_string = "/*";
   "reg_req"   => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
   "emit"      => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
   "outs"      => [ "EAX", "EDX", "M" ],
+  "latency"   => 10,
 },
 
 "l_MulS" => {
@@ -263,6 +269,7 @@ $comment_string = "/*";
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 5,
 },
 
 "l_Mul" => {
@@ -279,6 +286,7 @@ $comment_string = "/*";
   "reg_req"   => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
   "emit"      => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
   "outs"      => [ "EAX", "EDX", "M" ],
+  "latency"   => 5,
 },
 
 "And" => {
@@ -327,7 +335,8 @@ $comment_string = "/*";
   else {
 4.  cmovb %D1, %S2 /* %S1 is below %S2 */
   }
-'
+',
+  "latency"   => 2,
 },
 
 "Min" => {
@@ -342,7 +351,8 @@ $comment_string = "/*";
   else {
 2.  cmova %D1, %S2, %D1 /* %S1 is above %S2 */
   }
-'
+',
+  "latency"   => 2,
 },
 
 # not commutative operations
@@ -359,7 +369,7 @@ $comment_string = "/*";
 "SubC" => {
   "comment"   => "construct Sub with Carry: SubC(a, b) = a - b - carry",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
   "emit"      => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
 },
@@ -393,6 +403,7 @@ $comment_string = "/*";
   }
 ',
   "outs"      => [ "div_res", "mod_res", "M" ],
+  "latency"   => 25,
 },
 
 "Shl" => {
@@ -435,6 +446,7 @@ else {
 }
 ',
   "outs"      => [ "res", "M" ],
+  "latency"   => 6,
 },
 
 "l_ShlD" => {
@@ -483,6 +495,7 @@ else {
 }
 ',
   "outs"      => [ "res", "M" ],
+  "latency"   => 6,
 },
 
 "l_ShrD" => {
@@ -576,6 +589,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
   "outs"      => [ "false", "true" ],
+  "latency"   => 3,
 },
 
 "TestJmp" => {
@@ -584,6 +598,7 @@ else {
   "reg_req"  => { "in" => [ "gp", "gp" ] },
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "outs"      => [ "false", "true" ],
+  "latency"   => 3,
 },
 
 "CJmpAM" => {
@@ -606,6 +621,7 @@ else {
   "comment"   => "construct switch",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp" ], "out" => [ "none" ] },
+  "latency"   => 3,
 },
 
 "Const" => {
@@ -628,7 +644,6 @@ else {
 
 "Load" => {
   "op_flags"  => "L|F",
-  "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct Load: Load(ptr, mem) = LD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
@@ -686,7 +701,8 @@ else {
   "comment"   => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
-  "emit"      => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
+  "emit"      => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
+  "latency"   => 2,
 },
 
 "Push" => {
@@ -695,23 +711,35 @@ else {
   "emit"      => '
 if (get_ia32_id_cnst(n)) {
        if (get_ia32_immop_type(n) == ia32_ImmConst) {
-. push %C /* Push(%A2) */
-       } else {
-. push OFFSET FLAT:%C /* Push(%A2) */
+4. push %C /* Push const on stack */
+} else {
+4. push OFFSET FLAT:%C /* Push symconst on stack */
        }
 }
-else {
-. push %S2 /* Push(%A2) */
+else if (get_ia32_op_type(n) == ia32_Normal) {
+2. push %S2 /* Push(%A2) */
 }
+else {
+2. push %ia32_emit_am /* Push memory to stack */
+};
 ',
   "outs"      => [ "stack", "M" ],
+  "latency"   => 3,
 },
 
 "Pop" => {
   "comment"   => "pop a gp register from the stack",
   "reg_req"   => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
-  "emit"      => '. pop %D1 /* Pop -> %D1 */',
+  "emit"      => '
+if (get_ia32_op_type(n) == ia32_Normal) {
+2. pop %D1 /* Pop from stack into %D1 */
+}
+else {
+2. pop %ia32_emit_am /* Pop from stack into memory */
+}
+',
   "outs"      => [ "res", "stack", "M" ],
+  "latency"   => 4,
 },
 
 "Enter" => {
@@ -719,6 +747,7 @@ else {
   "reg_req"   => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
   "emit"      => '. enter /* Enter */',
   "outs"      => [ "frame", "stack", "M" ],
+  "latency"   => 15,
 },
 
 "Leave" => {
@@ -726,6 +755,14 @@ else {
   "reg_req"   => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
   "emit"      => '. leave /* Leave */',
   "outs"      => [ "frame", "stack", "M" ],
+  "latency"   => 3,
+},
+
+"AddSP" => {
+  "irn_flags" => "S|I",
+  "comment"   => "allocate space on stack",
+  "reg_req"   => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
+  "outs"      => [ "stack", "M" ],
 },
 
 #-----------------------------------------------------------------------------#
@@ -746,6 +783,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "xMul" => {
@@ -755,6 +793,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "xMax" => {
@@ -764,6 +803,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 2,
 },
 
 "xMin" => {
@@ -773,6 +813,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 2,
 },
 
 "xAnd" => {
@@ -782,6 +823,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 3,
 },
 
 "xOr" => {
@@ -800,6 +842,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 3,
 },
 
 # not commutative operations
@@ -811,6 +854,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
   "emit"      => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 3,
 },
 
 "xSub" => {
@@ -820,6 +864,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
   "emit"      => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "xDiv" => {
@@ -829,6 +874,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
   "emit"      => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 16,
 },
 
 # other operations
@@ -838,6 +884,7 @@ else {
   "comment"   => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 3,
 },
 
 "xCondJmp" => {
@@ -846,6 +893,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
   "outs"      => [ "false", "true" ],
+  "latency"   => 5,
 },
 
 "xConst" => {
@@ -855,19 +903,20 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "none" ], "out" => [ "xmm" ] },
   "emit"      => '. movs%M %D1, %C /* Load fConst into register */',
+  "latency"   => 2,
 },
 
 # Load / Store
 
 "xLoad" => {
   "op_flags"  => "L|F",
-  "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "construct SSE Load: Load(ptr, mem) = LD ptr",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
   "emit"      => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
   "outs"      => [ "res", "M" ],
+  "latency"   => 2,
 },
 
 "xStore" => {
@@ -878,6 +927,7 @@ else {
   "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ] },
   "emit"     => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
   "outs"      => [ "M" ],
+  "latency"   => 2,
 },
 
 "xStoreSimple" => {
@@ -888,6 +938,7 @@ else {
   "reg_req"  => { "in" => [ "gp", "xmm", "none" ] },
   "emit"     => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
   "outs"      => [ "M" ],
+  "latency"   => 2,
 },
 
 "l_X87toSSE" => {
@@ -913,6 +964,7 @@ else {
   "reg_req"  => { "in" => [ "gp", "none" ] },
   "emit"     => '. fstp %ia32_emit_am /* store ST0 onto stack */',
   "outs"     => [ "M" ],
+  "latency"  => 4,
 },
 
 "SetST0" => {
@@ -924,6 +976,7 @@ else {
   "reg_req"  => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] },
   "emit"     => '. fld %ia32_emit_am /* load ST0 from stack */',
   "outs"     => [ "res", "M" ],
+  "latency"  => 2,
 },
 
 # CopyB
@@ -940,7 +993,7 @@ else {
   "op_flags" => "F|H",
   "state"    => "pinned",
   "comment"  => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
-  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "cmp_attr" => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"  => { "in" => [ "edi", "esi", "none" ], "out" => [  "edi", "esi", "none" ] },
   "outs"     => [ "DST", "SRC", "M" ],
 },
@@ -949,61 +1002,68 @@ else {
 
 "Conv_I2I" => {
   "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
-  "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
+  "cmp_attr" => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
   "comment"  => "construct Conv Int -> Int",
-  "outs"      => [ "res", "M" ],
+  "outs"     => [ "res", "M" ],
 },
 
 "Conv_I2I8Bit" => {
   "reg_req"  => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
-  "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
+  "cmp_attr" => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
   "comment"  => "construct Conv Int -> Int",
-  "outs"      => [ "res", "M" ],
+  "outs"     => [ "res", "M" ],
 },
 
 "Conv_I2FP" => {
   "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
-  "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
+  "cmp_attr" => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
   "comment"  => "construct Conv Int -> Floating Point",
-  "outs"      => [ "res", "M" ],
+  "outs"     => [ "res", "M" ],
+  "latency"  => 10,
 },
 
 "Conv_FP2I" => {
   "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
-  "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
+  "cmp_attr" => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
   "comment"  => "construct Conv Floating Point -> Int",
-  "outs"      => [ "res", "M" ],
+  "outs"     => [ "res", "M" ],
+  "latency"  => 10,
 },
 
 "Conv_FP2FP" => {
   "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
-  "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
+  "cmp_attr" => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
   "comment"  => "construct Conv Floating Point -> Floating Point",
-  "outs"      => [ "res", "M" ],
+  "outs"     => [ "res", "M" ],
+  "latency"  => 8,
 },
 
 "CmpCMov" => {
   "irn_flags" => "R",
   "comment"   => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
-  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
+  "latency"   => 2,
 },
 
 "PsiCondCMov" => {
   "irn_flags" => "R",
   "comment"   => "check if Psi condition tree evaluates to true and move result accordingly",
-  "reg_req"   => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
+  "reg_req"   => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
+  "latency"   => 2,
 },
 
 "xCmpCMov" => {
   "irn_flags" => "R",
   "comment"   => "construct Conditional Move: SSE Compare + int CMov ",
-  "reg_req"   => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
+  "reg_req"   => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
+  "latency"   => 5,
 },
 
 "vfCmpCMov" => {
   "irn_flags" => "R",
   "comment"   => "construct Conditional Move: x87 Compare + int CMov",
-  "reg_req"   => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
+  "reg_req"   => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
+  "latency"   => 10,
 },
 
 "CmpSet" => {
@@ -1011,12 +1071,14 @@ else {
   "comment"   => "construct Set: Set(sel) == sel ? 1 : 0",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 2,
 },
 
 "PsiCondSet" => {
   "irn_flags" => "R",
   "comment"   => "check if Psi condition tree evaluates to true and set result accordingly",
   "reg_req"   => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
+  "latency"   => 2,
 },
 
 "xCmpSet" => {
@@ -1024,6 +1086,7 @@ else {
   "comment"   => "construct Set: SSE Compare + int Set",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 5,
 },
 
 "vfCmpSet" => {
@@ -1031,12 +1094,14 @@ else {
   "comment"   => "construct Set: x87 Compare + int Set",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 10,
 },
 
 "vfCMov" => {
   "irn_flags" => "R",
   "comment"   => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
-  "reg_req"   => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
+  "reg_req"   => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
+  "latency"   => 10,
 },
 
 #----------------------------------------------------------#
@@ -1059,6 +1124,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "vfmul" => {
@@ -1067,6 +1133,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "l_vfmul" => {
@@ -1082,6 +1149,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "l_vfsub" => {
@@ -1095,6 +1163,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 20,
 },
 
 "l_vfdiv" => {
@@ -1107,42 +1176,47 @@ else {
   "irn_flags" => "R",
   "comment"   => "virtual fp Abs: Abs(a) = |a|",
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+  "latency"   => 2,
 },
 
 "vfchs" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Chs: Chs(a) = -a",
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+  "latency"   => 2,
 },
 
 "vfsin" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Sin: Sin(a) = sin(a)",
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+  "latency"   => 150,
 },
 
 "vfcos" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Cos: Cos(a) = cos(a)",
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+  "latency"   => 150,
 },
 
 "vfsqrt" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
   "reg_req"   => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+  "latency"   => 30,
 },
 
 # virtual Load and Store
 
 "vfld" => {
   "op_flags"  => "L|F",
-  "irn_flags" => "R",
   "state"     => "exc_pinned",
   "comment"   => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 2,
 },
 
 "vfst" => {
@@ -1152,16 +1226,17 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "none" ] },
   "outs"      => [ "M" ],
+  "latency"   => 2,
 },
 
 # Conversions
 
 "vfild" => {
-  "irn_flags" => "R",
   "comment"   => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
   "outs"      => [ "res", "M" ],
+  "latency"   => 4,
 },
 
 "l_vfild" => {
@@ -1176,6 +1251,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "none" ] },
   "outs"      => [ "M" ],
+  "latency"   => 4,
 },
 
 "l_vfist" => {
@@ -1192,42 +1268,49 @@ else {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load 0.0: Ld 0.0 -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfld1" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load 1.0: Ld 1.0 -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfldpi" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load pi: Ld pi -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfldln2" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load ln 2: Ld ln 2 -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfldlg2" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load lg 2: Ld lg 2 -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfldl2t" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load ld 10: Ld ld 10 -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfldl2e" => {
   "irn_flags" => "R",
   "comment"   => "virtual fp Load ld e: Ld ld e -> reg",
   "reg_req"   => { "out" => [ "vfp" ] },
+  "latency"   => 4,
 },
 
 "vfConst" => {
@@ -1237,6 +1320,7 @@ else {
   "comment"   => "represents a virtual floating point constant",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "none" ], "out" => [ "vfp" ] },
+  "latency"   => 3,
 },
 
 # other
@@ -1247,6 +1331,7 @@ else {
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
   "outs"      => [ "false", "true", "temp_reg_eax" ],
+  "latency"   => 10,
 },
 
 #------------------------------------------------------------------------#
@@ -1262,7 +1347,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
+  "emit"      => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
 },
 
 "faddp" => {
@@ -1270,7 +1355,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
+  "emit"      => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
 },
 
 "fmul" => {
@@ -1278,7 +1363,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
+  "emit"      => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
 },
 
 "fmulp" => {
@@ -1286,7 +1371,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
+  "emit"      => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
 },
 
 "fsub" => {
@@ -1294,7 +1379,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
   "reg_req"   => { },
-  "emit"      => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
+  "emit"      => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
 },
 
 "fsubp" => {
@@ -1302,7 +1387,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
   "reg_req"   => { },
-  "emit"      => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
+  "emit"      => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
 },
 
 "fsubr" => {
@@ -1311,7 +1396,7 @@ else {
   "irn_flags" => "R",
   "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
   "reg_req"   => { },
-  "emit"      => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
+  "emit"      => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
 },
 
 "fsubrp" => {
@@ -1320,7 +1405,7 @@ else {
   "irn_flags" => "R",
   "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
   "reg_req"   => { },
-  "emit"      => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
+  "emit"      => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
 },
 
 "fdiv" => {
@@ -1328,7 +1413,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Div: Div(a, b) = a / b",
   "reg_req"   => { },
-  "emit"      => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
+  "emit"      => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
 },
 
 "fdivp" => {
@@ -1336,7 +1421,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Div: Div(a, b) = a / b",
   "reg_req"   => { },
-  "emit"      => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
+  "emit"      => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
 },
 
 "fdivr" => {
@@ -1344,7 +1429,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
   "reg_req"   => { },
-  "emit"      => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
+  "emit"      => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
 },
 
 "fdivrp" => {
@@ -1352,7 +1437,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
   "reg_req"   => { },
-  "emit"      => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
+  "emit"      => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
 },
 
 "fabs" => {
@@ -1360,7 +1445,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Abs: Abs(a) = |a|",
   "reg_req"   => { },
-  "emit"      => '. fabs /* x87 fabs(%S1) -> %D1 */',
+  "emit"      => '. fabs /* x87 fabs(%A1) -> %D1 */',
 },
 
 "fchs" => {
@@ -1368,7 +1453,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Chs: Chs(a) = -a",
   "reg_req"   => { },
-  "emit"      => '. fchs /* x87 fchs(%S1) -> %D1 */',
+  "emit"      => '. fchs /* x87 fchs(%A1) -> %D1 */',
 },
 
 "fsin" => {
@@ -1376,7 +1461,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sin: Sin(a) = sin(a)",
   "reg_req"   => { },
-  "emit"      => '. fsin /* x87 sin(%S1) -> %D1 */',
+  "emit"      => '. fsin /* x87 sin(%A1) -> %D1 */',
 },
 
 "fcos" => {
@@ -1384,7 +1469,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Cos: Cos(a) = cos(a)",
   "reg_req"   => { },
-  "emit"      => '. fcos /* x87 cos(%S1) -> %D1 */',
+  "emit"      => '. fcos /* x87 cos(%A1) -> %D1 */',
 },
 
 "fsqrt" => {
@@ -1392,7 +1477,7 @@ else {
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
   "reg_req"   => { },
-  "emit"      => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
+  "emit"      => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
 },
 
 # x87 Load and Store
@@ -1428,7 +1513,6 @@ else {
 
 "fild" => {
   "op_flags"  => "R",
-  "irn_flags" => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
   "reg_req"   => { },
@@ -1455,6 +1539,7 @@ else {
 
 "fldz" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load 0.0: Ld 0.0 -> reg",
   "reg_req"   => { },
@@ -1463,6 +1548,7 @@ else {
 
 "fld1" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load 1.0: Ld 1.0 -> reg",
   "reg_req"   => { },
@@ -1471,6 +1557,7 @@ else {
 
 "fldpi" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load pi: Ld pi -> reg",
   "reg_req"   => { },
@@ -1479,6 +1566,7 @@ else {
 
 "fldln2" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ln 2: Ld ln 2 -> reg",
   "reg_req"   => { },
@@ -1487,6 +1575,7 @@ else {
 
 "fldlg2" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load lg 2: Ld lg 2 -> reg",
   "reg_req"   => { },
@@ -1495,6 +1584,7 @@ else {
 
 "fldl2t" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ld 10: Ld ld 10 -> reg",
   "reg_req"   => { },
@@ -1503,6 +1593,7 @@ else {
 
 "fldl2e" => {
   "op_flags"  => "R",
+  "irn_flags"  => "R",
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ld e: Ld ld e -> reg",
   "reg_req"   => { },