use File::Basename;
-$new_emit_syntax = 1;
my $myname = $0;
# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
# 0 - no special type
# 1 - caller save (register must be saved by the caller of a function)
# 2 - callee save (register must be saved by the called function)
-# 4 - ignore (do not assign this register)
+# 4 - ignore (do not automatically assign this register)
# 8 - emitter can choose an arbitrary register of this class
# 16 - the register is a virtual one
# 32 - register represents a state
SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
SH0 => "${arch}_emit_8bit_high_source_register(node, 0);",
+ SS0 => "${arch}_emit_16bit_source_register_or_immediate(node, 0);",
+ SI0 => "${arch}_emit_source_register_or_immediate(node, 0);",
SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
D0 => "${arch}_emit_dest_register(node, 0);",
D1 => "${arch}_emit_dest_register(node, 1);",
+ DS0 => "${arch}_emit_dest_register_size(node, 0);",
DB0 => "${arch}_emit_8bit_dest_register(node, 0);",
X0 => "${arch}_emit_x87_register(node, 0);",
X1 => "${arch}_emit_x87_register(node, 1);",
%init_attr = (
ia32_asm_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_ia32_x87_attributes(res);".
"\tinit_ia32_asm_attributes(res);",
ia32_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);",
ia32_call_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_ia32_call_attributes(res, pop, call_tp);",
ia32_condcode_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_ia32_condcode_attributes(res, pnc);",
ia32_copyb_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_ia32_copyb_attributes(res, size);",
ia32_immediate_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);",
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, no_pic_adjust, offset);",
ia32_x87_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_ia32_x87_attributes(res);",
ia32_climbframe_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, exec_units, n_res);\n".
"\tinit_ia32_climbframe_attributes(res, count);",
);
state => "pinned",
op_flags => "c",
reg_req => { out => [ "gp_NOREG:I" ] },
- attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr => "ir_entity *symconst, int symconst_sign, int no_pic_adjust, long offset",
attr_type => "ia32_immediate_attr_t",
hash_func => "ia32_hash_Immediate",
latency => 0,
# very strict constraints
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
- out => [ "eax", "flags", "edx", "none" ] },
+ out => [ "eax", "flags", "none", "edx" ] },
ins => [ "base", "index", "mem", "left", "right" ],
emit => '. mul%M %unop4',
- outs => [ "res_low", "flags", "res_high", "M" ],
+ outs => [ "res_low", "flags", "M", "res_high" ],
am => "source,binary",
latency => 10,
units => [ "GP" ],
# very strict constraints
op_flags => "C",
cmp_attr => "return 1;",
- outs => [ "EAX", "flags", "EDX", "M" ],
- arity => 2
+ reg_req => { in => [ "none", "none" ],
+ out => [ "none", "none", "none", "none" ] },
+ ins => [ "left", "right" ],
+ outs => [ "res_low", "flags", "M", "res_high" ],
},
IMul => {
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
- out => [ "eax", "flags", "edx", "none" ] },
+ out => [ "eax", "flags", "none", "edx" ] },
ins => [ "base", "index", "mem", "left", "right" ],
emit => '. imul%M %unop4',
- outs => [ "res_low", "flags", "res_high", "M" ],
+ outs => [ "res_low", "flags", "M", "res_high" ],
am => "source,binary",
latency => 5,
units => [ "GP" ],
l_IMul => {
op_flags => "C",
cmp_attr => "return 1;",
- outs => [ "res_low", "res_high", "M" ],
- arity => 2
+ reg_req => { in => [ "none", "none" ],
+ out => [ "none", "none", "none", "none" ] },
+ ins => [ "left", "right" ],
+ outs => [ "res_low", "flags", "M", "res_high" ],
},
And => {
l_ShlDep => {
cmp_attr => "return 1;",
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
ins => [ "val", "count", "dep" ],
- arity => 3
},
ShlD => {
l_ShlD => {
cmp_attr => "return 1;",
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
ins => [ "val_high", "val_low", "count" ],
- arity => 3,
},
Shr => {
l_ShrDep => {
cmp_attr => "return 1;",
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
ins => [ "val", "count", "dep" ],
- arity => 3
},
ShrD => {
l_ShrD => {
cmp_attr => "return 1;",
- arity => 3,
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
ins => [ "val_high", "val_low", "count" ],
},
l_SarDep => {
cmp_attr => "return 1;",
ins => [ "val", "count", "dep" ],
- arity => 3
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
},
Ror => {
Cmp8Bit => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] ,
+ out => [ "flags", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "eflags" ],
+ outs => [ "eflags", "unused", "M" ],
am => "source,binary",
emit => '. cmpb %binop',
attr => "int ins_permuted, int cmp_unsigned",
Test => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] ,
+ out => [ "flags", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "eflags" ],
+ outs => [ "eflags", "unused", "M" ],
am => "source,binary",
emit => '. test%M %binop',
attr => "int ins_permuted, int cmp_unsigned",
Test8Bit => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] ,
+ out => [ "flags", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "eflags" ],
+ outs => [ "eflags", "unused", "M" ],
am => "source,binary",
emit => '. testb %binop',
attr => "int ins_permuted, int cmp_unsigned",
#irn_flags => "R",
reg_req => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] },
ins => [ "eflags" ],
+ outs => [ "res" ],
attr_type => "ia32_condcode_attr_t",
attr => "pn_Cmp pnc, int ins_permuted",
init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n".
# (note: leave the false,true order intact to make it compatible with other
# ia32_binary ops)
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "val_false", "val_true", "eflags" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
attr_type => "ia32_condcode_attr_t",
attr => "int ins_permuted, pn_Cmp pnc",
SwitchJmp => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp" ], out => [ "none" ] },
+ reg_req => { in => [ "gp" ] },
mode => "mode_T",
attr_type => "ia32_condcode_attr_t",
attr => "long pnc",
latency => 3,
units => [ "BRANCH" ],
modified_flags => $status_flags,
+ init_attr => "info->out_infos = NULL;", # XXX ugly hack for out requirements
+},
+
+Jmp => {
+ state => "pinned",
+ irn_flags => "J",
+ op_flags => "X",
+ reg_req => { out => [ "none" ] },
+ latency => 1,
+ units => [ "BRANCH" ],
+ mode => "mode_X",
},
IJmp => {
latency => 1,
units => [ "BRANCH" ],
mode => "mode_X",
+ init_attr => "info->out_infos = NULL;", # XXX ugly hack for out requirements
},
Const => {
irn_flags => "R",
reg_req => { out => [ "gp" ] },
units => [ "GP" ],
- attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr => "ir_entity *symconst, int symconst_sign, int no_pic_adjust, long offset",
attr_type => "ia32_immediate_attr_t",
latency => 1,
mode => $mode_gp,
Load => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ],
+ out => [ "gp", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M", "X_exc" ],
+ outs => [ "res", "unused", "M", "X_exc" ],
latency => 0,
emit => ". mov%EX%.l %AM, %D0",
units => [ "GP" ],
mode => mode_M,
},
+#
+# outport
+#
+Outport => {
+ irn_flags => "R",
+ state => "pinned",
+ reg_req => { in => [ "edx", "eax", "none" ], out => [ "none" ] },
+ ins => [ "port", "value", "mem" ],
+ emit => '. out%M %SS0, %SI1',
+ units => [ "GP" ],
+ latency => 1,
+ mode => mode_M,
+ modified_flags => $status_flags
+},
+
+#
+# inport
+#
+Inport => {
+ irn_flags => "R",
+ state => "pinned",
+ reg_req => { in => [ "edx", "none" ], out => [ "eax", "none" ] },
+ ins => [ "port", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. in%M %DS0, %SS0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => mode_T,
+ modified_flags => $status_flags
+},
+
#
# Intel style prefetching
#
xAdd => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. add%XXM %binop',
latency => 4,
xMul => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. mul%XXM %binop',
latency => 4,
xMax => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. max%XXM %binop',
latency => 2,
xMin => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. min%XXM %binop',
latency => 2,
xAnd => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. andp%XSD %binop',
latency => 3,
xOr => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. orp%XSD %binop',
latency => 3,
xXor => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. xorp%XSD %binop',
latency => 3,
xAndNot => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 !in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. andnp%XSD %binop',
latency => 3,
xSub => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4", "flags", "none" ] },
ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. sub%XXM %binop',
latency => 4,
xDiv => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "in_r4 !in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "dividend", "divisor" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
- outs => [ "res", "M" ],
emit => '. div%XXM %binop',
latency => 16,
units => [ "SSE" ],
Ucomi => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "eflags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ],
+ out => [ "eflags" ] },
ins => [ "base", "index", "mem", "left", "right" ],
outs => [ "flags" ],
am => "source,binary",
xLoad => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ],
+ out => [ "xmm", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M", "X_exc" ],
+ outs => [ "res", "unused", "M", "X_exc" ],
emit => '. mov%XXM %AM, %D0',
attr => "ir_mode *load_mode",
init_attr => "attr->ls_mode = load_mode;",
xStoreSimple => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M" ],
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
op_flags => "L|F",
cmp_attr => "return 1;",
ins => [ "val_high", "val_low" ],
+ reg_req => { in => [ "none", "none" ], out => [ "none" ] }
},
l_FloattoLL => {
cmp_attr => "return 1;",
ins => [ "val" ],
outs => [ "res_high", "res_low" ],
+ reg_req => { in => [ "none" ], out => [ "none", "none" ] }
},
# CopyB
Conv_I2I => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "gp", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
- outs => [ "res", "M" ],
+ outs => [ "res", "flags", "M" ],
am => "source,unary",
units => [ "GP" ],
latency => 1,
Conv_I2I8Bit => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "gp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ],
+ out => [ "gp", "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "res", "flags", "M" ],
am => "source,unary",
units => [ "GP" ],
latency => 1,
irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ],
+ out => [ "vfp", "none", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M", "X_exc" ],
+ outs => [ "res", "unused", "M", "X_exc" ],
attr => "ir_mode *load_mode",
init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ],
+ out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_exc" ],
attr => "ir_mode *store_mode",
vfild => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
- outs => [ "res", "M" ],
+ reg_req => { in => [ "gp", "gp", "none" ],
+ out => [ "vfp", "none", "none" ] },
+ outs => [ "res", "unused", "M" ],
ins => [ "base", "index", "mem" ],
latency => 4,
units => [ "VFP" ],
vfist => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ], out => [ "none" ] },
ins => [ "base", "index", "mem", "val", "fpcw" ],
+ outs => [ "M" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_M",
latency => 2,
},
-# SSE3 firsttp instruction
+# SSE3 fisttp instruction
fisttp => {
state => "exc_pinned",
rd_constructor => "NONE",
fxch => {
op_flags => "R|K",
- reg_req => { },
+ reg_req => { out => [ "none" ] },
cmp_attr => "return 1;",
emit => '. fxch %X0',
attr_type => "ia32_x87_attr_t",
fpush => {
op_flags => "R|K",
- reg_req => {},
+ reg_req => { out => [ "none" ] },
cmp_attr => "return 1;",
emit => '. fld %X0',
attr_type => "ia32_x87_attr_t",
fpop => {
op_flags => "K",
- reg_req => { },
+ reg_req => { out => [ "none" ] },
cmp_attr => "return 1;",
emit => '. fstp %X0',
attr_type => "ia32_x87_attr_t",
ffreep => {
op_flags => "K",
- reg_req => { },
+ reg_req => { out => [ "none" ] },
cmp_attr => "return 1;",
emit => '. ffreep %X0',
attr_type => "ia32_x87_attr_t",
emms => {
op_flags => "K",
- reg_req => { },
+ reg_req => { out => [ "none" ] },
cmp_attr => "return 1;",
emit => '. emms',
attr_type => "ia32_x87_attr_t",
femms => {
op_flags => "K",
- reg_req => { },
+ reg_req => { out => [ "none" ] },
cmp_attr => "return 1;",
emit => '. femms',
attr_type => "ia32_x87_attr_t",