{ "name" => "edi", "type" => 2 },
{ "name" => "ebp", "type" => 2 },
{ "name" => "esp", "type" => 4 },
- { "name" => "gp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
+ { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ "name" => "gp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
{ "mode" => "mode_Iu" }
],
{ "name" => "xmm5", "type" => 1 },
{ "name" => "xmm6", "type" => 1 },
{ "name" => "xmm7", "type" => 1 },
- { "name" => "xmm_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
+ { "name" => "xmm_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
- { "mode" => "mode_D" }
+ { "mode" => "mode_E" }
],
"vfp" => [
{ "name" => "vf0", "type" => 1 | 16 },
{ "name" => "vf5", "type" => 1 | 16 },
{ "name" => "vf6", "type" => 1 | 16 },
{ "name" => "vf7", "type" => 1 | 16 },
- { "name" => "vfp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes
+ { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ "name" => "vfp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
- { "mode" => "mode_D" }
+ { "mode" => "mode_E" }
],
"st" => [
{ "name" => "st0", "type" => 1 },
"ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
"M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
+ "XM" => "${arch}_emit_x87_mode_suffix(env, node);",
"AM" => "${arch}_emit_am(env, node);",
"unop" => "${arch}_emit_unop(env, node);",
"binop" => "${arch}_emit_binop(env, node);",
"reg_req" => { "out" => [ "vfp_UKNWN" ] },
"units" => [],
"emit" => "",
- "mode" => "mode_D"
+ "mode" => "mode_E"
},
"Unknown_XMM" => {
"reg_req" => { "out" => [ "xmm_UKNWN" ] },
"units" => [],
"emit" => "",
- "mode" => "mode_D"
+ "mode" => "mode_E"
},
"NoReg_GP" => {
"reg_req" => { "out" => [ "vfp_NOREG" ] },
"units" => [],
"emit" => "",
- "mode" => "mode_D"
+ "mode" => "mode_E"
},
"NoReg_XMM" => {
"reg_req" => { "out" => [ "xmm_NOREG" ] },
"units" => [],
"emit" => "",
- "mode" => "mode_D"
+ "mode" => "mode_E"
},
"ChangeCW" => {
"emit" => '. adds%M %binop',
"latency" => 4,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xMul" => {
"emit" => '. muls%M %binop',
"latency" => 4,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xMax" => {
"emit" => '. maxs%M %binop',
"latency" => 2,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xMin" => {
"emit" => '. mins%M %binop',
"latency" => 2,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xAnd" => {
"emit" => '. andp%M %binop',
"latency" => 3,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xOr" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
"emit" => '. orp%M %binop',
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xXor" => {
"emit" => '. xorp%M %binop',
"latency" => 3,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
# not commutative operations
"emit" => '. andnp%M %binop',
"latency" => 3,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xSub" => {
"emit" => '. subs%M %binop',
"latency" => 4,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xDiv" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
"latency" => 3,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"xCondJmp" => {
"emit" => '. movs%M %D1, $%C',
"latency" => 2,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
# Load / Store
"comment" => "construct Conv Int -> Floating Point",
"latency" => 10,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"Conv_FP2I" => {
"comment" => "construct Conv Floating Point -> Floating Point",
"latency" => 8,
"units" => [ "SSE" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"CmpCMov" => {
"reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
"latency" => 10,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
#----------------------------------------------------------#
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfmul" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"l_vfmul" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"l_vfsub" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"latency" => 20,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"l_vfprem" => {
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 2,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfchs" => {
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 2,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfsin" => {
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 150,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfcos" => {
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 150,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfsqrt" => {
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 30,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
# virtual Load and Store
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfld1" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfldpi" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfldln2" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfldlg2" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfldl2t" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfldl2e" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
"vfConst" => {
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 3,
"units" => [ "VFP" ],
- "mode" => "mode_D",
+ "mode" => "mode_E",
},
# other
"rd_constructor" => "NONE",
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fadd %x87_binop',
+ "emit" => '. fadd%XM %x87_binop',
},
"faddp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fmul %x87_binop',
+ "emit" => '. fmul%XM %x87_binop',
},
"fmulp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
- "emit" => '. fsub %x87_binop',
+ "emit" => '. fsub%XM %x87_binop',
},
"fsubp" => {
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
- "emit" => '. fsubr %x87_binop',
+ "emit" => '. fsubr%XM %x87_binop',
},
"fsubrp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
- "emit" => '. fdiv %x87_binop',
+ "emit" => '. fdiv%XM %x87_binop',
},
"fdivp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
- "emit" => '. fdivr %x87_binop',
+ "emit" => '. fdivr%XM %x87_binop',
},
"fdivrp" => {