]
); # %reg_classes
+%cpu = (
+ "ALU" => [ 1, "ALU1", "ALU2", "ALU3", "ALU4" ],
+ "MUL" => [ 1, "MUL1", "MUL2" ],
+ "SSE" => [ 1, "SSE1", "SSE2" ],
+ "FPU" => [ 1, "FPU1" ],
+ "MEM" => [ 1, "MEM1", "MEM2" ],
+ "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ],
+ "DUMMY" => [ 1, "DUMMY1", "DUMMY2", "DUMMY3", "DUMMY4" ]
+); # %cpu
+
+%vliw = (
+ "bundle_size" => 3,
+ "bundels_per_cycle" => 2
+); # vliw
+
#--------------------------------------------------#
# _ #
# (_) #
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU", "MEM" ],
},
"AddC" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU", "MEM" ],
+},
+
+"Add64Bit" => {
+ "irn_flags" => "R",
+ "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
+ "arity" => 4,
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
+ "emit" => '
+. mov %D1, %S1 /* mov a_l into assigned l_res register */
+. mov %D2, %S2 /* mov a_h into assigned h_res register */
+. add %D1, %S3 /* a_l + b_l */
+. adc %D2, %S4 /* a_h + b_h + carry */
+',
+ "outs" => [ "low_res", "high_res" ],
+ "units" => [ "ALU", "MEM" ],
},
"l_Add" => {
"emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
"outs" => [ "EAX", "EDX", "M" ],
"latency" => 10,
+ "units" => [ "MUL" ],
},
"l_MulS" => {
"emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 5,
+ "units" => [ "MUL" ],
},
"l_Mul" => {
"emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
"outs" => [ "EAX", "EDX", "M" ],
"latency" => 5,
+ "units" => [ "MUL" ],
},
"And" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"Or" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"Eor" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"l_Eor" => {
}
',
"latency" => 2,
+ "units" => [ "ALU" ],
},
"Min" => {
}
',
"latency" => 2,
+ "units" => [ "ALU" ],
},
# not commutative operations
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"SubC" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
"emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
+},
+
+"Sub64Bit" => {
+ "irn_flags" => "R",
+ "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
+ "arity" => 4,
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
+ "emit" => '
+. mov %D1, %S1 /* mov a_l into assigned l_res register */
+. mov %D2, %S2 /* mov a_h into assigned h_res register */
+. sub %D1, %S3 /* a_l - b_l */
+. sbb %D2, %S4 /* a_h - b_h - borrow */
+',
+ "outs" => [ "low_res", "high_res" ],
+ "units" => [ "ALU" ],
},
"l_Sub" => {
',
"outs" => [ "div_res", "mod_res", "M" ],
"latency" => 25,
+ "units" => [ "ALU" ],
},
"Shl" => {
"irn_flags" => "R",
"comment" => "construct Shl: Shl(a, b) = a << b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
"emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU1", "SSE1" ],
},
"l_Shl" => {
',
"outs" => [ "res", "M" ],
"latency" => 6,
+ "units" => [ "ALU1", "SSE1" ],
},
"l_ShlD" => {
"irn_flags" => "R",
"comment" => "construct Shr: Shr(a, b) = a >> b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
"emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU1", "SSE1" ],
},
"l_Shr" => {
',
"outs" => [ "res", "M" ],
"latency" => 6,
+ "units" => [ "ALU1", "SSE1" ],
},
"l_ShrD" => {
"irn_flags" => "R",
"comment" => "construct Shrs: Shrs(a, b) = a >> b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
"emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU1", "SSE1" ],
},
"l_Shrs" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
"emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU1", "SSE1" ],
},
"RotL" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
"emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU1", "SSE1" ],
},
# unary operations
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
+},
+
+"Minus64Bit" => {
+ "irn_flags" => "R",
+ "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
+ "arity" => 4,
+ "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
+ "emit" => '
+. mov %D1, %S1 /* l_res */
+. mov %D2, %S1 /* h_res */
+. sub %D1, %S2 /* 0 - a_l -> low_res */
+. sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
+',
+ "outs" => [ "low_res", "high_res" ],
+ "units" => [ "ALU" ],
},
+
"l_Minus" => {
"cmp_attr" => " return 1;\n",
"comment" => "construct lowered Minus: Minus(a) = -a",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"Dec" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"Not" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
# other operations
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
"outs" => [ "false", "true" ],
"latency" => 3,
+ "units" => [ "BRANCH" ],
},
"TestJmp" => {
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"outs" => [ "false", "true" ],
"latency" => 3,
+ "units" => [ "BRANCH" ],
},
"CJmpAM" => {
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
"outs" => [ "false", "true" ],
+ "units" => [ "BRANCH" ],
},
"CJmp" => {
"comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp" ] },
+ "units" => [ "BRANCH" ],
},
"SwitchJmp" => {
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
"latency" => 3,
+ "units" => [ "BRANCH" ],
},
"Const" => {
"comment" => "represents an integer constant",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "out" => [ "gp" ] },
+ "units" => [ "ALU" ],
},
"Cdq" => {
"reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
"emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
"outs" => [ "EAX", "EDX" ],
+ "units" => [ "ALU" ],
},
# Load / Store
}
',
"outs" => [ "res", "M" ],
+ "units" => [ "MEM" ],
},
"l_Load" => {
"emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
"outs" => [ "M" ],
"latency" => 3,
+ "units" => [ "MEM" ],
},
"Store8Bit" => {
"state" => "exc_pinned",
"comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
"emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
"outs" => [ "M" ],
"latency" => 3,
+ "units" => [ "MEM" ],
},
"Lea" => {
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
"emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
"latency" => 2,
+ "units" => [ "ALU" ],
},
"Push" => {
"emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
"outs" => [ "stack:I|S", "M" ],
"latency" => 3,
+ "units" => [ "MEM" ],
},
"Pop" => {
"emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
"outs" => [ "res", "stack:I|S", "M" ],
"latency" => 4,
+ "units" => [ "MEM" ],
},
"Enter" => {
"emit" => '. enter /* Enter */',
"outs" => [ "frame:I", "stack:I|S", "M" ],
"latency" => 15,
+ "units" => [ "MEM" ],
},
"Leave" => {
"emit" => '. leave /* Leave */',
"outs" => [ "frame:I", "stack:I|S", "M" ],
"latency" => 3,
+ "units" => [ "MEM" ],
},
"AddSP" => {
"comment" => "allocate space on stack",
"reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
"outs" => [ "stack:S", "M" ],
+ "units" => [ "ALU" ],
},
"SubSP" => {
"comment" => "free space on stack",
"reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
"outs" => [ "stack:S", "M" ],
+ "units" => [ "ALU" ],
},
"LdTls" => {
"irn_flags" => "R",
"comment" => "get the TLS base address",
"reg_req" => { "out" => [ "gp" ] },
+ "units" => [ "MEM" ],
},
"emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "SSE" ],
},
"xMul" => {
"emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "SSE" ],
},
"xMax" => {
"emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 2,
+ "units" => [ "SSE" ],
},
"xMin" => {
"emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 2,
+ "units" => [ "SSE" ],
},
"xAnd" => {
"emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 3,
+ "units" => [ "SSE" ],
},
"xOr" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
"emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
+ "units" => [ "SSE" ],
},
"xEor" => {
"emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 3,
+ "units" => [ "SSE" ],
},
# not commutative operations
"emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 3,
+ "units" => [ "SSE" ],
},
"xSub" => {
"emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "SSE" ],
},
"xDiv" => {
"emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 16,
+ "units" => [ "SSE" ],
},
# other operations
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
"outs" => [ "res", "M" ],
"latency" => 3,
+ "units" => [ "SSE" ],
},
"xCondJmp" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
"outs" => [ "false", "true" ],
"latency" => 5,
+ "units" => [ "SSE" ],
},
"xConst" => {
"reg_req" => { "out" => [ "xmm" ] },
"emit" => '. movs%M %D1, %C /* Load fConst into register */',
"latency" => 2,
+ "units" => [ "SSE" ],
},
# Load / Store
"emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
"outs" => [ "res", "M" ],
"latency" => 2,
+ "units" => [ "SSE" ],
},
"xStore" => {
"emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
"outs" => [ "M" ],
"latency" => 2,
+ "units" => [ "MEM" ],
},
"xStoreSimple" => {
"emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
"outs" => [ "M" ],
"latency" => 2,
+ "units" => [ "MEM" ],
},
"l_X87toSSE" => {
"emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
"outs" => [ "M" ],
"latency" => 4,
+ "units" => [ "MEM" ],
},
"SetST0" => {
"emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
"outs" => [ "res", "M" ],
"latency" => 2,
+ "units" => [ "MEM" ],
},
# CopyB
"comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
"reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
"outs" => [ "DST", "SRC", "CNT", "M" ],
+ "units" => [ "MEM" ],
},
"CopyB_i" => {
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
"outs" => [ "DST", "SRC", "M" ],
+ "units" => [ "MEM" ],
},
# Conversions
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
"comment" => "construct Conv Int -> Int",
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"Conv_I2I8Bit" => {
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
"comment" => "construct Conv Int -> Int",
"outs" => [ "res", "M" ],
+ "units" => [ "ALU" ],
},
"Conv_I2FP" => {
"comment" => "construct Conv Int -> Floating Point",
"outs" => [ "res", "M" ],
"latency" => 10,
+ "units" => [ "SSE" ],
},
"Conv_FP2I" => {
"comment" => "construct Conv Floating Point -> Int",
"outs" => [ "res", "M" ],
"latency" => 10,
+ "units" => [ "SSE" ],
},
"Conv_FP2FP" => {
"comment" => "construct Conv Floating Point -> Floating Point",
"outs" => [ "res", "M" ],
"latency" => 8,
+ "units" => [ "SSE" ],
},
"CmpCMov" => {
"comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
"latency" => 2,
+ "units" => [ "ALU" ],
},
"PsiCondCMov" => {
"comment" => "check if Psi condition tree evaluates to true and move result accordingly",
"reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
"latency" => 2,
+ "units" => [ "ALU" ],
},
"xCmpCMov" => {
"comment" => "construct Conditional Move: SSE Compare + int CMov ",
"reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
"latency" => 5,
+ "units" => [ "SSE" ],
},
"vfCmpCMov" => {
"comment" => "construct Conditional Move: x87 Compare + int CMov",
"reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
"latency" => 10,
+ "units" => [ "FPU" ],
},
"CmpSet" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
"outs" => [ "res", "M" ],
"latency" => 2,
+ "units" => [ "ALU" ],
},
"PsiCondSet" => {
"comment" => "check if Psi condition tree evaluates to true and set result accordingly",
"reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
"latency" => 2,
+ "units" => [ "ALU" ],
},
"xCmpSet" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
"outs" => [ "res", "M" ],
"latency" => 5,
+ "units" => [ "SSE" ],
},
"vfCmpSet" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
"outs" => [ "res", "M" ],
"latency" => 10,
+ "units" => [ "FPU" ],
},
"vfCMov" => {
"comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
"reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
"latency" => 10,
+ "units" => [ "FPU" ],
},
#----------------------------------------------------------#
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfmul" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "FPU" ],
},
"l_vfmul" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "FPU" ],
},
"l_vfsub" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"outs" => [ "res", "M" ],
"latency" => 20,
+ "units" => [ "FPU" ],
},
"l_vfdiv" => {
"arity" => 2,
},
+"vfprem" => {
+ "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 20,
+ "units" => [ "FPU" ],
+},
+
+"l_vfprem" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
+ "arity" => 2,
+},
+
"vfabs" => {
"irn_flags" => "R",
"comment" => "virtual fp Abs: Abs(a) = |a|",
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 2,
+ "units" => [ "FPU" ],
},
"vfchs" => {
"comment" => "virtual fp Chs: Chs(a) = -a",
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 2,
+ "units" => [ "FPU" ],
},
"vfsin" => {
"comment" => "virtual fp Sin: Sin(a) = sin(a)",
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 150,
+ "units" => [ "FPU" ],
},
"vfcos" => {
"comment" => "virtual fp Cos: Cos(a) = cos(a)",
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 150,
+ "units" => [ "FPU" ],
},
"vfsqrt" => {
"comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
"reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"latency" => 30,
+ "units" => [ "FPU" ],
},
# virtual Load and Store
"reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
"outs" => [ "res", "M" ],
"latency" => 2,
+ "units" => [ "FPU" ],
},
"vfst" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
"outs" => [ "M" ],
"latency" => 2,
+ "units" => [ "FPU" ],
},
# Conversions
"reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
"outs" => [ "res", "M" ],
"latency" => 4,
+ "units" => [ "FPU" ],
},
"l_vfild" => {
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
"outs" => [ "M" ],
"latency" => 4,
+ "units" => [ "FPU" ],
},
"l_vfist" => {
"comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfld1" => {
"comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfldpi" => {
"comment" => "virtual fp Load pi: Ld pi -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfldln2" => {
"comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfldlg2" => {
"comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfldl2t" => {
"comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfldl2e" => {
"comment" => "virtual fp Load ld e: Ld ld e -> reg",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 4,
+ "units" => [ "FPU" ],
},
"vfConst" => {
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "out" => [ "vfp" ] },
"latency" => 3,
+ "units" => [ "FPU" ],
},
# other
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
"outs" => [ "false", "true", "temp_reg_eax" ],
"latency" => 10,
+ "units" => [ "FPU" ],
},
#------------------------------------------------------------------------#
"emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
},
+"fprem" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
+ "reg_req" => { },
+ "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
+},
+
+# this node is just here, to keep the simulator running
+# we can omit this when a fprem simulation function exists
+"fpremp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
+ "reg_req" => { },
+ "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
+},
+
"fdiv" => {
"op_flags" => "R",
"rd_constructor" => "NONE",
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fldz /* x87 0.0 -> %D1 */',
},
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fld1 /* x87 1.0 -> %D1 */',
},
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load pi: Ld pi -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fldpi /* x87 pi -> %D1 */',
},
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
},
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
},
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
},
"op_flags" => "R|c",
"irn_flags" => "R",
"comment" => "x87 fp Load ld e: Ld ld e -> reg",
- "reg_req" => { },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
},
"rd_constructor" => "NONE",
"comment" => "represents a x87 constant",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "out" => [ "st" ] },
+ "reg_req" => { "out" => [ "vfp" ] },
"emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
},
# fxch, fpush, fpop
# Note that it is NEVER allowed to do CSE on these nodes
+# Moreover, note the virtual register requierements!
"fxch" => {
"op_flags" => "R|K",
"comment" => "x87 stack exchange",
- "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
+ "reg_req" => { },
"cmp_attr" => " return 1;\n",
"emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
},
"fpush" => {
+ "op_flags" => "R|K",
+ "comment" => "x87 stack push",
+ "reg_req" => {},
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fld %X1 /* x87 push %X1 */',
+},
+
+"fpushCopy" => {
"op_flags" => "R",
"comment" => "x87 stack push",
- "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
"cmp_attr" => " return 1;\n",
"emit" => '. fld %X1 /* x87 push %X1 */',
},
"fpop" => {
"op_flags" => "R|K",
"comment" => "x87 stack pop",
- "reg_req" => { "out" => [ "st" ] },
+ "reg_req" => { },
"cmp_attr" => " return 1;\n",
"emit" => '. fstp %X1 /* x87 pop %X1 */',
},
projects / libfirm / blobdiff