Add => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
emit => '. add%M %binop',
am => "full,binary",
units => [ "GP" ],
Adc => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right", "eflags" ],
+ outs => [ "res", "flags", "M" ],
emit => '. adc%M %binop',
am => "full,binary",
units => [ "GP" ],
# we should not rematrialize this node. It produces 2 results and has
# very strict constrains
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
+ out => [ "eax", "edx", "none" ] },
ins => [ "base", "index", "mem", "val_high", "val_low" ],
emit => '. mul%M %unop4',
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "res_low", "res_high", "M" ],
am => "source,binary",
latency => 10,
units => [ "GP" ],
# TODO: adjust out requirements for the 3 operand form
# (no need for should_be_same then)
reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
- out => [ "in_r4 in_r5", "none", "flags" ] },
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "res", "M", "flags" ],
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
latency => 5,
units => [ "GP" ],
IMul1OP => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
+ out => [ "eax", "edx", "none" ] },
ins => [ "base", "index", "mem", "val_high", "val_low" ],
emit => '. imul%M %unop4',
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "res_low", "res_high", "M" ],
am => "source,binary",
latency => 5,
units => [ "GP" ],
},
l_IMul => {
- # we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
op_flags => "C",
cmp_attr => "return 1;",
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "res_low", "res_high", "M" ],
arity => 2
},
And => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
op_modes => "commutative | am | immediate | mode_neutral",
am => "full,binary",
emit => '. and%M %binop',
Or => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "full,binary",
emit => '. or%M %binop',
units => [ "GP" ],
Xor => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "full,binary",
emit => '. xor%M %binop',
units => [ "GP" ],
Sub => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
am => "full,binary",
emit => '. sub%M %binop',
units => [ "GP" ],
Sbb => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
+ out => [ "in_r4 !in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right", "eflags" ],
+ outs => [ "res", "flags", "M" ],
am => "full,binary",
emit => '. sbb%M %binop',
units => [ "GP" ],
IDiv => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "none", "none", "edx" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ],
+ out => [ "eax", "flags", "none", "edx", "none" ] },
ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
- outs => [ "div_res", "M", "unused", "mod_res" ],
+ outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
am => "source,ternary",
emit => ". idiv%M %unop5",
latency => 25,
Div => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "none", "none", "edx" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ],
+ out => [ "eax", "flags", "none", "edx", "none" ] },
ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
- outs => [ "div_res", "M", "unused", "mod_res" ],
+ outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
am => "source,ternary",
emit => ". div%M %unop5",
latency => 25,
Shl => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
- ins => [ "left", "right" ],
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
emit => '. shl %SB1, %S0',
units => [ "GP" ],
latency => 1,
},
l_ShlDep => {
- cmp_attr => "return 1;",
- ins => [ "left", "right", "dep" ],
- # value, cnt, dependency
- arity => 3
+ cmp_attr => "return 1;",
+ ins => [ "val", "count", "dep" ],
+ arity => 3
},
ShlD => {
irn_flags => "R",
- # see ShrD about the strange out constraint
- reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] },
- ins => [ "left_high", "left_low", "right" ],
- emit => ". movl %S0, %D0".
- ". shld%M %SB2, %S1, %D0\n",
+ reg_req => { in => [ "gp", "gp", "ecx" ],
+ out => [ "in_r1 !in_r2 !in_r3", "flags" ] },
+ ins => [ "val_high", "val_low", "count" ],
+ outs => [ "res", "flags" ],
+ emit => ". shld%M %SB2, %S1, %D0",
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShlD => {
cmp_attr => "return 1;",
- ins => [ "high", "low", "count" ],
+ ins => [ "val_high", "val_low", "count" ],
arity => 3,
},
Shr => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
emit => '. shr %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
l_ShrDep => {
cmp_attr => "return 1;",
- ins => [ "left", "right", "dep" ],
- # value, cnt, dependency
+ ins => [ "val", "count", "dep" ],
arity => 3
},
ShrD => {
- # What's going on with the out constraint here? We would like to write
- # "in_r2" and be done. However in firm we only support should_be_same
- # constraints at the moment. Which means they could be non-fullfilled in
- # some cases. Now when all values happen to live through the node, out
- # is ecx and in_r2 not ecx, then we're screwed. Because in this case we
- # need a 4th Register.
- #
- # The best solution for this is extending the register allocator to support
- # must_be_same constraints which create a copy when the in_r2 value
- # lives through (this ensures that we have the 4th register in the cases
- # when we need it and can always fix the situation).
- #
- # For now I'm doing this ultra ugly !in hack which allocates 4 registers
- # and creates an extra mov
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] },
- ins => [ "left_high", "left_low", "right" ],
- emit => ". movl %S0, %D0".
- ". shld%M %SB2, %S1, %D0\n",
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx" ],
+ out => [ "in_r1 !in_r2 !in_r3", "flags" ] },
+ ins => [ "val_high", "val_low", "count" ],
+ outs => [ "res", "flags" ],
+ emit => ". shrd%M %SB2, %S1, %D0",
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShrD => {
cmp_attr => "return 1;",
arity => 3,
- ins => [ "high", "low", "count" ],
+ ins => [ "val_high", "val_low", "count" ],
},
Sar => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
emit => '. sar %SB1, %S0',
units => [ "GP" ],
latency => 1,
l_SarDep => {
cmp_attr => "return 1;",
- ins => [ "left", "right", "dep" ],
- # value, cnt, dependency
+ ins => [ "val", "count", "dep" ],
arity => 3
},
Ror => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
emit => '. ror %SB1, %S0',
units => [ "GP" ],
latency => 1,
Rol => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
emit => '. rol %SB1, %S0',
units => [ "GP" ],
latency => 1,
Neg => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
emit => '. neg %S0',
ins => [ "val" ],
+ outs => [ "res", "flags" ],
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
Inc => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ outs => [ "res", "flags" ],
emit => '. inc %S0',
units => [ "GP" ],
mode => $mode_gp,
Dec => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ outs => [ "res", "flags" ],
emit => '. dec %S0',
units => [ "GP" ],
mode => $mode_gp,
Not => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
ins => [ "val" ],
+ outs => [ "res", "flags" ],
emit => '. not %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
+ # no flags modified
},
NotMem => {
units => [ "GP" ],
latency => 1,
mode => "mode_M",
+ # no flags modified
+},
+
+Cmc => {
+ reg_req => { in => [ "flags" ], out => [ "flags" ] },
+ emit => '.cmc',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Stc => {
+ reg_req => { out => [ "flags" ] },
+ emit => '.stc',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags
},
# other operations
Load => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M" ],
+ outs => [ "res", "M", "X_exc" ],
latency => 0,
emit => ". mov%SE%ME%.l %AM, %D0",
units => [ "GP" ],
Store => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
emit => '. mov%M %SI3, %AM',
latency => 2,
units => [ "GP" ],
Store8Bit => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
emit => '. mov%M %SB3, %AM',
latency => 2,
units => [ "GP" ],
xLoad => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] },
ins => [ "base", "index", "mem" ],
+ outs => [ "res", "M", "X_exc" ],
emit => '. mov%XXM %AM, %D0',
attr => "ir_mode *load_mode",
init_attr => "attr->ls_mode = load_mode;",
- outs => [ "res", "M" ],
latency => 0,
units => [ "SSE" ],
},
xStore => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
},
-l_X87toSSE => {
+l_LLtoFloat => {
op_flags => "L|F",
cmp_attr => "return 1;",
- arity => 3,
+ ins => [ "val_high", "val_low" ],
},
-l_SSEtoX87 => {
+l_FloattoLL => {
op_flags => "L|F",
cmp_attr => "return 1;",
- arity => 3,
+ ins => [ "val" ],
+ outs => [ "res_high", "res_low" ],
},
# CopyB
irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M" ],
+ outs => [ "res", "M", "X_exc" ],
attr => "ir_mode *load_mode",
init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
attr => "ir_mode *store_mode",
init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
FucomFnstsw => {
reg_req => { },
emit => ". fucom %X1\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
FucompFnstsw => {
reg_req => { },
emit => ". fucomp %X1\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
FucomppFnstsw => {
reg_req => { },
emit => ". fucompp\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
FtstFnstsw => {
reg_req => { },
emit => ". ftst\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
$node->{op_attr_init} = $op_attr_init;
}
-print "ok";
+print "";
projects / libfirm / blobdiff