# comment => "any comment for constructor",
# reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
# cmp_attr => "c source code for comparing node attributes",
+# outs => { "out1", "out2" } # optional, creates pn_op_out1, ... consts
+# ins => { "in1", "in2" } # optional, creates n_op_in1, ... consts
+# mode => "mode_Iu" # optional, predefines the mode
# emit => "emit code with templates",
-# attr => "attitional attribute arguments for constructor"
-# init_attr => "emit attribute initialization template"
-# rd_constructor => "c source code which constructs an ir_node"
+# attr => "attitional attribute arguments for constructor",
+# init_attr => "emit attribute initialization template",
+# rd_constructor => "c source code which constructs an ir_node",
+# hash_func => "name of the hash function for this operation",
+# latency => "latency of this operation (can be float)"
# attr_type => "name of the attribute struct",
# },
#
# H irop_flag_highlevel
# c irop_flag_constlike
# K irop_flag_keep
+# NB irop_flag_dump_noblock
+# NI irop_flag_dump_noinput
#
# irn_flags: special node flags, OPTIONAL (default is 0)
# following irn_flags are supported:
SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+ SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
D0 => "${arch}_emit_dest_register(node, 0);",
D1 => "${arch}_emit_dest_register(node, 1);",
XXM => "${arch}_emit_xmm_mode_suffix(node);",
XSD => "${arch}_emit_xmm_mode_suffix_s(node);",
AM => "${arch}_emit_am(node);",
- unop3 => "${arch}_emit_unop(node, 3);",
- unop4 => "${arch}_emit_unop(node, 4);",
- unop5 => "${arch}_emit_unop(node, 5);",
+ unop3 => "${arch}_emit_unop(node, n_ia32_unary_op);",
+ unop4 => "${arch}_emit_unop(node, n_ia32_binary_right);",
binop => "${arch}_emit_binop(node);",
x87_binop => "${arch}_emit_x87_binop(node);",
CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);",
$res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_unary);";
} elsif($am eq "source,binary") {
$res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);";
- } elsif($am eq "dest,unary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);";
- } elsif($am eq "dest,binary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);";
- } elsif($am eq "dest,ternary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);";
} elsif($am eq "source,ternary") {
$res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);";
} elsif($am eq "none") {
$custom_init_attr_func = \&ia32_custom_init_attr;
%init_attr = (
- ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
- ia32_x87_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_x87_attributes(res);",
ia32_asm_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
"\tinit_ia32_x87_attributes(res);".
"\tinit_ia32_asm_attributes(res);",
- ia32_immediate_attr_t =>
+ ia32_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
+ ia32_condcode_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);",
+ "\tinit_ia32_condcode_attributes(res, pnc);",
ia32_copyb_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
"\tinit_ia32_copyb_attributes(res, size);",
- ia32_condcode_attr_t =>
+ ia32_immediate_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_condcode_attributes(res, pnc);",
+ "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);",
+ ia32_x87_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_x87_attributes(res);",
);
%compare_attr = (
- ia32_attr_t => "ia32_compare_nodes_attr",
- ia32_x87_attr_t => "ia32_compare_x87_attr",
ia32_asm_attr_t => "ia32_compare_asm_attr",
- ia32_immediate_attr_t => "ia32_compare_immediate_attr",
- ia32_copyb_attr_t => "ia32_compare_copyb_attr",
+ ia32_attr_t => "ia32_compare_nodes_attr",
ia32_condcode_attr_t => "ia32_compare_condcode_attr",
+ ia32_copyb_attr_t => "ia32_compare_copyb_attr",
+ ia32_immediate_attr_t => "ia32_compare_immediate_attr",
+ ia32_x87_attr_t => "ia32_compare_x87_attr",
);
%operands = (
reg_req => { out => [ "gp_NOREG" ] },
attr => "ir_entity *symconst, int symconst_sign, long offset",
attr_type => "ia32_immediate_attr_t",
+ hash_func => "ia32_hash_Immediate",
latency => 0,
mode => $mode_gp,
},
modified_flags => 1,
},
+# "allocates" a free register
ProduceVal => {
op_flags => "c",
irn_flags => "R",
Mul => {
# we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
+ # very strict constraints
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
out => [ "eax", "edx", "none" ] },
- ins => [ "base", "index", "mem", "val_high", "val_low" ],
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. mul%M %unop4',
outs => [ "res_low", "res_high", "M" ],
am => "source,binary",
l_Mul => {
# we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
+ # very strict constraints
op_flags => "C",
cmp_attr => "return 1;",
outs => [ "EAX", "EDX", "M" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
out => [ "eax", "edx", "none" ] },
- ins => [ "base", "index", "mem", "val_high", "val_low" ],
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. imul%M %unop4',
outs => [ "res_low", "res_high", "M" ],
am => "source,binary",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
out => [ "in_r4", "flags", "none" ] },
- ins => [ "base", "index", "mem", "left", "right" ],
+ ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. sub%M %binop',
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
- ins => [ "base", "index", "mem", "val" ],
+ ins => [ "base", "index", "mem", "subtrahend" ],
emit => '. sub%M %SI3, %AM',
units => [ "GP" ],
latency => 1,
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
- ins => [ "base", "index", "mem", "val" ],
+ ins => [ "base", "index", "mem", "subtrahend" ],
emit => '. sub%M %SB3, %AM',
units => [ "GP" ],
latency => 1,
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
out => [ "in_r4 !in_r5", "flags", "none" ] },
- ins => [ "base", "index", "mem", "left", "right", "eflags" ],
+ ins => [ "base", "index", "mem", "minuend", "subtrahend", "eflags" ],
outs => [ "res", "flags", "M" ],
am => "source,binary",
emit => '. sbb%M %binop',
l_Sub => {
reg_req => { in => [ "none", "none" ], out => [ "none" ] },
- ins => [ "left", "right" ],
+ ins => [ "minuend", "subtrahend" ],
},
l_Sbb => {
reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
- ins => [ "left", "right", "eflags" ],
+ ins => [ "minuend", "subtrahend", "eflags" ],
},
IDiv => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ],
+ reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
out => [ "eax", "flags", "none", "edx", "none" ] },
- ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
+ ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
am => "source,ternary",
- emit => ". idiv%M %unop5",
+ emit => ". idiv%M %unop3",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Div => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ],
+ reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
out => [ "eax", "flags", "none", "edx", "none" ] },
- ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
+ ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
am => "source,ternary",
- emit => ". div%M %unop5",
+ emit => ". div%M %unop3",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
irn_flags => "R",
reg_req => { in => [ "gp" ],
out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
outs => [ "res", "flags" ],
emit => '. inc %S0',
units => [ "GP" ],
irn_flags => "R",
reg_req => { in => [ "gp" ],
out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
outs => [ "res", "flags" ],
emit => '. dec %S0',
units => [ "GP" ],
Cmp => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "flags", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "eflags" ],
+ outs => [ "eflags", "unused", "M" ],
am => "source,binary",
emit => '. cmp%M %binop',
attr => "int ins_permuted, int cmp_unsigned",
reg_req => { in => [ "gp" ], out => [ "none" ] },
mode => "mode_T",
attr_type => "ia32_condcode_attr_t",
- attr => "pn_Cmp pnc",
+ attr => "long pnc",
latency => 3,
units => [ "BRANCH" ],
modified_flags => $status_flags,
Unknown_GP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB",
irn_flags => "I",
reg_req => { out => [ "gp_UKNWN" ] },
units => [],
Unknown_VFP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB",
irn_flags => "I",
reg_req => { out => [ "vfp_UKNWN" ] },
units => [],
Unknown_XMM => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB",
irn_flags => "I",
reg_req => { out => [ "xmm_UKNWN" ] },
units => [],
emit => "",
latency => 0,
- mode => "mode_E"
+ mode => $mode_xmm
},
NoReg_GP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB|NI",
irn_flags => "I",
reg_req => { out => [ "gp_NOREG" ] },
units => [],
NoReg_VFP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB|NI",
irn_flags => "I",
reg_req => { out => [ "vfp_NOREG" ] },
units => [],
NoReg_XMM => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB|NI",
irn_flags => "I",
reg_req => { out => [ "xmm_NOREG" ] },
units => [],
Cltd => {
# we should not rematrialize this node. It has very strict constraints.
reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] },
- ins => [ "val", "globbered" ],
+ ins => [ "val", "clobbered" ],
emit => '. cltd',
latency => 1,
mode => $mode_gp,
units => [ "GP" ],
},
-l_Load => {
- op_flags => "L|F",
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
-l_Store => {
- op_flags => "L|F",
- cmp_attr => "return 1;",
- state => "exc_pinned",
- arity => 3,
- mode => "mode_M",
-},
-
Store => {
op_flags => "L|F",
state => "exc_pinned",
Push => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp", "none" ] },
ins => [ "base", "index", "mem", "val", "stack" ],
- emit => '. push%M %unop4',
+ emit => '. push%M %unop3',
outs => [ "stack:I|S", "M" ],
- am => "source,binary",
+ am => "source,unary",
latency => 2,
units => [ "GP" ],
},
latency => 1,
},
+Bt => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp" ], out => [ "flags" ] },
+ ins => [ "left", "right" ],
+ emit => '. bt%M %S1, %S0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags # only CF is set, but the other flags are undefined
+},
#-----------------------------------------------------------------------------#
# _____ _____ ______ __ _ _ _ #
# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#-----------------------------------------------------------------------------#
+# produces a 0/+0.0
xZero => {
irn_flags => "R",
reg_req => { out => [ "xmm" ] },
emit => '. xorp%XSD %D0, %D0',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
+},
+
+xPzero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pxor %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# produces all 1 bits
+xAllOnes => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pcmpeqb %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, dword
+xPslld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. pslld %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, qword
+xPsllq => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psllq %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift right, dword
+xPsrld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psrld %SI1, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# mov from integer to SSE register
+xMovd => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp" ], out => [ "xmm" ] },
+ emit => '. movd %S0, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
},
# commutative operations
emit => '. add%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMul => {
emit => '. mul%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMax => {
emit => '. max%XXM %binop',
latency => 2,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMin => {
emit => '. min%XXM %binop',
latency => 2,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xAnd => {
emit => '. andp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xOr => {
emit => '. orp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xXor => {
emit => '. xorp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
# not commutative operations
emit => '. andnp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xSub => {
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
- ins => [ "base", "index", "mem", "left", "right" ],
+ ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
am => "source,binary",
emit => '. sub%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xDiv => {
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
- ins => [ "base", "index", "mem", "left", "right" ],
+ ins => [ "base", "index", "mem", "dividend", "divisor" ],
am => "source,binary",
outs => [ "res", "M" ],
emit => '. div%XXM %binop',
am => "source,unary",
latency => 10,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm,
},
Conv_FP2I => {
am => "source,unary",
latency => 8,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm,
},
#----------------------------------------------------------#
# irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
- ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
+ ins => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ],
am => "source,binary",
latency => 4,
units => [ "VFP" ],
vfdiv => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] },
- ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
+ ins => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ],
am => "source,binary",
outs => [ "res", "M" ],
latency => 20,
attr_type => "ia32_x87_attr_t",
},
-l_vfild => {
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
vfist => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] },
attr_type => "ia32_x87_attr_t",
},
-l_vfist => {
- cmp_attr => "return 1;",
+# SSE3 fisttp instruction
+vfisttp => {
state => "exc_pinned",
- arity => 3,
- mode => "mode_M",
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "in_r4", "none" ]},
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "res", "M" ],
+ latency => 4,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
},
latency => 2,
},
+# SSE3 firsttp instruction
+fisttp => {
+ state => "exc_pinned",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fisttp%M %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+ latency => 2,
+},
+
# constants
fldz => {
projects / libfirm / blobdiff