# for i = 1 .. arity: ir_node *op_i
# ir_mode *mode
#
+# outs: if a node defines more than one output, the names of the projections
+# nodes having outs having automatically the mode mode_T
+#
# comment: OPTIONAL comment for the node constructor
#
# rd_constructor: for every operation there will be a
# |_| #
#--------------------------------------------------#
+%operands = (
+);
+
%nodes = (
#-----------------------------------------------------------------#
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
"emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Mul" => {
- "irn_flags" => "A",
+ "irn_flags" => "R",
"comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
+ "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
"comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
- "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */'
+ "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
+ "outs" => [ "EAX", "EDX", "M" ],
},
"And" => {
"comment" => "construct And: And(a, b) = And(b, a) = a AND b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
+ "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Or" => {
"comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
+ "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Eor" => {
"comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
+ "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Max" => {
"comment" => "construct Sub: Sub(a, b) = a - b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
+ "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"DivMod" => {
else {
4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
-'
+',
+ "outs" => [ "div_res", "mod_res", "M" ],
},
"Shl" => {
"comment" => "construct Shl: Shl(a, b) = a << b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
+ "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Shr" => {
"comment" => "construct Shr: Shr(a, b) = a >> b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
+ "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"Shrs" => {
"comment" => "construct Shrs: Shrs(a, b) = a >> b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
+ "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"RotR" => {
"comment" => "construct RotR: RotR(a, b) = a ROTR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
+ "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"RotL" => {
"comment" => "construct RotL: RotL(a, b) = a ROTL b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
+ "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# unary operations
"comment" => "construct Minus: Minus(a) = -a",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
+ "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
"Inc" => {
"comment" => "construct Increment: Inc(a) = a++",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
+ "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
"Dec" => {
"comment" => "construct Decrement: Dec(a) = a--",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
+ "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
"Not" => {
"comment" => "construct Not: Not(a) = !a",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
+ "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
+ "outs" => [ "res", "M" ],
},
# other operations
"comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
+ "outs" => [ "false", "true" ],
},
"TestJmp" => {
"comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
"reg_req" => { "in" => [ "gp", "gp" ] },
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "outs" => [ "false", "true" ],
},
"CJmpAM" => {
"comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
+ "outs" => [ "false", "true" ],
},
"CJmp" => {
"irn_flags" => "R",
"comment" => "represents an integer constant",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "out" => [ "gp" ] },
+ "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
},
"Cdq" => {
"irn_flags" => "R",
"comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
"reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
- "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
+ "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
+ "outs" => [ "EAX", "EDX" ],
},
# Load / Store
else {
4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
}
-'
+',
+ "outs" => [ "res", "M" ],
},
"Store" => {
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
- "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
+ "outs" => [ "M" ],
},
"Store8Bit" => {
"comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
- "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
+ "outs" => [ "M" ],
},
"Lea" => {
"Push" => {
"comment" => "push a gp register on the stack",
- "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. push %S2 /* Push(%A2) */'
+ "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
+ "emit" => '
+if (get_ia32_id_cnst(n)) {
+ if (get_ia32_immop_type(n) == ia32_ImmConst) {
+. push %C /* Push(%A2) */
+ } else {
+. push OFFSET FLAT:%C /* Push(%A2) */
+ }
+}
+else {
+. push %S2 /* Push(%A2) */
+}
+',
+ "outs" => [ "stack", "M" ],
},
"Pop" => {
"comment" => "pop a gp register from the stack",
"reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
- "emit" => '. pop %D1 /* Pop -> %D1 */'
+ "emit" => '. pop %D1 /* Pop -> %D1 */',
+ "outs" => [ "res", "stack", "M" ],
},
"Enter" => {
"comment" => "create stack frame",
"reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
- "emit" => '. enter /* Enter */'
+ "emit" => '. enter /* Enter */',
+ "outs" => [ "frame", "stack", "M" ],
},
"Leave" => {
"comment" => "destroy stack frame",
"reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
- "emit" => '. leave /* Leave */'
+ "emit" => '. leave /* Leave */',
+ "outs" => [ "frame", "stack", "M" ],
},
#-----------------------------------------------------------------------------#
"comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
+ "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xMul" => {
"comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
+ "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xMax" => {
"comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
+ "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xMin" => {
"comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
+ "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xAnd" => {
"comment" => "construct SSE And: And(a, b) = a AND b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
+ "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xOr" => {
"comment" => "construct SSE Or: Or(a, b) = a OR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
+ "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xEor" => {
"comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
+ "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# not commutative operations
"comment" => "construct SSE Sub: Sub(a, b) = a - b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
+ "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xDiv" => {
"comment" => "construct SSE Div: Div(a, b) = a / b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
- "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
+ "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
# other operations
"comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
+ "outs" => [ "false", "true" ],
},
"xConst" => {
"irn_flags" => "R",
"comment" => "represents a SSE constant",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "out" => [ "xmm" ] },
+ "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] },
"emit" => '. mov%M %D1, %C /* Load fConst into register */',
},
"comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
- "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
+ "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
+ "outs" => [ "res", "M" ],
},
"xStore" => {
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
- "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
+ "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
+ "outs" => [ "M" ],
},
# CopyB
"Conv_I2I" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Int -> Int"
+ "comment" => "construct Conv Int -> Int",
+ "outs" => [ "res", "M" ],
},
"Conv_I2I8Bit" => {
"reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Int -> Int"
+ "comment" => "construct Conv Int -> Int",
+ "outs" => [ "res", "M" ],
},
"Conv_I2FP" => {
"reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Int -> Floating Point"
+ "comment" => "construct Conv Int -> Floating Point",
+ "outs" => [ "res", "M" ],
},
"Conv_FP2I" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
- "comment" => "construct Conv Floating Point -> Int"
+ "comment" => "construct Conv Floating Point -> Int",
+ "outs" => [ "res", "M" ],
},
"Conv_FP2FP" => {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
"cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
"comment" => "construct Conv Floating Point -> Floating Point",
+ "outs" => [ "res", "M" ],
},
#----------------------------------------------------------#
"comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfmul" => {
"comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfsub" => {
"comment" => "virtual fp Sub: Sub(a, b) = a - b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfdiv" => {
"comment" => "virtual fp Div: Div(a, b) = a / b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
},
"vfabs" => {
"state" => "exc_pinned",
"comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+ "outs" => [ "res", "M" ],
},
"vfst" => {
"comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
+ "outs" => [ "M" ],
},
# Conversions
"irn_flags" => "R",
"comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+ "outs" => [ "res", "M" ],
},
"vfist" => {
"comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
+ "outs" => [ "M" ],
},
# constants
"irn_flags" => "R",
"comment" => "represents a virtual floating point constant",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "out" => [ "vfp" ] },
+ "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] },
+},
+
+# other
+
+"vfCondJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "represents a virtual floating point compare",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
+ "outs" => [ "false", "true", "temp_reg_eax" ],
},
#------------------------------------------------------------------------#
"rd_constructor" => "NONE",
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
+ "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
},
"faddp" => {
"rd_constructor" => "NONE",
"comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { },
- "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
+ "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
},
"fmul" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
+ "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
},
"fmulp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
"reg_req" => { },
- "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
+ "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
},
"fsub" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
- "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
+ "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
},
"fsubp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sub: Sub(a, b) = a - b",
"reg_req" => { },
- "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
+ "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
},
"fsubr" => {
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
- "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
+ "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
},
"fsubrp" => {
"irn_flags" => "R",
"comment" => "x87 fp SubR: SubR(a, b) = b - a",
"reg_req" => { },
- "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
+ "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
},
"fdiv" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
- "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+ "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
},
"fdivp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Div: Div(a, b) = a / b",
"reg_req" => { },
- "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+ "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
},
"fdivr" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
- "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+ "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
},
"fdivrp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp DivR: DivR(a, b) = b / a",
"reg_req" => { },
- "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+ "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
},
"fabs" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Abs: Abs(a) = |a|",
"reg_req" => { },
- "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */'
+ "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */',
},
"fchs" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Chs: Chs(a) = -a",
"reg_req" => { },
- "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */'
+ "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */',
},
"fsin" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sin: Sin(a) = sin(a)",
"reg_req" => { },
- "emit" => '. fsin /* x87 sin(%S1) -> %D1 */'
+ "emit" => '. fsin /* x87 sin(%S1) -> %D1 */',
},
"fcos" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Cos: Cos(a) = cos(a)",
"reg_req" => { },
- "emit" => '. fcos /* x87 cos(%S1) -> %D1 */'
+ "emit" => '. fcos /* x87 cos(%S1) -> %D1 */',
},
"fsqrt" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
"reg_req" => { },
- "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */'
+ "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
},
# x87 Load and Store
"state" => "exc_pinned",
"comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { },
- "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */'
+ "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
},
"fst" => {
"state" => "exc_pinned",
"comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { },
- "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */'
+ "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
},
"fstp" => {
"state" => "exc_pinned",
"comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { },
- "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */'
+ "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
},
# Conversions
"irn_flags" => "R",
"comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
"reg_req" => { },
- "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */'
+ "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
},
"fist" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"reg_req" => { },
- "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */'
+ "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
},
"fistp" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"reg_req" => { },
- "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */'
+ "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
},
# constants
"rd_constructor" => "NONE",
"comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
"reg_req" => { },
- "emit" => '. fldz /* x87 0.0 -> %D1 */'
+ "emit" => '. fldz /* x87 0.0 -> %D1 */',
},
"fld1" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
"reg_req" => { },
- "emit" => '. fld1 /* x87 1.0 -> %D1 */'
+ "emit" => '. fld1 /* x87 1.0 -> %D1 */',
},
"fldpi" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load pi: Ld pi -> reg",
"reg_req" => { },
- "emit" => '. fldpi /* x87 pi -> %D1 */'
+ "emit" => '. fldpi /* x87 pi -> %D1 */',
},
"fldln2" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
"reg_req" => { },
- "emit" => '. fldln2 /* x87 ln(2) -> %D1 */'
+ "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
},
"fldlg2" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
"reg_req" => { },
- "emit" => '. fldlg2 /* x87 log(2) -> %D1 */'
+ "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
},
"fldl2t" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
"reg_req" => { },
- "emit" => '. fldll2t /* x87 ld(10) -> %D1 */'
+ "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
},
"fldl2e" => {
"rd_constructor" => "NONE",
"comment" => "x87 fp Load ld e: Ld ld e -> reg",
"reg_req" => { },
- "emit" => '. fldl2e /* x87 ld(e) -> %D1 */'
+ "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
},
"fldConst" => {
"emit" => '. fld%M %C /* Load fConst into register -> %D1 */',
},
-# fxch, fpush
+# fxch, fpush, fpop
# Note that it is NEVER allowed to do CSE on these nodes
"fxch" => {
"emit" => '. fld %X1 /* x87 push %X1 */',
},
+"fpop" => {
+ "op_flags" => "R|K",
+ "comment" => "x87 stack pop",
+ "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fstp %X1 /* x87 pop %X1 */',
+},
+
+# compare
+
+"fcomJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcompJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare and pop",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomppJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare and pop twice",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomrJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare reverse",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomrpJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare reverse and pop",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomrppJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare reverse and pop twice",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
); # end of %nodes
projects / libfirm / blobdiff