fixed requirements for ShrD and ShlD

[libfirm] / ir / be / ia32 / ia32_spec.pl

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 6faef6a..0d32820 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -425,7 +425,7 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "comment"   => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] },
   "emit"      =>
 '
 if (get_ia32_immop_type(n) == ia32_ImmNone) {
@@ -474,7 +474,7 @@ else {
   "irn_flags" => "R",
   "comment"   => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] },
   "emit"      =>
 '
 if (get_ia32_immop_type(n) == ia32_ImmNone) {
@@ -648,6 +648,7 @@ else {
   "comment"   => "construct Load: Load(ptr, mem) = LD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
+  "latency"   => 3,
   "emit"      =>
 '  if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
 4.   mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
@@ -684,6 +685,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ] },
   "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
   "outs"      => [ "M" ],
+  "latency"   => 3,
 },
 
 "Store8Bit" => {
@@ -694,6 +696,7 @@ else {
   "reg_req"   => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
   "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
   "outs"      => [ "M" ],
+  "latency"   => 3,
 },
 
 "Lea" => {
@@ -706,6 +709,7 @@ else {
 },
 
 "Push" => {
+  # We don't set class modify_stack here (but we will do this on proj 0)
   "comment"   => "push a gp register on the stack",
   "reg_req"   => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
   "emit"      => '
@@ -728,6 +732,7 @@ else {
 },
 
 "Pop" => {
+  # We don't set class modify stack here (but we will do this on proj 1)
   "comment"   => "pop a gp register from the stack",
   "reg_req"   => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
   "emit"      => '
@@ -759,12 +764,20 @@ else {
 },
 
 "AddSP" => {
-  "irn_flags" => "S|I",
+  "irn_flags" => "I",
   "comment"   => "allocate space on stack",
   "reg_req"   => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
   "outs"      => [ "stack", "M" ],
 },
 
+"LdTls" => {
+  "irn_flags" => "R",
+  "comment"   => "get the TLS base address",
+  "reg_req"   => { "out" => [ "gp" ] },
+},
+
+
+
 #-----------------------------------------------------------------------------#
 #   _____ _____ ______    __ _             _                     _            #
 #  / ____/ ____|  ____|  / _| |           | |                   | |           #
@@ -1538,63 +1551,56 @@ else {
 # constants
 
 "fldz" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load 0.0: Ld 0.0 -> reg",
   "reg_req"   => { },
   "emit"      => '. fldz /* x87 0.0 -> %D1 */',
 },
 
 "fld1" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load 1.0: Ld 1.0 -> reg",
   "reg_req"   => { },
   "emit"      => '. fld1 /* x87 1.0 -> %D1 */',
 },
 
 "fldpi" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load pi: Ld pi -> reg",
   "reg_req"   => { },
   "emit"      => '. fldpi /* x87 pi -> %D1 */',
 },
 
 "fldln2" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ln 2: Ld ln 2 -> reg",
   "reg_req"   => { },
   "emit"      => '. fldln2 /* x87 ln(2) -> %D1 */',
 },
 
 "fldlg2" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load lg 2: Ld lg 2 -> reg",
   "reg_req"   => { },
   "emit"      => '. fldlg2 /* x87 log(2) -> %D1 */',
 },
 
 "fldl2t" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ld 10: Ld ld 10 -> reg",
   "reg_req"   => { },
   "emit"      => '. fldll2t /* x87 ld(10) -> %D1 */',
 },
 
 "fldl2e" => {
-  "op_flags"  => "R",
+  "op_flags"  => "R|c",
   "irn_flags"  => "R",
-  "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ld e: Ld ld e -> reg",
   "reg_req"   => { },
   "emit"      => '. fldl2e /* x87 ld(e) -> %D1 */',
@@ -1632,7 +1638,7 @@ else {
 "fpop" => {
   "op_flags"  => "R|K",
   "comment"   => "x87 stack pop",
-  "reg_req"   => { "in" => [ "st"], "out" => [ "st" ] },
+  "reg_req"   => { "out" => [ "st" ] },
   "cmp_attr"  => "  return 1;\n",
   "emit"      => '. fstp %X1 /* x87 pop %X1 */',
 },