# init_attr => "emit attribute initialization template"
# rd_constructor => "c source code which constructs an ir_node"
# latency => "latency of this operation (can be float)"
+# attr_type => "name of the attribute struct",
# },
#
# ... # (all nodes you need to describe)
# NOTE: Last entry of each class is the largest Firm-Mode a register can hold
%reg_classes = (
gp => [
- { name => "eax", type => 1 },
{ name => "edx", type => 1 },
- { name => "ebx", type => 2 },
{ name => "ecx", type => 1 },
+ { name => "eax", type => 1 },
+ { name => "ebx", type => 2 },
{ name => "esi", type => 2 },
{ name => "edi", type => 2 },
{ name => "ebp", type => 2 },
{ name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
{ mode => "mode_Iu" }
],
+ mmx => [
+ { name => "mm0", type => 4 },
+ { name => "mm1", type => 4 },
+ { name => "mm2", type => 4 },
+ { name => "mm3", type => 4 },
+ { name => "mm4", type => 4 },
+ { name => "mm5", type => 4 },
+ { name => "mm6", type => 4 },
+ { name => "mm7", type => 4 },
+ { mode => "mode_E", flags => "manual_ra" }
+ ],
xmm => [
{ name => "xmm0", type => 1 },
{ name => "xmm1", type => 1 },
{ name => "st5", realname => "st(5)", type => 4 },
{ name => "st6", realname => "st(6)", type => 4 },
{ name => "st7", realname => "st(7)", type => 4 },
- { mode => "mode_E" }
+ { mode => "mode_E", flags => "manual_ra" }
],
fp_cw => [ # the floating point control word
- { name => "fpcw", type => 4 | 32},
- { mode => "mode_fpcw" }
+ { name => "fpcw", type => 4|32 },
+ { mode => "mode_fpcw", flags => "manual_ra|state" }
],
flags => [
- { name => "eflags", type => 4 },
- { mode => "mode_Iu" }
- ],
- fp_sw => [
- { name => "fpsw", type => 4 },
- { mode => "mode_Hu" }
+ { name => "eflags", type => 0 },
+ { mode => "mode_Iu", flags => "manual_ra" }
],
); # %reg_classes
-%flags = (
- CF => { reg => "eflags", bit => 0 },
- PF => { reg => "eflags", bit => 2 },
- AF => { reg => "eflags", bit => 4 },
- ZF => { reg => "eflags", bit => 6 },
- SF => { reg => "eflags", bit => 7 },
- TF => { reg => "eflags", bit => 8 },
- IF => { reg => "eflags", bit => 9 },
- DF => { reg => "eflags", bit => 10 },
- OF => { reg => "eflags", bit => 11 },
- IOPL0 => { reg => "eflags", bit => 12 },
- IOPL1 => { reg => "eflags", bit => 13 },
- NT => { reg => "eflags", bit => 14 },
- RF => { reg => "eflags", bit => 16 },
- VM => { reg => "eflags", bit => 17 },
- AC => { reg => "eflags", bit => 18 },
- VIF => { reg => "eflags", bit => 19 },
- VIP => { reg => "eflags", bit => 20 },
- ID => { reg => "eflags", bit => 21 },
-
- FP_IE => { reg => "fpsw", bit => 0 },
- FP_DE => { reg => "fpsw", bit => 1 },
- FP_ZE => { reg => "fpsw", bit => 2 },
- FP_OE => { reg => "fpsw", bit => 3 },
- FP_UE => { reg => "fpsw", bit => 4 },
- FP_PE => { reg => "fpsw", bit => 5 },
- FP_SF => { reg => "fpsw", bit => 6 },
- FP_ES => { reg => "fpsw", bit => 7 },
- FP_C0 => { reg => "fpsw", bit => 8 },
- FP_C1 => { reg => "fpsw", bit => 9 },
- FP_C2 => { reg => "fpsw", bit => 10 },
- FP_TOP0 => { reg => "fpsw", bit => 11 },
- FP_TOP1 => { reg => "fpsw", bit => 12 },
- FP_TOP2 => { reg => "fpsw", bit => 13 },
- FP_C3 => { reg => "fpsw", bit => 14 },
- FP_B => { reg => "fpsw", bit => 15 },
-
- FP_IM => { reg => "fpcw", bit => 0 },
- FP_DM => { reg => "fpcw", bit => 1 },
- FP_ZM => { reg => "fpcw", bit => 2 },
- FP_OM => { reg => "fpcw", bit => 3 },
- FP_UM => { reg => "fpcw", bit => 4 },
- FP_PM => { reg => "fpcw", bit => 5 },
- FP_PC0 => { reg => "fpcw", bit => 8 },
- FP_PC1 => { reg => "fpcw", bit => 9 },
- FP_RC0 => { reg => "fpcw", bit => 10 },
- FP_RC1 => { reg => "fpcw", bit => 11 },
- FP_X => { reg => "fpcw", bit => 12 }
-); # %flags
-
%cpu = (
GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
); # vliw
%emit_templates = (
- S0 => "${arch}_emit_source_register(env, node, 0);",
- S1 => "${arch}_emit_source_register(env, node, 1);",
- S2 => "${arch}_emit_source_register(env, node, 2);",
- S3 => "${arch}_emit_source_register(env, node, 3);",
- S4 => "${arch}_emit_source_register(env, node, 4);",
- S5 => "${arch}_emit_source_register(env, node, 5);",
- D0 => "${arch}_emit_dest_register(env, node, 0);",
- D1 => "${arch}_emit_dest_register(env, node, 1);",
- D2 => "${arch}_emit_dest_register(env, node, 2);",
- D3 => "${arch}_emit_dest_register(env, node, 3);",
- D4 => "${arch}_emit_dest_register(env, node, 4);",
- D5 => "${arch}_emit_dest_register(env, node, 5);",
- X0 => "${arch}_emit_x87_name(env, node, 0);",
- X1 => "${arch}_emit_x87_name(env, node, 1);",
- X2 => "${arch}_emit_x87_name(env, node, 2);",
- C => "${arch}_emit_immediate(env, node);",
- SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
+ S0 => "${arch}_emit_source_register(node, 0);",
+ S1 => "${arch}_emit_source_register(node, 1);",
+ S2 => "${arch}_emit_source_register(node, 2);",
+ S3 => "${arch}_emit_source_register(node, 3);",
+ S4 => "${arch}_emit_source_register(node, 4);",
+ S5 => "${arch}_emit_source_register(node, 5);",
+ SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
+ SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
+ SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+ SI0 => "${arch}_emit_source_register_or_immediate(node, 0);",
+ SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
+ SI2 => "${arch}_emit_source_register_or_immediate(node, 2);",
+ SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
+ D0 => "${arch}_emit_dest_register(node, 0);",
+ D1 => "${arch}_emit_dest_register(node, 1);",
+ D2 => "${arch}_emit_dest_register(node, 2);",
+ D3 => "${arch}_emit_dest_register(node, 3);",
+ D4 => "${arch}_emit_dest_register(node, 4);",
+ D5 => "${arch}_emit_dest_register(node, 5);",
+ DB0 => "${arch}_emit_8bit_dest_register(node, 0);",
+ X0 => "${arch}_emit_x87_register(node, 0);",
+ X1 => "${arch}_emit_x87_register(node, 1);",
+ X2 => "${arch}_emit_x87_register(node, 2);",
+ SE => "${arch}_emit_extend_suffix(get_ia32_ls_mode(node));",
ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
- ia32_emit_mode_suffix(env, node);",
- M => "${arch}_emit_mode_suffix(env, node);",
- XM => "${arch}_emit_x87_mode_suffix(env, node);",
- XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
- XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
- AM => "${arch}_emit_am(env, node);",
- unop => "${arch}_emit_unop(env, node);",
- binop => "${arch}_emit_binop(env, node);",
- x87_binop => "${arch}_emit_x87_binop(env, node);",
+ ia32_emit_mode_suffix(node);",
+ M => "${arch}_emit_mode_suffix(node);",
+ XM => "${arch}_emit_x87_mode_suffix(node);",
+ XXM => "${arch}_emit_xmm_mode_suffix(node);",
+ XSD => "${arch}_emit_xmm_mode_suffix_s(node);",
+ AM => "${arch}_emit_am(node);",
+ unop0 => "${arch}_emit_unop(node, 0);",
+ unop1 => "${arch}_emit_unop(node, 1);",
+ unop2 => "${arch}_emit_unop(node, 2);",
+ unop3 => "${arch}_emit_unop(node, 3);",
+ unop4 => "${arch}_emit_unop(node, 4);",
+ unop5 => "${arch}_emit_unop(node, 5);",
+ DAM0 => "${arch}_emit_am_or_dest_register(node, 0);",
+ DAM1 => "${arch}_emit_am_or_dest_register(node, 1);",
+ binop => "${arch}_emit_binop(node, 1);",
+ binop_nores => "${arch}_emit_binop(node, 0);",
+ x87_binop => "${arch}_emit_x87_binop(node);",
+ CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);",
);
#--------------------------------------------------#
# |_| #
#--------------------------------------------------#
-$default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
$default_attr_type = "ia32_attr_t";
+$default_copy_attr = "ia32_copy_attr";
+
+sub ia32_custom_init_attr {
+ my $node = shift;
+ my $name = shift;
+ my $res = "";
+ if(defined($node->{modified_flags})) {
+ $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n";
+ }
+ if(defined($node->{am})) {
+ my $am = $node->{am};
+ if($am eq "full,binary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_binary);";
+ } elsif($am eq "full,unary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_unary);";
+ } elsif($am eq "source,binary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);";
+ } elsif($am eq "dest,unary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);";
+ } elsif($am eq "dest,binary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);";
+ } elsif($am eq "dest,ternary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);";
+ } elsif($am eq "source,ternary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);";
+ } elsif($am eq "none") {
+ # nothing to do
+ } else {
+ die("Invalid address mode '$am' specified on op $name");
+ }
+ }
+ return $res;
+}
+$custom_init_attr_func = \&ia32_custom_init_attr;
+
+%init_attr = (
+ ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);",
+ ia32_x87_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
+ "\tinit_ia32_x87_attributes(res);",
+ ia32_asm_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
+ "\tinit_ia32_x87_attributes(res);".
+ "\tinit_ia32_asm_attributes(res);",
+ ia32_immediate_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
+ "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);"
+);
+
+%compare_attr = (
+ ia32_attr_t => "ia32_compare_nodes_attr",
+ ia32_x87_attr_t => "ia32_compare_x87_attr",
+ ia32_asm_attr_t => "ia32_compare_asm_attr",
+ ia32_immediate_attr_t => "ia32_compare_immediate_attr",
+);
%operands = (
);
$mode_xmm = "mode_E";
$mode_gp = "mode_Iu";
+$mode_flags = "mode_Iu";
$mode_fpcw = "mode_fpcw";
$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
%nodes = (
-#Immediate => {
-# irn_flags => "i",
-# reg_req => { out => [ "NoReg_GP" ] },
-# mode => $mode_gp,
-# attr_type => "ia32_imm_t",
-#},
+Immediate => {
+ state => "pinned",
+ op_flags => "c",
+ irn_flags => "I",
+ reg_req => { out => [ "gp_NOREG" ] },
+ attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr_type => "ia32_immediate_attr_t",
+ latency => 0,
+ mode => $mode_gp,
+},
+
+Asm => {
+ mode => "mode_T",
+ arity => "variable",
+ out_arity => "variable",
+ attr_type => "ia32_asm_attr_t",
+ latency => 100,
+},
+
+ProduceVal => {
+ op_flags => "c",
+ irn_flags => "R",
+ reg_req => { out => [ "gp" ] },
+ emit => "",
+ units => [ ],
+ latency => 0,
+ mode => $mode_gp,
+ cmp_attr => "return 1;",
+},
#-----------------------------------------------------------------#
# _ _ _ #
# commutative operations
-# NOTE:
-# All nodes supporting Addressmode have 5 INs:
-# 1 - base r1 == NoReg in case of no AM or no base
-# 2 - index r2 == NoReg in case of no AM or no index
-# 3 - op1 r3 == always present
-# 4 - op2 r4 == NoReg in case of immediate operation
-# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
-
Add => {
irn_flags => "R",
- comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. add%M %binop',
+ am => "full,binary",
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
-Adc => {
- comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. adc%M %binop',
+AddMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => ". add%M %SI3, %AM",
units => [ "GP" ],
- mode => $mode_gp,
+ mode => "mode_M",
modified_flags => $status_flags
},
-Add64Bit => {
+AddMem8Bit => {
irn_flags => "R",
- comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
- arity => 4,
- reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S1, %D1
-. addl %S2, %D0
-. adcl %S3, %D1
-',
- outs => [ "low_res", "high_res" ],
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => ". add%M %SB3, %AM",
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+Adc => {
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right", "eflags" ],
+ emit => '. adc%M %binop',
+ am => "full,binary",
units => [ "GP" ],
+ mode => $mode_gp,
modified_flags => $status_flags
},
l_Add => {
op_flags => "C",
- irn_flags => "R",
- cmp_attr => "return 1;",
- comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
- arity => 2,
+ reg_req => { in => [ "none", "none" ], out => [ "none" ] },
+ ins => [ "left", "right" ],
},
l_Adc => {
- op_flags => "C",
- cmp_attr => "return 1;",
- comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
- arity => 2,
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
+ ins => [ "left", "right", "eflags" ],
},
Mul => {
# we should not rematrialize this node. It produces 2 results and has
# very strict constrains
- comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
- reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- emit => '. mul%M %unop',
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "val_high", "val_low" ],
+ emit => '. mul%M %unop4',
outs => [ "EAX", "EDX", "M" ],
+ am => "source,binary",
latency => 10,
units => [ "GP" ],
modified_flags => $status_flags
# very strict constrains
op_flags => "C",
cmp_attr => "return 1;",
- comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
outs => [ "EAX", "EDX", "M" ],
arity => 2
},
IMul => {
irn_flags => "R",
- comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. imul%M %binop',
+ am => "source,binary",
latency => 5,
units => [ "GP" ],
mode => $mode_gp,
IMul1OP => {
irn_flags => "R",
- comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
- reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- emit => '. imul%M %unop',
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "val_high", "val_low" ],
+ emit => '. imul%M %unop4',
outs => [ "EAX", "EDX", "M" ],
+ am => "source,binary",
latency => 5,
units => [ "GP" ],
modified_flags => $status_flags
},
l_IMul => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
op_flags => "C",
cmp_attr => "return 1;",
- comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
+ outs => [ "EAX", "EDX", "M" ],
arity => 2
},
And => {
irn_flags => "R",
- comment => "construct And: And(a, b) = And(b, a) = a AND b",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "full,binary",
emit => '. and%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+AndMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. and%M %SI3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+AndMem8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. and%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Or => {
irn_flags => "R",
- comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "full,binary",
emit => '. or%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+OrMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. or%M %SI3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+OrMem8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. or%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Xor => {
irn_flags => "R",
- comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "full,binary",
emit => '. xor%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Xor => {
- op_flags => "C",
- cmp_attr => "return 1;",
- comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
- arity => 2,
+XorMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. xor%M %SI3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+XorMem8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. xor%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
modified_flags => $status_flags
},
Sub => {
irn_flags => "R",
- comment => "construct Sub: Sub(a, b) = a - b",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "full,binary",
emit => '. sub%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+SubMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. sub%M %SI3, %AM',
+ units => [ "GP" ],
+ mode => 'mode_M',
+ modified_flags => $status_flags
+},
+
+SubMem8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. sub%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => 'mode_M',
+ modified_flags => $status_flags
+},
+
Sbb => {
- comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 !in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "full,binary",
emit => '. sbb%M %binop',
units => [ "GP" ],
mode => $mode_gp,
Sub64Bit => {
irn_flags => "R",
- comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
arity => 4,
reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
emit => '
. movl %S0, %D0
. movl %S1, %D1
-. subl %S2, %D0
-. sbbl %S3, %D1
+. subl %SI2, %D0
+. sbbl %SI3, %D1
',
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
modified_flags => $status_flags
},
-l_Sub => {
- irn_flags => "R",
- cmp_attr => "return 1;",
- comment => "construct lowered Sub: Sub(a, b) = a - b",
- arity => 2,
-},
-
-l_Sbb => {
- cmp_attr => "return 1;",
- comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
- arity => 2,
-},
-
IDiv => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
+ outs => [ "div_res", "mod_res", "M" ],
attr => "ia32_op_flavour_t dm_flav",
+ am => "source,ternary",
init_attr => "attr->data.op_flav = dm_flav;",
- emit => ". idiv%M %unop",
- outs => [ "div_res", "mod_res", "M" ],
+ emit => ". idiv%M %unop5",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Div => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
+ outs => [ "div_res", "mod_res", "M" ],
attr => "ia32_op_flavour_t dm_flav",
+ am => "source,ternary",
init_attr => "attr->data.op_flav = dm_flav;",
- emit => ". div%M %unop",
- outs => [ "div_res", "mod_res", "M" ],
+ emit => ". div%M %unop5",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Shl => {
irn_flags => "R",
- comment => "construct Shl: Shl(a, b) = a << b",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
- emit => '. shl%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "left", "right" ],
+ am => "dest,binary",
+ emit => '. shl %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Shl => {
+ShlMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. shl%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+l_ShlDep => {
cmp_attr => "return 1;",
- comment => "construct lowered Shl: Shl(a, b) = a << b",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShlD => {
- irn_flags => "R",
- comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
- emit =>
-'
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shld%M %%cl, %S3, %AM
- } else {
- . shld%M %%cl, %S3, %S2
- }
-} else {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shld%M %C, %S3, %AM
- } else {
- . shld%M %C, %S3, %S2
- }
-}
-',
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "in_r1 !in_r3" ] },
+ ins => [ "left_high", "left_low", "right" ],
+ am => "dest,ternary",
+ emit => '. shld%M %SB2, %S1, %S0',
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShlD => {
cmp_attr => "return 1;",
- comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
arity => 3,
},
Shr => {
irn_flags => "R",
- comment => "construct Shr: Shr(a, b) = a >> b",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. shr%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ am => "dest,binary",
+ emit => '. shr %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Shr => {
+ShrMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. shr%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+l_ShrDep => {
cmp_attr => "return 1;",
- comment => "construct lowered Shr: Shr(a, b) = a << b",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShrD => {
- irn_flags => "R",
- comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
- emit => '
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shrd%M %%cl, %S3, %AM
- } else {
- . shrd%M %%cl, %S3, %S2
- }
-} else {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shrd%M %C, %S3, %AM
- } else {
- . shrd%M %C, %S3, %S2
- }
-}
-',
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "in_r1 !in_r3" ] },
+ ins => [ "left_high", "left_low", "right" ],
+ am => "dest,ternary",
+ emit => '. shrd%M %SB2, %S1, %S0',
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShrD => {
cmp_attr => "return 1;",
- comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
arity => 3
},
Sar => {
irn_flags => "R",
- comment => "construct Shrs: Shrs(a, b) = a >> b",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. sar%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ am => "dest,binary",
+ emit => '. sar %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+SarMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. sar%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
l_Sar => {
cmp_attr => "return 1;",
- comment => "construct lowered Sar: Sar(a, b) = a << b",
+ # value, cnt
arity => 2
},
+l_SarDep => {
+ cmp_attr => "return 1;",
+ # value, cnt, dependency
+ arity => 3
+},
+
Ror => {
irn_flags => "R",
- comment => "construct Ror: Ror(a, b) = a ROR b",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. ror%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ am => "dest,binary",
+ emit => '. ror %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+RorMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. ror%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Rol => {
irn_flags => "R",
- comment => "construct Rol: Rol(a, b) = a ROL b",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. rol%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ am => "dest,binary",
+ emit => '. rol %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+RolMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. rol%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
# unary operations
Neg => {
irn_flags => "R",
- comment => "construct Minus: Minus(a) = -a",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. neg%M %unop',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ emit => '. neg %S0',
+ ins => [ "val" ],
+ am => "dest,unary",
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+NegMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. neg%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Minus64Bit => {
irn_flags => "R",
- comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
- arity => 4,
- reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S0, %D1
-. subl %S1, %D0
-. sbbl %S2, %D1
-',
+ reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] },
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
modified_flags => $status_flags
l_Neg => {
cmp_attr => "return 1;",
- comment => "construct lowered Minus: Minus(a) = -a",
arity => 1,
},
Inc => {
irn_flags => "R",
- comment => "construct Increment: Inc(a) = a++",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. inc%M %unop',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ am => "dest,unary",
+ emit => '. inc %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
},
+IncMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. inc%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+},
+
Dec => {
irn_flags => "R",
- comment => "construct Decrement: Dec(a) = a--",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. dec%M %unop',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ am => "dest,unary",
+ emit => '. dec %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
},
+DecMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. dec%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+},
+
Not => {
irn_flags => "R",
- comment => "construct Not: Not(a) = !a",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. not%M %unop',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ ins => [ "val" ],
+ am => "dest,unary",
+ emit => '. not %S0',
units => [ "GP" ],
mode => $mode_gp,
- modified_flags => []
+},
+
+NotMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. not%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
},
# other operations
-CondJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
- outs => [ "false", "true" ],
- latency => 3,
- units => [ "BRANCH" ],
+Cmp => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. cmp%M %binop_nores',
+ attr => "int flipped, int cmp_unsigned",
+ init_attr => "attr->data.cmp_flipped = flipped;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
},
-TestJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
- reg_req => { in => [ "gp", "gp" ] },
- outs => [ "false", "true" ],
- latency => 3,
- units => [ "BRANCH" ],
+Cmp8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. cmpb %binop_nores',
+ attr => "int flipped, int cmp_unsigned",
+ init_attr => "attr->data.cmp_flipped = flipped;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
},
-CJmpAM => {
- state => "pinned",
- op_flags => "L|X|Y",
- comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
- outs => [ "false", "true" ],
- units => [ "BRANCH" ],
+Test => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. test%M %binop_nores',
+ attr => "int flipped, int cmp_unsigned",
+ init_attr => "attr->data.cmp_flipped = flipped;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
},
-CJmp => {
+Test8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. testb %binop_nores',
+ attr => "int flipped, int cmp_unsigned",
+ init_attr => "attr->data.cmp_flipped = flipped;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Set => {
+ #irn_flags => "R",
+ reg_req => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] },
+ ins => [ "eflags" ],
+ am => "dest,unary",
+ attr => "pn_Cmp pnc",
+ init_attr => "attr->pn_code = pnc;\nset_ia32_ls_mode(res, mode_Bu);\n",
+ emit => '. set%CMP0 %DB0',
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+CMov => {
+ #irn_flags => "R",
+ # (note: leave the false,true order intact to make it compatible with other
+ # ia32_binary ops)
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4" ] },
+ ins => [ "base", "index", "mem", "val_false", "val_true", "eflags" ],
+ am => "source,binary",
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+Jcc => {
state => "pinned",
op_flags => "L|X|Y",
- comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
- reg_req => { in => [ "gp", "gp" ] },
+ reg_req => { in => [ "eflags" ], out => [ "none", "none" ] },
+ ins => [ "eflags" ],
+ outs => [ "false", "true" ],
+ attr => "pn_Cmp pnc",
+ init_attr => "attr->pn_code = pnc;",
+ latency => 2,
units => [ "BRANCH" ],
},
SwitchJmp => {
state => "pinned",
op_flags => "L|X|Y",
- comment => "construct switch",
reg_req => { in => [ "gp" ], out => [ "none" ] },
latency => 3,
units => [ "BRANCH" ],
+ mode => "mode_T",
+ modified_flags => $status_flags
+},
+
+IJmp => {
+ state => "pinned",
+ op_flags => "X",
+ reg_req => { in => [ "gp" ] },
+ emit => '. jmp *%S0',
+ units => [ "BRANCH" ],
+ mode => "mode_X",
},
Const => {
op_flags => "c",
irn_flags => "R",
- comment => "represents an integer constant",
reg_req => { out => [ "gp" ] },
units => [ "GP" ],
+ attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr_type => "ia32_immediate_attr_t",
mode => $mode_gp,
+# depends on the const and is set in ia32_transform
+# modified_flags => $status_flags
},
Unknown_GP => {
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "unknown value",
reg_req => { out => [ "gp_UKNWN" ] },
units => [],
emit => "",
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "unknown value",
reg_req => { out => [ "vfp_UKNWN" ] },
units => [],
emit => "",
- mode => "mode_E"
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
Unknown_XMM => {
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "unknown value",
reg_req => { out => [ "xmm_UKNWN" ] },
units => [],
emit => "",
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "noreg GP value",
reg_req => { out => [ "gp_NOREG" ] },
units => [],
emit => "",
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "noreg VFP value",
reg_req => { out => [ "vfp_NOREG" ] },
units => [],
emit => "",
- mode => "mode_E"
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
NoReg_XMM => {
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "noreg XMM value",
reg_req => { out => [ "xmm_NOREG" ] },
units => [],
emit => "",
state => "pinned",
op_flags => "c",
irn_flags => "I",
- comment => "change floating point control word",
reg_req => { out => [ "fp_cw" ] },
mode => $mode_fpcw,
latency => 3,
FldCW => {
op_flags => "L|F",
- state => "exc_pinned",
- comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
+ ins => [ "base", "index", "mem" ],
latency => 5,
emit => ". fldcw %AM",
mode => $mode_fpcw,
FnstCW => {
op_flags => "L|F",
- state => "exc_pinned",
- comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
- reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "none", "fp_cw" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "fpcw" ],
latency => 5,
emit => ". fnstcw %AM",
mode => "mode_M",
},
Cltd => {
- # we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
- comment => "construct CDQ: sign extend EAX -> EDX:EAX",
- reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
+ # we should not rematrialize this node. It has very strict constraints.
+ reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] },
+ ins => [ "val", "globbered" ],
emit => '. cltd',
- outs => [ "EAX", "EDX" ],
+ mode => $mode_gp,
units => [ "GP" ],
},
# Load / Store
+#
+# Note that we add additional latency values depending on address mode, so a
+# lateny of 0 for load is correct
Load => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
- latency => 3,
- emit => ". mov%SE%ME%.l %AM, %D0",
+ ins => [ "base", "index", "mem" ],
outs => [ "res", "M" ],
+ latency => 0,
+ emit => ". mov%SE%ME%.l %AM, %D0",
units => [ "GP" ],
},
l_Load => {
op_flags => "L|F",
cmp_attr => "return 1;",
- comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
outs => [ "res", "M" ],
arity => 2,
},
op_flags => "L|F",
cmp_attr => "return 1;",
state => "exc_pinned",
- comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
arity => 3,
mode => "mode_M",
},
Store => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
- emit => '. mov%M %binop',
- latency => 3,
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. mov%M %SI3, %AM',
+ latency => 2,
units => [ "GP" ],
mode => "mode_M",
},
Store8Bit => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
- reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
- emit => '. mov%M %binop',
- latency => 3,
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. mov%M %SB3, %AM',
+ latency => 2,
units => [ "GP" ],
mode => "mode_M",
},
Lea => {
irn_flags => "R",
- comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
- reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ ins => [ "base", "index" ],
emit => '. leal %AM, %D0',
latency => 2,
units => [ "GP" ],
mode => $mode_gp,
- modified_flags => [],
+# well this isn't true for Lea, but we often transform Lea back to Add, Inc
+# or Dec, so we set the flag
+ modified_flags => 1,
},
Push => {
- comment => "push on the stack",
- reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
- emit => '. push%M %unop',
+ reg_req => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp", "none" ] },
+ ins => [ "base", "index", "mem", "val", "stack" ],
+ emit => '. push%M %unop3',
outs => [ "stack:I|S", "M" ],
- latency => 3,
+ am => "source,binary",
+ latency => 2,
units => [ "GP" ],
- modified_flags => [],
},
Pop => {
- comment => "pop a gp register from the stack",
- reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
- emit => '. pop%M %unop',
+ reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "esp", "gp", "none" ] },
+ emit => '. pop%M %DAM1',
outs => [ "stack:I|S", "res", "M" ],
- latency => 4,
+ ins => [ "base", "index", "mem", "stack" ],
+ am => "dest,unary",
+ latency => 3, # Pop is more expensive than Push on Athlon
units => [ "GP" ],
- modified_flags => [],
},
Enter => {
- comment => "create stack frame",
- reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
+ reg_req => { in => [ "esp" ], out => [ "ebp", "esp", "none" ] },
emit => '. enter',
outs => [ "frame:I", "stack:I|S", "M" ],
latency => 15,
},
Leave => {
- comment => "destroy stack frame",
reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
emit => '. leave',
outs => [ "frame:I", "stack:I|S" ],
AddSP => {
irn_flags => "I",
- comment => "allocate space on stack",
- reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "none" ] },
+ ins => [ "base", "index", "mem", "stack", "size" ],
+ am => "source,binary",
emit => '. addl %binop',
outs => [ "stack:S", "M" ],
units => [ "GP" ],
},
SubSP => {
- irn_flags => "I",
- comment => "free space on stack",
- reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
- emit => '. subl %binop',
- outs => [ "stack:S", "M" ],
+#irn_flags => "I",
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "gp", "none" ] },
+ ins => [ "base", "index", "mem", "stack", "size" ],
+ am => "source,binary",
+ emit => ". subl %binop\n".
+ ". movl %%esp, %D1",
+ outs => [ "stack:I|S", "addr", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
LdTls => {
irn_flags => "R",
- comment => "get the TLS base address",
reg_req => { out => [ "gp" ] },
units => [ "GP" ],
},
# the int instruction
int => {
- reg_req => { in => [ "none" ], out => [ "none" ] },
- comment => "software interrupt",
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
mode => "mode_M",
- attr => "tarval *tv",
- init_attr => "\tset_ia32_Immop_tarval(res, tv);",
- emit => '. int %C',
+ emit => '. int %SI0',
units => [ "GP" ],
cmp_attr => "return 1;",
},
# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#-----------------------------------------------------------------------------#
+xZero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. xorp%XSD %D1, %D1',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => "mode_E",
+},
+
# commutative operations
xAdd => {
irn_flags => "R",
- comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. add%XXM %binop',
latency => 4,
units => [ "SSE" ],
xMul => {
irn_flags => "R",
- comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. mul%XXM %binop',
latency => 4,
units => [ "SSE" ],
xMax => {
irn_flags => "R",
- comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. max%XXM %binop',
latency => 2,
units => [ "SSE" ],
xMin => {
irn_flags => "R",
- comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. min%XXM %binop',
latency => 2,
units => [ "SSE" ],
xAnd => {
irn_flags => "R",
- comment => "construct SSE And: And(a, b) = a AND b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. andp%XSD %binop',
latency => 3,
units => [ "SSE" ],
xOr => {
irn_flags => "R",
- comment => "construct SSE Or: Or(a, b) = a OR b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. orp%XSD %binop',
units => [ "SSE" ],
mode => "mode_E",
xXor => {
irn_flags => "R",
- comment => "construct SSE Xor: Xor(a, b) = a XOR b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. xorp%XSD %binop',
latency => 3,
units => [ "SSE" ],
xAndNot => {
irn_flags => "R",
- comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. andnp%XSD %binop',
latency => 3,
units => [ "SSE" ],
xSub => {
irn_flags => "R",
- comment => "construct SSE Sub: Sub(a, b) = a - b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. sub%XXM %binop',
latency => 4,
units => [ "SSE" ],
xDiv => {
irn_flags => "R",
- comment => "construct SSE Div: Div(a, b) = a / b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
outs => [ "res", "M" ],
emit => '. div%XXM %binop',
latency => 16,
# other operations
-xCmp => {
+Ucomi => {
irn_flags => "R",
- comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "eflags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "flags" ],
+ am => "source,binary",
+ attr => "int flipped",
+ init_attr => "attr->data.cmp_flipped = flipped;",
+ emit => ' .ucomi%XXM %binop_nores',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
-},
-
-xCondJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
- outs => [ "false", "true" ],
- latency => 5,
- units => [ "SSE" ],
-},
-
-xConst => {
- op_flags => "c",
- irn_flags => "R",
- comment => "represents a SSE constant",
- reg_req => { out => [ "xmm" ] },
- emit => '. mov%XXM %C, %D0',
- latency => 2,
- units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_flags,
+ modified_flags => 1,
},
# Load / Store
xLoad => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+ ins => [ "base", "index", "mem" ],
emit => '. mov%XXM %AM, %D0',
+ attr => "ir_mode *load_mode",
+ init_attr => "attr->ls_mode = load_mode;",
outs => [ "res", "M" ],
- latency => 2,
+ latency => 0,
units => [ "SSE" ],
},
xStore => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
- emit => '. mov%XXM %binop',
- latency => 2,
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. mov%XXM %S3, %AM',
+ latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
xStoreSimple => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
- reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
- ins => [ "base", "index", "val", "mem" ],
- emit => '. mov%XXM %S2, %AM',
- latency => 2,
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. mov%XXM %S3, %AM',
+ latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
CvtSI2SS => {
op_flags => "L|F",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
emit => '. cvtsi2ss %D0, %AM',
latency => 2,
units => [ "SSE" ],
CvtSI2SD => {
op_flags => "L|F",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
- emit => '. cvtsi2sd %unop',
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. cvtsi2sd %unop3',
latency => 2,
units => [ "SSE" ],
mode => $mode_xmm
l_X87toSSE => {
op_flags => "L|F",
- comment => "construct: transfer a value from x87 FPU into a SSE register",
cmp_attr => "return 1;",
arity => 3,
},
l_SSEtoX87 => {
op_flags => "L|F",
- comment => "construct: transfer a value from SSE register to x87 FPU",
cmp_attr => "return 1;",
arity => 3,
},
-GetST0 => {
- op_flags => "L|F",
- irn_flags => "I",
- state => "exc_pinned",
- comment => "store ST0 onto stack",
- reg_req => { in => [ "gp", "gp", "none" ] },
- emit => '. fstp%XM %AM',
- latency => 4,
- units => [ "SSE" ],
- mode => "mode_M",
-},
-
-SetST0 => {
- op_flags => "L|F",
- irn_flags => "I",
- state => "exc_pinned",
- comment => "load ST0 from stack",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] },
- ins => [ "base", "index", "mem" ],
- emit => '. fld%XM %AM',
- outs => [ "res", "M" ],
- latency => 2,
- units => [ "SSE" ],
-},
-
# CopyB
CopyB => {
op_flags => "F|H",
state => "pinned",
- comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
outs => [ "DST", "SRC", "CNT", "M" ],
units => [ "GP" ],
- modified_flags => [ "DF" ]
+# we don't care about this flag, so no need to mark this node
+# modified_flags => [ "DF" ]
},
CopyB_i => {
op_flags => "F|H",
state => "pinned",
- comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
outs => [ "DST", "SRC", "M" ],
units => [ "GP" ],
- modified_flags => [ "DF" ]
+# we don't care about this flag, so no need to mark this node
+# modified_flags => [ "DF" ]
},
# Conversions
Conv_I2I => {
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
- comment => "construct Conv Int -> Int",
- units => [ "GP" ],
- mode => $mode_gp,
- modified_flags => $status_flags
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ units => [ "GP" ],
+ attr => "ir_mode *smaller_mode",
+ init_attr => "attr->ls_mode = smaller_mode;",
+ mode => $mode_gp,
},
Conv_I2I8Bit => {
- reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
- comment => "construct Conv Int -> Int",
- units => [ "GP" ],
- mode => $mode_gp,
- modified_flags => $status_flags
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "gp", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ units => [ "GP" ],
+ attr => "ir_mode *smaller_mode",
+ init_attr => "attr->ls_mode = smaller_mode;",
+ mode => $mode_gp,
},
Conv_I2FP => {
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
- comment => "construct Conv Int -> Floating Point",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
latency => 10,
units => [ "SSE" ],
mode => "mode_E",
},
Conv_FP2I => {
- reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
- comment => "construct Conv Floating Point -> Int",
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "gp", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
latency => 10,
units => [ "SSE" ],
mode => $mode_gp,
},
Conv_FP2FP => {
- reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
- comment => "construct Conv Floating Point -> Floating Point",
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "xmm", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
latency => 8,
units => [ "SSE" ],
mode => "mode_E",
},
-CmpCMov => {
- irn_flags => "R",
- comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
- reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-PsiCondCMov => {
- irn_flags => "R",
- comment => "check if Psi condition tree evaluates to true and move result accordingly",
- reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-xCmpCMov => {
- irn_flags => "R",
- comment => "construct Conditional Move: SSE Compare + int CMov ",
- reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
- latency => 5,
- units => [ "SSE" ],
- mode => $mode_gp,
-},
-
-vfCmpCMov => {
- irn_flags => "R",
- comment => "construct Conditional Move: x87 Compare + int CMov",
- reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
- latency => 10,
- units => [ "VFP" ],
- mode => $mode_gp,
-},
-
-CmpSet => {
- irn_flags => "R",
- comment => "construct Set: Set(sel) == sel ? 1 : 0",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-PsiCondSet => {
- irn_flags => "R",
- comment => "check if Psi condition tree evaluates to true and set result accordingly",
- reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-xCmpSet => {
- irn_flags => "R",
- comment => "construct Set: SSE Compare + int Set",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
- latency => 5,
- units => [ "SSE" ],
- mode => $mode_gp,
-},
-
-vfCmpSet => {
- irn_flags => "R",
- comment => "construct Set: x87 Compare + int Set",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
- latency => 10,
- units => [ "VFP" ],
- mode => $mode_gp,
-},
-
-vfCMov => {
- irn_flags => "R",
- comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
- reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
- latency => 10,
- units => [ "VFP" ],
- mode => "mode_E",
-},
-
#----------------------------------------------------------#
# _ _ _ __ _ _ #
# (_) | | | | / _| | | | #
vfadd => {
irn_flags => "R",
- comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfmul => {
irn_flags => "R",
- comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
l_vfmul => {
op_flags => "C",
cmp_attr => "return 1;",
- comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
arity => 2,
},
vfsub => {
irn_flags => "R",
- comment => "virtual fp Sub: Sub(a, b) = a - b",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
l_vfsub => {
cmp_attr => "return 1;",
- comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
arity => 2,
},
vfdiv => {
- comment => "virtual fp Div: Div(a, b) = a / b",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
outs => [ "res", "M" ],
latency => 20,
units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
},
l_vfdiv => {
cmp_attr => "return 1;",
- comment => "lowered virtual fp Div: Div(a, b) = a / b",
outs => [ "res", "M" ],
arity => 2,
},
vfprem => {
- comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
latency => 20,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
l_vfprem => {
cmp_attr => "return 1;",
- comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
arity => 2,
},
vfabs => {
irn_flags => "R",
- comment => "virtual fp Abs: Abs(a) = |a|",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ ins => [ "value" ],
latency => 2,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfchs => {
irn_flags => "R",
- comment => "virtual fp Chs: Chs(a) = -a",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ ins => [ "value" ],
latency => 2,
units => [ "VFP" ],
mode => "mode_E",
-},
-
-vfsin => {
- irn_flags => "R",
- comment => "virtual fp Sin: Sin(a) = sin(a)",
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
- latency => 150,
- units => [ "VFP" ],
- mode => "mode_E",
-},
-
-vfcos => {
- irn_flags => "R",
- comment => "virtual fp Cos: Cos(a) = cos(a)",
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
- latency => 150,
- units => [ "VFP" ],
- mode => "mode_E",
-},
-
-vfsqrt => {
- irn_flags => "R",
- comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
- latency => 30,
- units => [ "VFP" ],
- mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
# virtual Load and Store
vfld => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "mem" ],
outs => [ "res", "M" ],
+ attr => "ir_mode *load_mode",
+ init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
},
vfst => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
- reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ attr => "ir_mode *store_mode",
+ init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
units => [ "VFP" ],
mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
},
# Conversions
vfild => {
- comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
+ state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
outs => [ "res", "M" ],
+ ins => [ "base", "index", "mem" ],
latency => 4,
units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
},
l_vfild => {
cmp_attr => "return 1;",
- comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
outs => [ "res", "M" ],
arity => 2,
},
vfist => {
- comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
- reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] },
+ ins => [ "base", "index", "mem", "val", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
},
l_vfist => {
cmp_attr => "return 1;",
- comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ state => "exc_pinned",
arity => 3,
mode => "mode_M",
},
vfldz => {
irn_flags => "R",
- comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfld1 => {
irn_flags => "R",
- comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfldpi => {
irn_flags => "R",
- comment => "virtual fp Load pi: Ld pi -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfldln2 => {
irn_flags => "R",
- comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfldlg2 => {
irn_flags => "R",
- comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfldl2t => {
irn_flags => "R",
- comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
vfldl2e => {
irn_flags => "R",
- comment => "virtual fp Load ld e: Ld ld e -> reg",
reg_req => { out => [ "vfp" ] },
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
},
-vfConst => {
- op_flags => "c",
- irn_flags => "R",
-# init_attr => " set_ia32_ls_mode(res, mode);",
- comment => "represents a virtual floating point constant",
- reg_req => { out => [ "vfp" ] },
+# other
+
+vFucomFnstsw => {
+# we can't allow to rematerialize this node so we don't have
+# accidently produce Phi(Fucom, Fucom(flipped))
+# irn_flags => "R",
+ reg_req => { in => [ "vfp", "vfp" ], out => [ "eax" ] },
+ ins => [ "left", "right" ],
+ outs => [ "flags" ],
+ am => "source,binary",
+ attr => "int flipped",
+ init_attr => "attr->attr.data.cmp_flipped = flipped;",
latency => 3,
units => [ "VFP" ],
- mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+ mode => $mode_gp
},
-# other
-
-vfCondJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- comment => "represents a virtual floating point compare",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
- outs => [ "false", "true", "temp_reg_eax" ],
- latency => 10,
- units => [ "VFP" ],
+Sahf => {
+ irn_flags => "R",
+ reg_req => { in => [ "eax" ], out => [ "eflags" ] },
+ ins => [ "val" ],
+ outs => [ "flags" ],
+ emit => '. sahf',
+ units => [ "GP" ],
+ mode => $mode_flags,
},
#------------------------------------------------------------------------#
fadd => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
reg_req => { },
emit => '. fadd%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
faddp => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
reg_req => { },
- emit => '. faddp %x87_binop',
+ emit => '. faddp%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fmul => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
reg_req => { },
emit => '. fmul%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fmulp => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
reg_req => { },
- emit => '. fmulp %x87_binop',,
+ emit => '. fmulp%XM %x87_binop',,
+ attr_type => "ia32_x87_attr_t",
},
fsub => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Sub: Sub(a, b) = a - b",
reg_req => { },
emit => '. fsub%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fsubp => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Sub: Sub(a, b) = a - b",
reg_req => { },
# see note about gas bugs
- emit => '. fsubrp %x87_binop',
+ emit => '. fsubrp%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fsubr => {
op_flags => "R",
rd_constructor => "NONE",
irn_flags => "R",
- comment => "x87 fp SubR: SubR(a, b) = b - a",
reg_req => { },
emit => '. fsubr%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fsubrp => {
op_flags => "R",
rd_constructor => "NONE",
irn_flags => "R",
- comment => "x87 fp SubR: SubR(a, b) = b - a",
reg_req => { },
# see note about gas bugs
- emit => '. fsubp %x87_binop',
+ emit => '. fsubp%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fprem => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
reg_req => { },
emit => '. fprem1',
+ attr_type => "ia32_x87_attr_t",
},
# this node is just here, to keep the simulator running
fpremp => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
reg_req => { },
emit => '. fprem1',
+ attr_type => "ia32_x87_attr_t",
},
fdiv => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Div: Div(a, b) = a / b",
reg_req => { },
emit => '. fdiv%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fdivp => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Div: Div(a, b) = a / b",
reg_req => { },
# see note about gas bugs
- emit => '. fdivrp %x87_binop',
+ emit => '. fdivrp%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fdivr => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp DivR: DivR(a, b) = b / a",
reg_req => { },
emit => '. fdivr%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fdivrp => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp DivR: DivR(a, b) = b / a",
reg_req => { },
# see note about gas bugs
- emit => '. fdivp %x87_binop',
+ emit => '. fdivp%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
},
fabs => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp Abs: Abs(a) = |a|",
reg_req => { },
emit => '. fabs',
+ attr_type => "ia32_x87_attr_t",
},
fchs => {
op_flags => "R|K",
rd_constructor => "NONE",
- comment => "x87 fp Chs: Chs(a) = -a",
reg_req => { },
emit => '. fchs',
-},
-
-fsin => {
- op_flags => "R",
- rd_constructor => "NONE",
- comment => "x87 fp Sin: Sin(a) = sin(a)",
- reg_req => { },
- emit => '. fsin',
-},
-
-fcos => {
- op_flags => "R",
- rd_constructor => "NONE",
- comment => "x87 fp Cos: Cos(a) = cos(a)",
- reg_req => { },
- emit => '. fcos',
-},
-
-fsqrt => {
- op_flags => "R",
- rd_constructor => "NONE",
- comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
- reg_req => { },
- emit => '. fsqrt $',
+ attr_type => "ia32_x87_attr_t",
},
# x87 Load and Store
rd_constructor => "NONE",
op_flags => "R|L|F",
state => "exc_pinned",
- comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
reg_req => { },
emit => '. fld%XM %AM',
+ attr_type => "ia32_x87_attr_t",
},
fst => {
rd_constructor => "NONE",
op_flags => "R|L|F",
state => "exc_pinned",
- comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
reg_req => { },
emit => '. fst%XM %AM',
mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
},
fstp => {
rd_constructor => "NONE",
op_flags => "R|L|F",
state => "exc_pinned",
- comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
reg_req => { },
emit => '. fstp%XM %AM',
mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
},
# Conversions
fild => {
op_flags => "R",
rd_constructor => "NONE",
- comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
reg_req => { },
- emit => '. fild%XM %AM',
+ emit => '. fild%M %AM',
+ attr_type => "ia32_x87_attr_t",
},
fist => {
op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
- comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
reg_req => { },
- emit => '. fist%XM %AM',
+ emit => '. fist%M %AM',
mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
},
fistp => {
op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
- comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
reg_req => { },
- emit => '. fistp%XM %AM',
+ emit => '. fistp%M %AM',
mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
},
# constants
fldz => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
reg_req => { },
emit => '. fldz',
+ attr_type => "ia32_x87_attr_t",
},
fld1 => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
reg_req => { },
emit => '. fld1',
+ attr_type => "ia32_x87_attr_t",
},
fldpi => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load pi: Ld pi -> reg",
reg_req => { },
emit => '. fldpi',
+ attr_type => "ia32_x87_attr_t",
},
fldln2 => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
reg_req => { },
emit => '. fldln2',
+ attr_type => "ia32_x87_attr_t",
},
fldlg2 => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
reg_req => { },
emit => '. fldlg2',
+ attr_type => "ia32_x87_attr_t",
},
fldl2t => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
reg_req => { },
emit => '. fldll2t',
+ attr_type => "ia32_x87_attr_t",
},
fldl2e => {
op_flags => "R|c|K",
irn_flags => "R",
- comment => "x87 fp Load ld e: Ld ld e -> reg",
reg_req => { },
emit => '. fldl2e',
+ attr_type => "ia32_x87_attr_t",
},
# fxch, fpush, fpop
fxch => {
op_flags => "R|K",
- comment => "x87 stack exchange",
reg_req => { },
cmp_attr => "return 1;",
emit => '. fxch %X0',
+ attr_type => "ia32_x87_attr_t",
},
fpush => {
op_flags => "R|K",
- comment => "x87 stack push",
reg_req => {},
cmp_attr => "return 1;",
emit => '. fld %X0',
+ attr_type => "ia32_x87_attr_t",
},
fpushCopy => {
op_flags => "R",
- comment => "x87 stack push",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
cmp_attr => "return 1;",
emit => '. fld %X0',
+ attr_type => "ia32_x87_attr_t",
},
fpop => {
- op_flags => "R|K",
- comment => "x87 stack pop",
+ op_flags => "K",
reg_req => { },
cmp_attr => "return 1;",
emit => '. fstp %X0',
+ attr_type => "ia32_x87_attr_t",
},
-# compare
-
-fcomJmp => {
- op_flags => "L|X|Y",
- comment => "floating point compare",
+ffreep => {
+ op_flags => "K",
reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. ffreep %X0',
+ attr_type => "ia32_x87_attr_t",
},
-fcompJmp => {
- op_flags => "L|X|Y",
- comment => "floating point compare and pop",
+emms => {
+ op_flags => "K",
reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. emms',
+ attr_type => "ia32_x87_attr_t",
},
-fcomppJmp => {
- op_flags => "L|X|Y",
- comment => "floating point compare and pop twice",
+femms => {
+ op_flags => "K",
reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. femms',
+ attr_type => "ia32_x87_attr_t",
},
-fcomrJmp => {
- op_flags => "L|X|Y",
- comment => "floating point compare reverse",
+# compare
+
+FucomFnstsw => {
+ op_flags => "R",
reg_req => { },
+ emit => ". fucom %X1\n".
+ ". fnstsw",
+ attr_type => "ia32_x87_attr_t",
},
-fcomrpJmp => {
- op_flags => "L|X|Y",
- comment => "floating point compare reverse and pop",
+FucompFnstsw => {
+ op_flags => "R",
reg_req => { },
+ emit => ". fucomp %X1\n".
+ ". fnstsw",
+ attr_type => "ia32_x87_attr_t",
},
-fcomrppJmp => {
- op_flags => "L|X|Y",
- comment => "floating point compare reverse and pop twice",
+FucomppFnstsw => {
+ op_flags => "R",
reg_req => { },
+ emit => ". fucompp\n".
+ ". fnstsw",
+ attr_type => "ia32_x87_attr_t",
},
xxLoad => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
emit => '. movdqu %D0, %AM',
outs => [ "res", "M" ],
xxStore => {
op_flags => "L|F",
state => "exc_pinned",
- comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
emit => '. movdqu %binop',
units => [ "SSE" ],
mode => "mode_M",