* @author Matthias Braun, Christian Wuerdig
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include "irnode.h"
#include "irprog_t.h"
#include "tv.h"
#include "irgmod.h"
#include "irgwalk.h"
-#include "height.h"
+#include "heights.h"
#include "irbitset.h"
#include "irprintf.h"
+#include "irdump.h"
#include "error.h"
#include "../be_t.h"
#include "../beabi.h"
-#include "../benode_t.h"
-#include "../besched_t.h"
+#include "../benode.h"
+#include "../besched.h"
#include "../bepeephole.h"
#include "ia32_new_nodes.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-static const arch_env_t *arch_env;
-static ia32_code_gen_t *cg;
-
static void copy_mark(const ir_node *old, ir_node *new)
{
if (is_ia32_is_reload(old))
produces_flag_zero : produces_no_flag;
}
-/**
- * If the given node has not mode_T, creates a mode_T version (with a result Proj).
- *
- * @param node the node to change
- *
- * @return the new mode_T node (if the mode was changed) or node itself
- */
-static ir_node *turn_into_mode_t(ir_node *node)
-{
- ir_node *block;
- ir_node *res_proj;
- ir_node *new_node;
- const arch_register_t *reg;
-
- if(get_irn_mode(node) == mode_T)
- return node;
-
- assert(get_irn_mode(node) == mode_Iu);
-
- new_node = exact_copy(node);
- set_irn_mode(new_node, mode_T);
-
- block = get_nodes_block(new_node);
- res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
- pn_ia32_res);
-
- reg = arch_get_irn_register(arch_env, node);
- arch_set_irn_register(arch_env, res_proj, reg);
-
- sched_add_before(node, new_node);
- be_peephole_exchange(node, res_proj);
- return new_node;
-}
-
/**
* Replace Cmp(x, 0) by a Test(x, x)
*/
static void peephole_ia32_Cmp(ir_node *const node)
{
ir_node *right;
+ ir_graph *irg;
ia32_immediate_attr_t const *imm;
dbg_info *dbgi;
- ir_graph *irg;
ir_node *block;
ir_node *noreg;
ir_node *nomem;
return;
dbgi = get_irn_dbg_info(node);
- irg = current_ir_graph;
+ irg = get_irn_irg(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
- nomem = get_irg_no_mem(irg);
+ noreg = ia32_new_NoReg_gp(irg);
+ nomem = get_irg_no_mem(current_ir_graph);
op = get_irn_n(node, n_ia32_Cmp_left);
attr = get_irn_generic_attr(node);
ins_permuted = attr->data.ins_permuted;
cmp_unsigned = attr->data.cmp_unsigned;
if (is_ia32_Cmp(node)) {
- test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
+ test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
op, op, ins_permuted, cmp_unsigned);
} else {
- test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
+ test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
op, op, ins_permuted, cmp_unsigned);
}
set_ia32_ls_mode(test, get_ia32_ls_mode(node));
- reg = arch_get_irn_register(arch_env, node);
- arch_set_irn_register(arch_env, test, reg);
+ reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
+ arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
foreach_out_edge_safe(node, edge, tmp) {
ir_node *const user = get_edge_src_irn(edge);
/**
* Peephole optimization for Test instructions.
- * We can remove the Test, if a zero flags was produced which is still
- * live.
+ * - Remove the Test, if an appropriate flag was produced which is still live
+ * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
*/
static void peephole_ia32_Test(ir_node *node)
{
- ir_node *left = get_irn_n(node, n_ia32_Test_left);
- ir_node *right = get_irn_n(node, n_ia32_Test_right);
- ir_node *flags_proj;
- ir_node *block;
- ir_mode *flags_mode;
- int pn = pn_ia32_res;
- ir_node *schedpoint;
- const ir_edge_t *edge;
+ ir_node *left = get_irn_n(node, n_ia32_Test_left);
+ ir_node *right = get_irn_n(node, n_ia32_Test_right);
assert(n_ia32_Test_left == n_ia32_Test8Bit_left
&& n_ia32_Test_right == n_ia32_Test8Bit_right);
- /* we need a test for 0 */
- if(left != right)
- return;
+ if (left == right) { /* we need a test for 0 */
+ ir_node *block = get_nodes_block(node);
+ int pn = pn_ia32_res;
+ ir_node *flags_proj;
+ ir_mode *flags_mode;
+ ir_node *schedpoint;
+ const ir_edge_t *edge;
- block = get_nodes_block(node);
- if(get_nodes_block(left) != block)
- return;
+ if (get_nodes_block(left) != block)
+ return;
- if(is_Proj(left)) {
- pn = get_Proj_proj(left);
- left = get_Proj_pred(left);
- }
+ if (is_Proj(left)) {
+ pn = get_Proj_proj(left);
+ left = get_Proj_pred(left);
+ }
- /* happens rarely, but if it does code will panic' */
- if (is_ia32_Unknown_GP(left))
- return;
+ /* walk schedule up and abort when we find left or some other node
+ * destroys the flags */
+ schedpoint = node;
+ for (;;) {
+ schedpoint = sched_prev(schedpoint);
+ if (schedpoint == left)
+ break;
+ if (arch_irn_is(schedpoint, modify_flags))
+ return;
+ if (schedpoint == block)
+ panic("couldn't find left");
+ }
- /* walk schedule up and abort when we find left or some other node destroys
- the flags */
- schedpoint = node;
- for (;;) {
- schedpoint = sched_prev(schedpoint);
- if (schedpoint == left)
- break;
- if (arch_irn_is(arch_env, schedpoint, modify_flags))
- return;
- if (schedpoint == block)
- panic("couldn't find left");
- }
+ /* make sure only Lg/Eq tests are used */
+ foreach_out_edge(node, edge) {
+ ir_node *user = get_edge_src_irn(edge);
+ int pnc = get_ia32_condcode(user);
- /* make sure only Lg/Eq tests are used */
- foreach_out_edge(node, edge) {
- ir_node *user = get_edge_src_irn(edge);
- int pnc = get_ia32_condcode(user);
+ if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
+ return;
+ }
+ }
- if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
- return;
+ switch (produces_test_flag(left, pn)) {
+ case produces_flag_zero:
+ break;
+
+ case produces_flag_carry:
+ foreach_out_edge(node, edge) {
+ ir_node *user = get_edge_src_irn(edge);
+ int pnc = get_ia32_condcode(user);
+
+ switch (pnc) {
+ case pn_Cmp_Eq: pnc = ia32_pn_Cmp_not_carry; break;
+ case pn_Cmp_Lg: pnc = ia32_pn_Cmp_carry; break;
+ default: panic("unexpected pn");
+ }
+ set_ia32_condcode(user, pnc);
+ }
+ break;
+
+ default:
+ return;
}
- }
- switch (produces_test_flag(left, pn)) {
- case produces_flag_zero:
- break;
+ if (get_irn_mode(left) != mode_T) {
+ set_irn_mode(left, mode_T);
- case produces_flag_carry:
- foreach_out_edge(node, edge) {
- ir_node *user = get_edge_src_irn(edge);
- int pnc = get_ia32_condcode(user);
+ /* If there are other users, reroute them to result proj */
+ if (get_irn_n_edges(left) != 2) {
+ ir_node *res = new_r_Proj(left, mode_Iu, pn_ia32_res);
- switch (pnc) {
- case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
- case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
- default: panic("unexpected pn");
- }
- set_ia32_condcode(user, pnc);
+ edges_reroute(left, res, current_ir_graph);
+ /* Reattach the result proj to left */
+ set_Proj_pred(res, left);
}
- break;
+ }
- default:
- return;
- }
+ flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
+ flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags);
+ arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
+
+ assert(get_irn_mode(node) != mode_T);
+
+ be_peephole_exchange(node, flags_proj);
+ } else if (is_ia32_Immediate(right)) {
+ ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
+ unsigned offset;
- left = turn_into_mode_t(left);
+ /* A test with a symconst is rather strange, but better safe than sorry */
+ if (imm->symconst != NULL)
+ return;
- flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
- flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
- pn_ia32_flags);
- arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
+ offset = imm->offset;
+ if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ ia32_attr_t *const attr = get_irn_generic_attr(node);
+
+ if ((offset & 0xFFFFFF00) == 0) {
+ /* attr->am_offs += 0; */
+ } else if ((offset & 0xFFFF00FF) == 0) {
+ ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
+ set_irn_n(node, n_ia32_Test_right, imm);
+ attr->am_offs += 1;
+ } else if ((offset & 0xFF00FFFF) == 0) {
+ ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
+ set_irn_n(node, n_ia32_Test_right, imm);
+ attr->am_offs += 2;
+ } else if ((offset & 0x00FFFFFF) == 0) {
+ ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
+ set_irn_n(node, n_ia32_Test_right, imm);
+ attr->am_offs += 3;
+ } else {
+ return;
+ }
+ } else if (offset < 256) {
+ arch_register_t const* const reg = arch_get_irn_register(left);
- assert(get_irn_mode(node) != mode_T);
+ if (reg != &ia32_gp_regs[REG_EAX] &&
+ reg != &ia32_gp_regs[REG_EBX] &&
+ reg != &ia32_gp_regs[REG_ECX] &&
+ reg != &ia32_gp_regs[REG_EDX]) {
+ return;
+ }
+ } else {
+ return;
+ }
- be_peephole_exchange(node, flags_proj);
+ /* Technically we should build a Test8Bit because of the register
+ * constraints, but nobody changes registers at this point anymore. */
+ set_ia32_ls_mode(node, mode_Bu);
+ }
}
/**
* conditional jump or directly preceded by other jump instruction.
* Can be avoided by placing a Rep prefix before the return.
*/
-static void peephole_ia32_Return(ir_node *node) {
+static void peephole_ia32_Return(ir_node *node)
+{
ir_node *block, *irn;
if (!ia32_cg_config.use_pad_return)
/* the return node itself, ignore */
continue;
case iro_Start:
- case beo_RegParams:
+ case beo_Start:
case beo_Barrier:
/* ignore no code generated */
continue;
/* walk through the Stores and create Pushs for them */
block = get_nodes_block(irn);
spmode = get_irn_mode(irn);
- irg = cg->irg;
+ irg = get_irn_irg(irn);
for (; i >= 0; --i) {
const arch_register_t *spreg;
ir_node *push;
ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i];
- ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
- spreg = arch_get_irn_register(cg->arch_env, curr_sp);
+ spreg = arch_get_irn_register(curr_sp);
- push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
+ push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
copy_mark(store, push);
if (first_push == NULL)
first_push = push;
- sched_add_after(curr_sp, push);
+ sched_add_after(skip_Proj(curr_sp), push);
/* create stackpointer Proj */
- curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
- arch_set_irn_register(cg->arch_env, curr_sp, spreg);
+ curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
+ arch_set_irn_register(curr_sp, spreg);
/* create memory Proj */
- mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
+ mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
/* use the memproj now */
be_peephole_exchange(store, mem_proj);
}
#if 0
+/**
+ * Creates a Push instruction before the given schedule point.
+ *
+ * @param dbgi debug info
+ * @param block the block
+ * @param stack the previous stack value
+ * @param schedpoint the new node is added before this node
+ * @param reg the register to pop
+ *
+ * @return the new stack value
+ */
+static ir_node *create_push(dbg_info *dbgi, ir_node *block,
+ ir_node *stack, ir_node *schedpoint)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+
+ ir_node *val = ia32_new_NoReg_gp(cg);
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
+ sched_add_before(schedpoint, push);
+
+ stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
+ arch_set_irn_register(stack, esp);
+
+ return stack;
+}
+
static void peephole_store_incsp(ir_node *store)
{
dbg_info *dbgi;
ir_node *node;
ir_node *block;
- ir_node *noref;
+ ir_node *noreg;
ir_node *mem;
ir_node *push;
ir_node *val;
+ ir_node *base;
+ ir_node *index;
ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
if (!be_is_IncSP(am_base)
|| get_nodes_block(am_base) != get_nodes_block(store))
|| get_ia32_op_type(node) == ia32_AddrModeD)) {
int node_offset = get_ia32_am_offs_int(node);
ir_mode *node_ls_mode = get_ia32_ls_mode(node);
- int node_size = get_mode_size_bytes(node);
+ int node_size = get_mode_size_bytes(node_ls_mode);
/* overlapping with our position? abort */
if (node_offset < my_offset + my_store_size
&& node_offset + node_size >= my_offset)
dbgi = get_irn_dbg_info(store);
block = get_nodes_block(store);
noreg = ia32_new_NoReg_gp(cg);
- val = get_ia32_
+ val = get_irn_n(store, n_ia32_Store_val);
- push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem,
+ push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
create_push(dbgi, current_ir_graph, block, am_base, store);
}
/**
* Return true if a mode can be stored in the GP register set
*/
-static INLINE int mode_needs_gp_reg(ir_mode *mode) {
+static inline int mode_needs_gp_reg(ir_mode *mode)
+{
if (mode == mode_fpcw)
return 0;
if (get_mode_size_bits(mode) > 32)
/* not a GP copy, ignore */
continue;
}
- dreg = arch_get_irn_register(arch_env, node);
- sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
+ dreg = arch_get_irn_register(node);
+ sreg = arch_get_irn_register(be_get_Copy_op(node));
if (regmask & copymask & (1 << sreg->index)) {
break;
}
if (loads[loadslot] != NULL)
break;
- dreg = arch_get_irn_register(arch_env, node);
+ dreg = arch_irn_get_register(node, pn_ia32_Load_res);
if (regmask & (1 << dreg->index)) {
/* this register is already used */
break;
/* create a new IncSP if needed */
block = get_nodes_block(irn);
- irg = cg->irg;
+ irg = get_irn_irg(irn);
if (inc_ofs > 0) {
- pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
+ pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
sched_add_before(irn, pred_sp);
}
const arch_register_t *reg;
mem = get_irn_n(load, n_ia32_mem);
- reg = arch_get_irn_register(arch_env, load);
+ reg = arch_irn_get_register(load, pn_ia32_Load_res);
- pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
- arch_set_irn_register(arch_env, pop, reg);
+ pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
+ arch_irn_set_register(pop, pn_ia32_Load_res, reg);
copy_mark(load, pop);
/* create stackpointer Proj */
- pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
- arch_set_irn_register(arch_env, pred_sp, esp);
+ pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
+ arch_set_irn_register(pred_sp, esp);
sched_add_before(irn, pop);
{
int i;
- for(i = 0; i < N_ia32_gp_REGS; ++i) {
+ for (i = 0; i < N_ia32_gp_REGS; ++i) {
const arch_register_t *reg = &ia32_gp_regs[i];
- if(arch_register_type_is(reg, ignore))
+ if (arch_register_type_is(reg, ignore))
continue;
- if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
+ if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
return &ia32_gp_regs[i];
}
* Creates a Pop instruction before the given schedule point.
*
* @param dbgi debug info
- * @param irg the graph
* @param block the block
* @param stack the previous stack value
* @param schedpoint the new node is added before this node
*
* @return the new stack value
*/
-static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
+static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
ir_node *stack, ir_node *schedpoint,
const arch_register_t *reg)
{
ir_node *val;
ir_node *in[1];
- pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
+ pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack);
- stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
- arch_set_irn_register(arch_env, stack, esp);
- val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
- arch_set_irn_register(arch_env, val, reg);
+ stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
+ arch_set_irn_register(stack, esp);
+ val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
+ arch_set_irn_register(val, reg);
sched_add_before(schedpoint, pop);
in[0] = val;
- keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+ keep = be_new_Keep(block, 1, in);
sched_add_before(schedpoint, keep);
return stack;
}
-/**
- * Creates a Push instruction before the given schedule point.
- *
- * @param dbgi debug info
- * @param irg the graph
- * @param block the block
- * @param stack the previous stack value
- * @param schedpoint the new node is added before this node
- * @param reg the register to pop
- *
- * @return the new stack value
- */
-static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
- ir_node *stack, ir_node *schedpoint)
-{
- const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
-
- ir_node *val = ia32_new_Unknown_gp(cg);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *nomem = get_irg_no_mem(irg);
- ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
- sched_add_before(schedpoint, push);
-
- stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
- arch_set_irn_register(arch_env, stack, esp);
-
- return stack;
-}
-
/**
* Optimize an IncSp by replacing it with Push/Pop.
*/
{
const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
const arch_register_t *reg;
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi;
ir_node *block;
ir_node *stack;
/* transform Load->IncSP combinations to Pop where possible */
peephole_Load_IncSP_to_pop(node);
- if (arch_get_irn_register(arch_env, node) != esp)
+ if (arch_get_irn_register(node) != esp)
return;
/* replace IncSP -4 by Pop freereg when possible */
block = get_nodes_block(node);
stack = be_get_IncSP_pred(node);
- stack = create_pop(dbgi, irg, block, stack, node, reg);
+ stack = create_pop(dbgi, block, stack, node, reg);
if (offset == -8) {
- stack = create_pop(dbgi, irg, block, stack, node, reg);
+ stack = create_pop(dbgi, block, stack, node, reg);
}
} else {
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
stack = be_get_IncSP_pred(node);
- stack = create_push(dbgi, irg, block, stack, node);
+ stack = new_bd_ia32_PushEax(dbgi, block, stack);
+ arch_set_irn_register(stack, esp);
+ sched_add_before(node, stack);
if (offset == +8) {
- stack = create_push(dbgi, irg, block, stack, node);
+ stack = new_bd_ia32_PushEax(dbgi, block, stack);
+ arch_set_irn_register(stack, esp);
+ sched_add_before(node, stack);
}
}
{
const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
const arch_register_t *reg;
- ir_graph *irg = current_ir_graph;
ir_node *block;
dbg_info *dbgi;
- ir_node *produceval;
ir_node *xor;
- ir_node *noreg;
/* try to transform a mov 0, reg to xor reg reg */
if (attr->offset != 0 || attr->symconst != NULL)
if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
return;
- reg = arch_get_irn_register(arch_env, node);
+ reg = arch_get_irn_register(node);
assert(be_peephole_get_reg_value(reg) == NULL);
/* create xor(produceval, produceval) */
- block = get_nodes_block(node);
- dbgi = get_irn_dbg_info(node);
- produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
- arch_set_irn_register(arch_env, produceval, reg);
-
- noreg = ia32_new_NoReg_gp(cg);
- xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
- produceval, produceval);
- arch_set_irn_register(arch_env, xor, reg);
+ block = get_nodes_block(node);
+ dbgi = get_irn_dbg_info(node);
+ xor = new_bd_ia32_Xor0(dbgi, block);
+ arch_set_irn_register(xor, reg);
- sched_add_before(node, produceval);
sched_add_before(node, xor);
copy_mark(node, xor);
be_peephole_exchange(node, xor);
}
-static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
+static inline int is_noreg(const ir_node *node)
{
- return node == cg->noreg_gp;
+ return is_ia32_NoReg_GP(node);
}
-static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
+ir_node *ia32_immediate_from_long(long val)
{
ir_graph *irg = current_ir_graph;
ir_node *start_block = get_irg_start_block(irg);
- ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
- 0, val);
- arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
+ ir_node *immediate
+ = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
+ arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
return immediate;
}
-static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
- const ir_node *node)
+static ir_node *create_immediate_from_am(const ir_node *node)
{
- ir_graph *irg = get_irn_irg(node);
ir_node *block = get_nodes_block(node);
int offset = get_ia32_am_offs_int(node);
int sc_sign = is_ia32_am_sc_sign(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
ir_entity *entity = get_ia32_am_sc(node);
ir_node *res;
- res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
- arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
+ res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
+ offset);
+ arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
return res;
}
*/
static void peephole_ia32_Lea(ir_node *node)
{
- const arch_env_t *arch_env = cg->arch_env;
- ir_graph *irg = current_ir_graph;
+ ir_graph *irg;
ir_node *base;
ir_node *index;
const arch_register_t *base_reg;
assert(is_ia32_Lea(node));
- /* we can only do this if are allowed to globber the flags */
- if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
+ /* we can only do this if it is allowed to clobber the flags */
+ if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
return;
base = get_irn_n(node, n_ia32_Lea_base);
index = get_irn_n(node, n_ia32_Lea_index);
- if(is_noreg(cg, base)) {
+ if (is_noreg(base)) {
base = NULL;
base_reg = NULL;
} else {
- base_reg = arch_get_irn_register(arch_env, base);
+ base_reg = arch_get_irn_register(base);
}
- if(is_noreg(cg, index)) {
+ if (is_noreg(index)) {
index = NULL;
index_reg = NULL;
} else {
- index_reg = arch_get_irn_register(arch_env, index);
+ index_reg = arch_get_irn_register(index);
}
- if(base == NULL && index == NULL) {
+ if (base == NULL && index == NULL) {
/* we shouldn't construct these in the first place... */
#ifdef DEBUG_libfirm
ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
return;
}
- out_reg = arch_get_irn_register(arch_env, node);
+ out_reg = arch_get_irn_register(node);
scale = get_ia32_am_scale(node);
assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
/* check if we have immediates values (frame entities should already be
* expressed in the offsets) */
- if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
+ if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
has_immediates = 1;
} else {
has_immediates = 0;
/* we can transform leas where the out register is the same as either the
* base or index register back to an Add or Shl */
- if(out_reg == base_reg) {
- if(index == NULL) {
+ if (out_reg == base_reg) {
+ if (index == NULL) {
#ifdef DEBUG_libfirm
- if(!has_immediates) {
+ if (!has_immediates) {
ir_fprintf(stderr, "Optimisation warning: found lea which is "
"just a copy\n");
}
op1 = base;
goto make_add_immediate;
}
- if(scale == 0 && !has_immediates) {
+ if (scale == 0 && !has_immediates) {
op1 = base;
op2 = index;
goto make_add;
}
/* can't create an add */
return;
- } else if(out_reg == index_reg) {
- if(base == NULL) {
- if(has_immediates && scale == 0) {
+ } else if (out_reg == index_reg) {
+ if (base == NULL) {
+ if (has_immediates && scale == 0) {
op1 = index;
goto make_add_immediate;
- } else if(!has_immediates && scale > 0) {
+ } else if (!has_immediates && scale > 0) {
op1 = index;
- op2 = create_immediate_from_int(cg, scale);
+ op2 = ia32_immediate_from_long(scale);
goto make_shl;
- } else if(!has_immediates) {
+ } else if (!has_immediates) {
#ifdef DEBUG_libfirm
ir_fprintf(stderr, "Optimisation warning: found lea which is "
"just a copy\n");
#endif
}
- } else if(scale == 0 && !has_immediates) {
+ } else if (scale == 0 && !has_immediates) {
op1 = index;
op2 = base;
goto make_add;
}
make_add_immediate:
- if(ia32_cg_config.use_incdec) {
- if(is_am_one(node)) {
+ if (ia32_cg_config.use_incdec) {
+ if (is_am_one(node)) {
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- res = new_rd_ia32_Inc(dbgi, irg, block, op1);
- arch_set_irn_register(arch_env, res, out_reg);
+ res = new_bd_ia32_Inc(dbgi, block, op1);
+ arch_set_irn_register(res, out_reg);
goto exchange;
}
- if(is_am_minus_one(node)) {
+ if (is_am_minus_one(node)) {
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- res = new_rd_ia32_Dec(dbgi, irg, block, op1);
- arch_set_irn_register(arch_env, res, out_reg);
+ res = new_bd_ia32_Dec(dbgi, block, op1);
+ arch_set_irn_register(res, out_reg);
goto exchange;
}
}
- op2 = create_immediate_from_am(cg, node);
+ op2 = create_immediate_from_am(node);
make_add:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
+ irg = get_irn_irg(node);
+ noreg = ia32_new_NoReg_gp(irg);
nomem = new_NoMem();
- res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
- arch_set_irn_register(arch_env, res, out_reg);
+ res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
+ arch_set_irn_register(res, out_reg);
set_ia32_commutative(res);
goto exchange;
make_shl:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
+ irg = get_irn_irg(node);
+ noreg = ia32_new_NoReg_gp(irg);
nomem = new_NoMem();
- res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
- arch_set_irn_register(arch_env, res, out_reg);
+ res = new_bd_ia32_Shl(dbgi, block, op1, op2);
+ arch_set_irn_register(res, out_reg);
goto exchange;
exchange:
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
+ SET_IA32_ORIG_NODE(res, node);
/* add new ADD/SHL to schedule */
DBG_OPT_LEA2ADD(node, res);
/* fine, we can rebuild it */
res = turn_back_am(imul);
- arch_set_irn_register(arch_env, res, reg);
+ arch_set_irn_register(res, reg);
}
/**
* Replace xorps r,r and xorpd r,r by pxor r,r
*/
-static void peephole_ia32_xZero(ir_node *xor) {
+static void peephole_ia32_xZero(ir_node *xor)
+{
set_irn_op(xor, op_ia32_xPzero);
}
+/**
+ * Replace 16bit sign extension from ax to eax by shorter cwtl
+ */
+static void peephole_ia32_Conv_I2I(ir_node *node)
+{
+ const arch_register_t *eax = &ia32_gp_regs[REG_EAX];
+ ir_mode *smaller_mode = get_ia32_ls_mode(node);
+ ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_node *cwtl;
+
+ if (get_mode_size_bits(smaller_mode) != 16 ||
+ !mode_is_signed(smaller_mode) ||
+ eax != arch_get_irn_register(val) ||
+ eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
+ return;
+
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
+ arch_set_irn_register(cwtl, eax);
+ sched_add_before(node, cwtl);
+ be_peephole_exchange(node, cwtl);
+}
+
/**
* Register a peephole optimisation function.
*/
-static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
+static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
+{
assert(op->ops.generic == NULL);
op->ops.generic = (op_func)func;
}
/* Perform peephole-optimizations. */
-void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
+void ia32_peephole_optimization(ir_graph *irg)
{
- cg = new_cg;
- arch_env = cg->arch_env;
-
/* register peephole optimisations */
clear_irp_opcodes_generic_func();
register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
if (ia32_cg_config.use_pxor)
register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
+ if (ia32_cg_config.use_short_sex_eax)
+ register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
- be_peephole_opt(cg->birg);
+ be_peephole_opt(irg);
}
/**
* all it's Projs are removed as well.
* @param irn The irn to be removed from schedule
*/
-static INLINE void try_kill(ir_node *node)
+static inline void try_kill(ir_node *node)
{
- if(get_irn_mode(node) == mode_T) {
+ if (get_irn_mode(node) == mode_T) {
const ir_edge_t *edge, *next;
foreach_out_edge_safe(node, edge, next) {
ir_node *proj = get_edge_src_irn(edge);
}
}
- if(get_irn_n_edges(node) != 0)
+ if (get_irn_n_edges(node) != 0)
return;
if (sched_is_scheduled(node)) {
ir_mode *conv_mode;
ir_mode *store_mode;
- if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
+ if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
return;
assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
pred_proj = get_irn_n(node, n_ia32_Store_val);
- if(is_Proj(pred_proj)) {
+ if (is_Proj(pred_proj)) {
pred = get_Proj_pred(pred_proj);
} else {
pred = pred_proj;
}
- if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
+ if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
return;
- if(get_ia32_op_type(pred) != ia32_Normal)
+ if (get_ia32_op_type(pred) != ia32_Normal)
return;
/* the store only stores the lower bits, so we only need the conv
* it it shrinks the mode */
conv_mode = get_ia32_ls_mode(pred);
store_mode = get_ia32_ls_mode(node);
- if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
+ if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
return;
set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
- if(get_irn_n_edges(pred_proj) == 0) {
+ if (get_irn_n_edges(pred_proj) == 0) {
kill_node(pred_proj);
- if(pred != pred_proj)
+ if (pred != pred_proj)
kill_node(pred);
}
}
assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
pred = get_irn_n(node, n_ia32_Conv_I2I_val);
- if(!is_Proj(pred))
+ if (!is_Proj(pred))
return;
predpred = get_Proj_pred(pred);
- if(!is_ia32_Load(predpred))
+ if (!is_ia32_Load(predpred))
return;
/* the load is sign extending the upper bits, so we only need the conv
* if it shrinks the mode */
load_mode = get_ia32_ls_mode(predpred);
conv_mode = get_ia32_ls_mode(node);
- if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
+ if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
return;
- if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
+ if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
/* change the load if it has only 1 user */
- if(get_irn_n_edges(pred) == 1) {
+ if (get_irn_n_edges(pred) == 1) {
ir_mode *newmode;
- if(get_mode_sign(conv_mode)) {
+ if (get_mode_sign(conv_mode)) {
newmode = find_signed_mode(load_mode);
} else {
newmode = find_unsigned_mode(load_mode);
assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
- if(is_Proj(pred_proj))
+ if (is_Proj(pred_proj))
pred = get_Proj_pred(pred_proj);
else
pred = pred_proj;
- if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
+ if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
return;
/* we know that after a conv, the upper bits are sign extended
pred_mode = get_ia32_ls_mode(pred);
pred_mode_bits = get_mode_size_bits(pred_mode);
- if(conv_mode_bits == pred_mode_bits
+ if (conv_mode_bits == pred_mode_bits
&& get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
result_conv = pred_proj;
- } else if(conv_mode_bits <= pred_mode_bits) {
+ } else if (conv_mode_bits <= pred_mode_bits) {
/* if 2nd conv is smaller then first conv, then we can always take the
* 2nd conv */
- if(get_irn_n_edges(pred_proj) == 1) {
+ if (get_irn_n_edges(pred_proj) == 1) {
result_conv = pred_proj;
set_ia32_ls_mode(pred, conv_mode);
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
set_irn_op(pred, op_ia32_Conv_I2I8Bit);
- set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
+ arch_set_in_register_reqs(pred,
+ arch_get_in_register_reqs(node));
}
} else {
/* we don't want to end up with 2 loads, so we better do nothing */
- if(get_irn_mode(pred) == mode_T) {
+ if (get_irn_mode(pred) == mode_T) {
return;
}
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
- set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
+ arch_set_in_register_reqs(result_conv,
+ arch_get_in_register_reqs(node));
}
}
} else {
/* if both convs have the same sign, then we can take the smaller one */
- if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
+ if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
result_conv = pred_proj;
} else {
/* no optimisation possible if smaller conv is sign-extend */
- if(mode_is_signed(pred_mode)) {
+ if (mode_is_signed(pred_mode)) {
return;
}
/* we can take the smaller conv if it is unsigned */
}
}
+ /* Some user (like Phis) won't be happy if we change the mode. */
+ set_irn_mode(result_conv, get_irn_mode(node));
+
/* kill the conv */
exchange(node, result_conv);
- if(get_irn_n_edges(pred_proj) == 0) {
+ if (get_irn_n_edges(pred_proj) == 0) {
kill_node(pred_proj);
- if(pred != pred_proj)
+ if (pred != pred_proj)
kill_node(pred);
}
optimize_conv_conv(result_conv);
/**
* Performs conv and address mode optimization.
*/
-void ia32_optimize_graph(ia32_code_gen_t *cg)
+void ia32_optimize_graph(ir_graph *irg)
{
- irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
-
- if (cg->dump)
- be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
+ irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
}
void ia32_init_optimize(void)