fixed fxch emitter

[libfirm] / ir / be / ia32 / ia32_optimize.c

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index df7a64b..beb96c9 100644 (file)
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -217,7 +217,7 @@ void ia32_place_consts_set_modes(ir_node *irn, void *env) {
        tenv.block    = get_nodes_block(irn);
        tenv.cg       = cg;
        tenv.irg      = cg->irg;
-       tenv.mod      = cg->mod;
+       DEBUG_ONLY(tenv.mod      = cg->mod;)
 
        /* Loop over all predecessors and check for Sym/Const nodes */
        for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
@@ -407,6 +407,32 @@ void ia32_peephole_optimization(ir_node *irn, void *env) {
        else if (is_ia32_CondJmp(irn)) {
                ia32_optimize_CondJmp(irn, env);
        }
+#if 0
+       else if (be_is_IncSP(irn)) {
+               ir_node *prev = sched_prev(irn);
+
+               if (be_is_IncSP(prev)) {
+                       /* two scheduled IncSP one-after-one, kill the first one */
+                       unsigned       prev_offs = be_get_IncSP_offset(prev);
+                       be_stack_dir_t prev_dir  = be_get_IncSP_direction(prev);
+                       unsigned       curr_offs = be_get_IncSP_offset(irn);
+                       be_stack_dir_t curr_dir  = be_get_IncSP_direction(irn);
+
+                       int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
+                                     curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
+
+                       if (new_ofs < 0) {
+                               new_ofs  = -new_ofs;
+                               curr_dir = be_stack_dir_expand;
+                       }
+                       else
+                               curr_dir = be_stack_dir_shrink;
+                       be_set_IncSP_offset(prev, 0);
+                       be_set_IncSP_offset(irn, (unsigned)new_ofs);
+                       be_set_IncSP_direction(irn, curr_dir);
+               }
+       }
+#endif
 }
 
 
@@ -596,7 +622,7 @@ static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
 /**
  * Folds Add or Sub to LEA if possible
  */
-static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
+static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
        ir_graph   *irg        = get_irn_irg(irn);
        dbg_info   *dbg        = get_irn_dbg_info(irn);
        ir_node    *block      = get_nodes_block(irn);
@@ -613,6 +639,7 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, firm_dbg_module_t *
        ir_node    *left, *right, *temp;
        ir_node    *base, *index;
        ia32_am_flavour_t am_flav;
+       DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
 
        if (is_ia32_Add(irn))
                isadd = 1;
@@ -849,7 +876,6 @@ static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, firm_dbg_module_t *
  */
 void ia32_optimize_am(ir_node *irn, void *env) {
        ia32_code_gen_t   *cg   = env;
-       firm_dbg_module_t *mod  = cg->mod;
        ir_node           *res  = irn;
        dbg_info          *dbg;
        ir_mode           *mode;
@@ -858,6 +884,7 @@ void ia32_optimize_am(ir_node *irn, void *env) {
        ir_node           *store, *load, *mem_proj;
        ir_node           *succ, *addr_b, *addr_i;
        int                check_am_src = 0;
+       DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
 
        if (! is_ia32_irn(irn))
                return;
@@ -889,7 +916,7 @@ void ia32_optimize_am(ir_node *irn, void *env) {
                /* check is irn is a candidate for address calculation */
                if (is_candidate(block, irn, 1)) {
                        DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
-                       res = fold_addr(cg, irn, mod, noreg_gp);
+                       res = fold_addr(cg, irn, noreg_gp);
 
                        if (res == irn)
                                DB((mod, LEVEL_1, "transformed into %+F\n", res));