+/**
+ * Project: libFIRM
+ * File name: ir/be/ia32/ia32_optimize.c
+ * Purpose: Implements several optimizations for IA32
+ * Author: Christian Wuerdig
+ * CVS-ID: $Id$
+ * Copyright: (c) 2006 Universität Karlsruhe
+ * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
+ */
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "iredges.h"
#include "tv.h"
#include "irgmod.h"
+#include "irgwalk.h"
+#include "height.h"
#include "../be_t.h"
#include "../beabi.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
+typedef enum {
+ IA32_AM_CAND_NONE = 0,
+ IA32_AM_CAND_LEFT = 1,
+ IA32_AM_CAND_RIGHT = 2,
+ IA32_AM_CAND_BOTH = 3
+} ia32_am_cand_t;
+
#undef is_NoMem
#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
ir_node *block = env->block;
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
- cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
+ cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
else
- cnst = new_rd_ia32_vfConst(dbg, irg, block, mode);
- }
- else {
- cnst = new_rd_ia32_Const(dbg, irg, block, mode);
+ cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
}
+ else
+ cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
+
set_ia32_Const_attr(cnst, env->irn);
+
return cnst;
}
if (tp == firm_unknown_type)
tp = get_prim_type(cg->isa->types, mode);
- res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
+ res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
set_entity_ld_ident(res, get_entity_ident(res));
set_entity_visibility(res, visibility_local);
cnst = gen_SymConst(env);
}
else {
- cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
+ cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
set_ia32_Const_attr(cnst, node);
}
return cnst;
}
/* put the const into the block where the original const was */
- if (! cg->opt.placecnst) {
+ if (! (cg->opt & IA32_OPT_PLACECNST)) {
tenv.block = get_nodes_block(pred);
}
int same_args = 1;
for (i = 0; i < n; i++) {
- if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
+ if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
same_args = 0;
break;
}
DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
DBG_OPT_CJMP(irn);
- set_irn_op(irn, op_ia32_CJmp);
+ set_irn_op(irn, op_ia32_CJmpAM);
DB((cg->mod, LEVEL_1, "%+F\n", irn));
}
bl = get_nodes_block(irn);
push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
- be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp), mode_T);
- proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), 0);
- proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, 1);
+ be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
+ proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
+ proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
+
+ /* copy a possible constant from the store */
+ set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
+ set_ia32_immop_type(push, get_ia32_immop_type(irn));
/* the push must have SP out register */
arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
&ia32_gp_regs[REG_GP_NOREG])
return;
- if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->sp)
+ if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
return;
/* ok, translate into pop */
reg = arch_get_irn_register(cg->arch_env, load);
sp = arch_get_irn_register(cg->arch_env, irn);
- pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2), mode_T);
- proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), 0);
- proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), 1);
- proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, 2);
+ pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
+ proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
+ proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
+ proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
exchange(old_proj_M, proj_M);
exchange(old_proj_res, proj_res);
sched_add_before(proj_res,pop);
}
-/**
-
/**
* Tries to optimize two following IncSP.
*/
be_set_IncSP_offset(prev, 0);
be_set_IncSP_offset(irn, (unsigned)new_ofs);
be_set_IncSP_direction(irn, curr_dir);
+
+ /* Omit the optimized IncSP */
+ be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
}
}
ia32_optimize_TestJmp(irn, cg);
else if (is_ia32_CondJmp(irn))
ia32_optimize_CondJmp(irn, cg);
- else if (be_is_IncSP(irn))
- ia32_optimize_IncSP(irn, cg);
+ /* seems to be buggy when using Pushes */
+// else if (be_is_IncSP(irn))
+// ia32_optimize_IncSP(irn, cg);
+ else if (is_ia32_Store(irn))
+ ia32_create_Push(irn, cg);
}
*
******************************************************************/
+typedef struct {
+ ia32_code_gen_t *cg;
+ heights_t *h;
+} ia32_am_opt_env_t;
+
static int node_is_ia32_comm(const ir_node *irn) {
return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
}
return 0;
}
-
-
/**
- * Checks if irn is a candidate for address calculation or address mode.
+ * Checks if irn is a candidate for address calculation.
*
- * address calculation (AC):
* - none of the operand must be a Load within the same block OR
* - all Loads must have more than one user OR
* - the irn has a frame entity (it's a former FrameAddr)
*
+ * @param block The block the Loads must/mustnot be in
+ * @param irn The irn to check
+ * return 1 if irn is a candidate, 0 otherwise
+ */
+static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
+ ir_node *in, *left, *right;
+ int n, is_cand = 1;
+
+ left = get_irn_n(irn, 2);
+ right = get_irn_n(irn, 3);
+
+ in = left;
+
+ if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
+ n = ia32_get_irn_n_edges(in);
+ is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
+ }
+
+ in = right;
+
+ if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
+ n = ia32_get_irn_n_edges(in);
+ is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
+ }
+
+ is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
+
+ return is_cand;
+}
+
+/**
+ * Checks if irn is a candidate for address mode.
+ *
* address mode (AM):
* - at least one operand has to be a Load within the same block AND
* - the load must not have other users than the irn AND
* - the irn must not have a frame entity set
*
- * @param block The block the Loads must/not be in
+ * @param h The height information of the irg
+ * @param block The block the Loads must/mustnot be in
* @param irn The irn to check
- * @param check_addr 1 if to check for address calculation, 0 otherwise
- * return 1 if irn is a candidate for AC or AM, 0 otherwise
+ * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
*/
-static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
- ir_node *in;
- int n, is_cand = check_addr;
+static ia32_am_cand_t is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
+ ir_node *in, *load, *other, *left, *right;
+ int n, is_cand = 0, cand;
- in = get_irn_n(irn, 2);
+ if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+ return 0;
+
+ left = get_irn_n(irn, 2);
+ right = get_irn_n(irn, 3);
+
+ in = left;
if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
n = ia32_get_irn_n_edges(in);
- is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
+ is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
+
+ load = get_Proj_pred(in);
+ other = right;
+
+ /* If there is a data dependency of other irn from load: cannot use AM */
+ if (get_nodes_block(other) == block) {
+ other = skip_Proj(other);
+ is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
+ }
}
- in = get_irn_n(irn, 3);
+ cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
+ in = right;
+ is_cand = 0;
if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
n = ia32_get_irn_n_edges(in);
- is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
+ is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
+
+ load = get_Proj_pred(in);
+ other = left;
+
+ /* If there is a data dependency of other irn from load: cannot use load */
+ if (get_nodes_block(other) == block) {
+ other = skip_Proj(other);
+ is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
+ }
}
- is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
+ cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
- return is_cand;
+ /* if the irn has a frame entity: we do not use address mode */
+ return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
}
/**
}
/**
- * Optimizes a pattern around irn to address mode if possible.
+ * Sets new_right index of irn to right and new_left index to left.
+ * Also exchange left and right
*/
-void ia32_optimize_am(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
- ir_node *res = irn;
- dbg_info *dbg;
- ir_mode *mode;
- ir_node *block, *noreg_gp, *noreg_fp;
- ir_node *left, *right, *temp;
- ir_node *store, *load, *mem_proj;
- ir_node *succ, *addr_b, *addr_i;
- int check_am_src = 0;
- DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
+static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
+ ir_node *temp;
- if (! is_ia32_irn(irn))
- return;
+ set_irn_n(irn, new_right, *right);
+ set_irn_n(irn, new_left, *left);
- dbg = get_irn_dbg_info(irn);
- mode = get_irn_mode(irn);
- block = get_nodes_block(irn);
- noreg_gp = ia32_new_NoReg_gp(cg);
- noreg_fp = ia32_new_NoReg_fp(cg);
+ temp = *left;
+ *left = *right;
+ *right = temp;
- DBG((mod, LEVEL_1, "checking for AM\n"));
+ /* this is only needed for Compares, but currently ALL nodes
+ * have this attribute :-) */
+ set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
+}
- /* 1st part: check for address calculations and transform the into Lea */
+/**
+ * Performs address calculation optimization (create LEAs if possible)
+ */
+static void optimize_lea(ir_node *irn, void *env) {
+ ia32_code_gen_t *cg = env;
+ ir_node *block, *noreg_gp, *left, *right;
+
+ if (! is_ia32_irn(irn))
+ return;
/* Following cases can occur: */
/* - Sub (l, imm) -> LEA [base - offset] */
/* with scale > 1 iff l/r == shl (1,2,3) */
if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
- left = get_irn_n(irn, 2);
- right = get_irn_n(irn, 3);
+ left = get_irn_n(irn, 2);
+ right = get_irn_n(irn, 3);
+ block = get_nodes_block(irn);
+ noreg_gp = ia32_new_NoReg_gp(cg);
/* Do not try to create a LEA if one of the operands is a Load. */
/* check is irn is a candidate for address calculation */
- if (is_candidate(block, irn, 1)) {
- DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
+ if (is_addr_candidate(block, irn)) {
+ ir_node *res;
+
+ DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
res = fold_addr(cg, irn, noreg_gp);
- if (res == irn)
- DB((mod, LEVEL_1, "transformed into %+F\n", res));
+ if (res != irn)
+ DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
else
- DB((mod, LEVEL_1, "not transformed\n"));
+ DB((cg->mod, LEVEL_1, "not transformed\n"));
}
}
+ else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
+ /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
+ /* - Store -> LEA into Store } it might be better to keep the LEA */
+ left = get_irn_n(irn, 0);
+
+ if (is_ia32_Lea(left)) {
+ const ir_edge_t *edge, *ne;
+ ir_node *src;
+
+ /* merge all Loads/Stores connected to this LEA with the LEA */
+ foreach_out_edge_safe(left, edge, ne) {
+ src = get_edge_src_irn(edge);
- /* 2nd part: fold following patterns: */
- /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
- /* - Store -> LEA into Store } it might be better to keep the LEA */
+ if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
+ DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
+ if (! is_ia32_got_lea(src))
+ merge_loadstore_lea(src, left);
+ set_ia32_got_lea(src);
+ }
+ }
+ }
+ }
+}
+
+
+/**
+ * Checks for address mode patterns and performs the
+ * necessary transformations.
+ * This function is called by a walker.
+ */
+static void optimize_am(ir_node *irn, void *env) {
+ ia32_am_opt_env_t *am_opt_env = env;
+ ia32_code_gen_t *cg = am_opt_env->cg;
+ heights_t *h = am_opt_env->h;
+ ir_node *block, *noreg_gp, *noreg_fp;
+ ir_node *left, *right;
+ ir_node *store, *load, *mem_proj;
+ ir_node *succ, *addr_b, *addr_i;
+ int check_am_src = 0;
+ int need_exchange_on_fail = 0;
+ DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
+
+ if (! is_ia32_irn(irn))
+ return;
+
+ block = get_nodes_block(irn);
+ noreg_gp = ia32_new_NoReg_gp(cg);
+ noreg_fp = ia32_new_NoReg_fp(cg);
+
+ DBG((mod, LEVEL_1, "checking for AM\n"));
+
+ /* fold following patterns: */
/* - op -> Load into AMop with am_Source */
/* conditions: */
/* - op is am_Source capable AND */
/* - the Load and Store are in the same block AND */
/* - nobody else uses the result of the op */
- if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
- /* 1st: check for Load/Store -> LEA */
- if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
- left = get_irn_n(irn, 0);
-
- if (is_ia32_Lea(left)) {
- const ir_edge_t *edge, *ne;
- ir_node *src;
+ if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn)) {
+ ia32_am_cand_t cand = is_am_candidate(h, block, irn);
+ ia32_am_cand_t orig_cand = cand;
- /* merge all Loads/Stores connected to this LEA with the LEA */
- foreach_out_edge_safe(left, edge, ne) {
- src = get_edge_src_irn(edge);
+ /* cand == 1: load is left; cand == 2: load is right; */
- if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
- DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
- merge_loadstore_lea(src, left);
- }
- }
- }
- }
- /* check if the node is an address mode candidate */
- else if (is_candidate(block, irn, 0)) {
- DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
-
- left = get_irn_n(irn, 2);
- if (get_irn_arity(irn) == 4) {
- /* it's an "unary" operation */
- right = left;
- }
- else {
- right = get_irn_n(irn, 3);
- }
+ if (cand == IA32_AM_CAND_NONE)
+ return;
- /* normalize commutative ops */
- if (node_is_ia32_comm(irn)) {
- /* Assure that right operand is always a Load if there is one */
- /* because non-commutative ops can only use Dest AM if the right */
- /* operand is a load, so we only need to check right operand. */
- if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
- {
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
-
- temp = left;
- left = right;
- right = temp;
- }
- }
+ DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
- /* check for Store -> op -> Load */
+ left = get_irn_n(irn, 2);
+ if (get_irn_arity(irn) == 4) {
+ /* it's an "unary" operation */
+ right = left;
+ }
+ else {
+ right = get_irn_n(irn, 3);
+ }
- /* Store -> op -> Load optimization is only possible if supported by op */
- /* and if right operand is a Load */
- if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
- pred_is_specific_nodeblock(block, right, is_ia32_Ld))
- {
+ /* normalize commutative ops */
+ if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_LEFT)) {
- /* An address mode capable op always has a result Proj. */
- /* If this Proj is used by more than one other node, we don't need to */
- /* check further, otherwise we check for Store and remember the address, */
- /* the Store points to. */
+ /* Assure that right operand is always a Load if there is one */
+ /* because non-commutative ops can only use Dest AM if the right */
+ /* operand is a load, so we only need to check right operand. */
- succ = get_res_proj(irn);
- assert(succ && "Couldn't find result proj");
+ exchange_left_right(irn, &left, &right, 3, 2);
+ need_exchange_on_fail = 1;
- addr_b = NULL;
- addr_i = NULL;
- store = NULL;
+ /* now: load is right */
+ cand = IA32_AM_CAND_RIGHT;
+ }
- /* now check for users and Store */
- if (ia32_get_irn_n_edges(succ) == 1) {
- succ = get_edge_src_irn(get_irn_out_edge_first(succ));
+ /* check for Store -> op -> Load */
- if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
- store = succ;
- addr_b = get_irn_n(store, 0);
- addr_i = get_irn_n(store, 1);
- }
+ /* Store -> op -> Load optimization is only possible if supported by op */
+ /* and if right operand is a Load */
+ if ((get_ia32_am_support(irn) & ia32_am_Dest) && (cand & IA32_AM_CAND_RIGHT))
+ {
+ /* An address mode capable op always has a result Proj. */
+ /* If this Proj is used by more than one other node, we don't need to */
+ /* check further, otherwise we check for Store and remember the address, */
+ /* the Store points to. */
+
+ succ = get_res_proj(irn);
+ assert(succ && "Couldn't find result proj");
+
+ addr_b = NULL;
+ addr_i = NULL;
+ store = NULL;
+
+ /* now check for users and Store */
+ if (ia32_get_irn_n_edges(succ) == 1) {
+ succ = get_edge_src_irn(get_irn_out_edge_first(succ));
+
+ if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
+ store = succ;
+ addr_b = get_irn_n(store, 0);
+ addr_i = get_irn_n(store, 1);
}
+ }
- if (store) {
- /* we found a Store as single user: Now check for Load */
+ if (store) {
+ /* we found a Store as single user: Now check for Load */
- /* Extra check for commutative ops with two Loads */
- /* -> put the interesting Load right */
- if (node_is_ia32_comm(irn) &&
- pred_is_specific_nodeblock(block, left, is_ia32_Ld))
+ /* Extra check for commutative ops with two Loads */
+ /* -> put the interesting Load right */
+ if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_BOTH)) {
+ if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
+ (addr_i == get_irn_n(get_Proj_pred(left), 1)))
{
- if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
- (addr_i == get_irn_n(get_Proj_pred(left), 1)))
- {
- /* We exchange left and right, so it's easier to kill */
- /* the correct Load later and to handle unary operations. */
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
-
- temp = left;
- left = right;
- right = temp;
- }
+ /* We exchange left and right, so it's easier to kill */
+ /* the correct Load later and to handle unary operations. */
+ exchange_left_right(irn, &left, &right, 3, 2);
+ need_exchange_on_fail ^= 1;
}
+ }
- /* skip the Proj for easier access */
- load = get_Proj_pred(right);
-
- /* Compare Load and Store address */
- if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
- /* Right Load is from same address, so we can */
- /* disconnect the Load and Store here */
-
- /* set new base, index and attributes */
- set_irn_n(irn, 0, addr_b);
- set_irn_n(irn, 1, addr_i);
- add_ia32_am_offs(irn, get_ia32_am_offs(load));
- set_ia32_am_scale(irn, get_ia32_am_scale(load));
- set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
- set_ia32_op_type(irn, ia32_AddrModeD);
- set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
- set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
-
- set_ia32_am_sc(irn, get_ia32_am_sc(load));
- if (is_ia32_am_sc_sign(load))
- set_ia32_am_sc_sign(irn);
-
- if (is_ia32_use_frame(load))
- set_ia32_use_frame(irn);
-
- /* connect to Load memory and disconnect Load */
- if (get_irn_arity(irn) == 5) {
- /* binary AMop */
- set_irn_n(irn, 4, get_irn_n(load, 2));
- set_irn_n(irn, 3, noreg_gp);
- }
- else {
- /* unary AMop */
- set_irn_n(irn, 3, get_irn_n(load, 2));
- set_irn_n(irn, 2, noreg_gp);
- }
-
- /* connect the memory Proj of the Store to the op */
- mem_proj = get_mem_proj(store);
- set_Proj_pred(mem_proj, irn);
- set_Proj_proj(mem_proj, 1);
-
- /* clear remat flag */
- set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
-
- DBG_OPT_AM_D(load, store, irn);
-
- DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
+ /* skip the Proj for easier access */
+ load = get_Proj_pred(right);
+
+ /* Compare Load and Store address */
+ if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
+ /* Right Load is from same address, so we can */
+ /* disconnect the Load and Store here */
+
+ /* set new base, index and attributes */
+ set_irn_n(irn, 0, addr_b);
+ set_irn_n(irn, 1, addr_i);
+ add_ia32_am_offs(irn, get_ia32_am_offs(load));
+ set_ia32_am_scale(irn, get_ia32_am_scale(load));
+ set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
+ set_ia32_op_type(irn, ia32_AddrModeD);
+ set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
+ set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
+
+ set_ia32_am_sc(irn, get_ia32_am_sc(load));
+ if (is_ia32_am_sc_sign(load))
+ set_ia32_am_sc_sign(irn);
+
+ if (is_ia32_use_frame(load))
+ set_ia32_use_frame(irn);
+
+ /* connect to Load memory and disconnect Load */
+ if (get_irn_arity(irn) == 5) {
+ /* binary AMop */
+ set_irn_n(irn, 4, get_irn_n(load, 2));
+ set_irn_n(irn, 3, noreg_gp);
}
- } /* if (store) */
- else if (get_ia32_am_support(irn) & ia32_am_Source) {
- /* There was no store, check if we still can optimize for source address mode */
- check_am_src = 1;
+ else {
+ /* unary AMop */
+ set_irn_n(irn, 3, get_irn_n(load, 2));
+ set_irn_n(irn, 2, noreg_gp);
+ }
+
+ /* connect the memory Proj of the Store to the op */
+ mem_proj = get_mem_proj(store);
+ set_Proj_pred(mem_proj, irn);
+ set_Proj_proj(mem_proj, 1);
+
+ /* clear remat flag */
+ set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+
+ DBG_OPT_AM_D(load, store, irn);
+
+ DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
+
+ need_exchange_on_fail = 0;
}
- } /* if (support AM Dest) */
+ } /* if (store) */
else if (get_ia32_am_support(irn) & ia32_am_Source) {
- /* op doesn't support am AM Dest -> check for AM Source */
+ /* There was no store, check if we still can optimize for source address mode */
check_am_src = 1;
}
+ } /* if (support AM Dest) */
+ else if (get_ia32_am_support(irn) & ia32_am_Source) {
+ /* op doesn't support am AM Dest -> check for AM Source */
+ check_am_src = 1;
+ }
- /* normalize commutative ops */
- if (node_is_ia32_comm(irn)) {
- /* Assure that left operand is always a Load if there is one */
- /* because non-commutative ops can only use Source AM if the */
- /* left operand is a Load, so we only need to check the left */
- /* operand afterwards. */
- if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
-
- temp = left;
- left = right;
- right = temp;
- }
- }
+ /* was exchanged but optimize failed: exchange back */
+ if (need_exchange_on_fail) {
+ exchange_left_right(irn, &left, &right, 3, 2);
+ cand = orig_cand;
+ }
- /* optimize op -> Load iff Load is only used by this op */
- /* and left operand is a Load which only used by this irn */
- if (check_am_src &&
- pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
- (ia32_get_irn_n_edges(left) == 1))
- {
- left = get_Proj_pred(left);
-
- addr_b = get_irn_n(left, 0);
- addr_i = get_irn_n(left, 1);
-
- /* set new base, index and attributes */
- set_irn_n(irn, 0, addr_b);
- set_irn_n(irn, 1, addr_i);
- add_ia32_am_offs(irn, get_ia32_am_offs(left));
- set_ia32_am_scale(irn, get_ia32_am_scale(left));
- set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
- set_ia32_op_type(irn, ia32_AddrModeS);
- set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
- set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
-
- set_ia32_am_sc(irn, get_ia32_am_sc(left));
- if (is_ia32_am_sc_sign(left))
- set_ia32_am_sc_sign(irn);
-
- /* clear remat flag */
- set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
-
- if (is_ia32_use_frame(left))
- set_ia32_use_frame(irn);
-
- /* connect to Load memory */
- if (get_irn_arity(irn) == 5) {
- /* binary AMop */
- set_irn_n(irn, 4, get_irn_n(left, 2));
- }
- else {
- /* unary AMop */
- set_irn_n(irn, 3, get_irn_n(left, 2));
- }
+ need_exchange_on_fail = 0;
+
+ /* normalize commutative ops */
+ if (check_am_src && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_RIGHT)) {
+
+ /* Assure that left operand is always a Load if there is one */
+ /* because non-commutative ops can only use Source AM if the */
+ /* left operand is a Load, so we only need to check the left */
+ /* operand afterwards. */
+
+ exchange_left_right(irn, &left, &right, 3, 2);
+ need_exchange_on_fail = 1;
+
+ /* now: load is left */
+ cand = IA32_AM_CAND_LEFT;
+ }
+
+ /* optimize op -> Load iff Load is only used by this op */
+ /* and left operand is a Load which only used by this irn */
+ if (check_am_src &&
+ (cand & IA32_AM_CAND_LEFT) &&
+ (ia32_get_irn_n_edges(left) == 1))
+ {
+ left = get_Proj_pred(left);
+
+ addr_b = get_irn_n(left, 0);
+ addr_i = get_irn_n(left, 1);
+
+ /* set new base, index and attributes */
+ set_irn_n(irn, 0, addr_b);
+ set_irn_n(irn, 1, addr_i);
+ add_ia32_am_offs(irn, get_ia32_am_offs(left));
+ set_ia32_am_scale(irn, get_ia32_am_scale(left));
+ set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
+ set_ia32_op_type(irn, ia32_AddrModeS);
+ set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
+ set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
+
+ set_ia32_am_sc(irn, get_ia32_am_sc(left));
+ if (is_ia32_am_sc_sign(left))
+ set_ia32_am_sc_sign(irn);
+
+ /* clear remat flag */
+ set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+
+ if (is_ia32_use_frame(left))
+ set_ia32_use_frame(irn);
+
+ /* connect to Load memory */
+ if (get_irn_arity(irn) == 5) {
+ /* binary AMop */
+ set_irn_n(irn, 4, get_irn_n(left, 2));
+
+ /* this is only needed for Compares, but currently ALL nodes
+ * have this attribute :-) */
+ set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
/* disconnect from Load */
- set_irn_n(irn, 2, noreg_gp);
+ /* (make second op -> first, set second in to noreg) */
+ set_irn_n(irn, 2, get_irn_n(irn, 3));
+ set_irn_n(irn, 3, noreg_gp);
+ }
+ else {
+ /* unary AMop */
+ set_irn_n(irn, 3, get_irn_n(left, 2));
- DBG_OPT_AM_S(left, irn);
+ /* disconnect from Load */
+ set_irn_n(irn, 2, noreg_gp);
+ }
- /* If Load has a memory Proj, connect it to the op */
- mem_proj = get_mem_proj(left);
- if (mem_proj) {
- set_Proj_pred(mem_proj, irn);
- set_Proj_proj(mem_proj, 1);
- }
+ DBG_OPT_AM_S(left, irn);
- DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
+ /* If Load has a memory Proj, connect it to the op */
+ mem_proj = get_mem_proj(left);
+ if (mem_proj) {
+ set_Proj_pred(mem_proj, irn);
+ set_Proj_proj(mem_proj, 1);
}
+
+ DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
}
+ else {
+ /* was exchanged but optimize failed: exchange back */
+ if (need_exchange_on_fail)
+ exchange_left_right(irn, &left, &right, 3, 2);
+ }
+ }
+}
+
+/**
+ * Performs address mode optimization.
+ */
+void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
+ /* if we are supposed to do AM or LEA optimization: recalculate edges */
+ if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+ }
+ else {
+ /* no optimizations at all */
+ return;
+ }
+
+ /* beware: we cannot optimize LEA and AM in one run because */
+ /* LEA optimization adds new nodes to the irg which */
+ /* invalidates the phase data */
+
+ if (cg->opt & IA32_OPT_LEA) {
+ irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
+ }
+
+ if (cg->opt & IA32_OPT_DOAM) {
+ /* we need height information for am optimization */
+ heights_t *h = heights_new(cg->irg);
+ ia32_am_opt_env_t env;
+
+ env.cg = cg;
+ env.h = h;
+
+ irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);
+
+ heights_free(h);
}
}
projects / libfirm / blobdiff