*/
static void peephole_ia32_Return(ir_node *node)
{
- ir_node *block, *irn;
+ ir_node *irn;
if (!ia32_cg_config.use_pad_return)
return;
- block = get_nodes_block(node);
-
/* check if this return is the first on the block */
sched_foreach_reverse_from(node, irn) {
switch (get_irn_opcode(irn)) {
ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i];
ir_node *noreg = ia32_new_NoReg_gp(irg);
+ const ir_edge_t *edge;
+ const ir_edge_t *next;
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
spreg = arch_get_irn_register(curr_sp);
- push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
+ push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
+ mem, val, curr_sp);
copy_mark(store, push);
if (first_push == NULL)
/* create memory Proj */
mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
+ /* rewire Store Projs */
+ foreach_out_edge_safe(store, edge, next) {
+ ir_node *proj = get_edge_src_irn(edge);
+ if (!is_Proj(proj))
+ continue;
+ switch (get_Proj_proj(proj)) {
+ case pn_ia32_Store_M:
+ exchange(proj, mem_proj);
+ break;
+ default:
+ panic("unexpected Proj on Store->IncSp");
+ }
+ }
+
/* use the memproj now */
- be_peephole_exchange(store, mem_proj);
+ be_peephole_exchange(store, push);
inc_ofs -= 4;
}
int i, maxslot, inc_ofs, ofs;
ir_node *node, *pred_sp, *block;
ir_node *loads[MAXPUSH_OPTIMIZE];
- ir_graph *irg;
unsigned regmask = 0;
unsigned copymask = ~0;
/* create a new IncSP if needed */
block = get_nodes_block(irn);
- irg = get_irn_irg(irn);
if (inc_ofs > 0) {
pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
sched_add_before(irn, pred_sp);