static const arch_env_t *arch_env;
static ia32_code_gen_t *cg;
+static void copy_mark(const ir_node *old, ir_node *new)
+{
+ if (is_ia32_is_reload(old))
+ set_ia32_is_reload(new);
+ if (is_ia32_is_spill(old))
+ set_ia32_is_spill(new);
+ if (is_ia32_is_remat(old))
+ set_ia32_is_remat(new);
+}
+
+typedef enum produces_flag_t {
+ produces_no_flag,
+ produces_flag_zero,
+ produces_flag_carry
+} produces_flag_t;
+
/**
- * Returns non-zero if the given node produces
- * a zero flag.
+ * Return which usable flag the given node produces
*
* @param node the node to check
- * @param pn if >= 0, the projection number of the used result
+ * @param pn the projection number of the used result
*/
-static int produces_zero_flag(ir_node *node, int pn)
+static produces_flag_t produces_test_flag(ir_node *node, int pn)
{
ir_node *count;
const ia32_immediate_attr_t *imm_attr;
if (!is_ia32_irn(node))
- return 0;
-
- if (pn >= 0) {
- if (pn != pn_ia32_res)
- return 0;
- }
+ return produces_no_flag;
switch (get_ia32_irn_opcode(node)) {
- case iro_ia32_Add:
- case iro_ia32_Adc:
- case iro_ia32_And:
- case iro_ia32_Or:
- case iro_ia32_Xor:
- case iro_ia32_Sub:
- case iro_ia32_Sbb:
- case iro_ia32_Neg:
- case iro_ia32_Inc:
- case iro_ia32_Dec:
- return 1;
-
- case iro_ia32_ShlD:
- case iro_ia32_ShrD:
- case iro_ia32_Shl:
- case iro_ia32_Shr:
- case iro_ia32_Sar:
- assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
- assert(n_ia32_Shl_count == n_ia32_Shr_count
- && n_ia32_Shl_count == n_ia32_Sar_count);
- if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
+ case iro_ia32_Add:
+ case iro_ia32_Adc:
+ case iro_ia32_And:
+ case iro_ia32_Or:
+ case iro_ia32_Xor:
+ case iro_ia32_Sub:
+ case iro_ia32_Sbb:
+ case iro_ia32_Neg:
+ case iro_ia32_Inc:
+ case iro_ia32_Dec:
+ break;
+
+ case iro_ia32_ShlD:
+ case iro_ia32_ShrD:
+ assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
count = get_irn_n(node, n_ia32_ShlD_count);
- } else {
+ goto check_shift_amount;
+
+ case iro_ia32_Shl:
+ case iro_ia32_Shr:
+ case iro_ia32_Sar:
+ assert(n_ia32_Shl_count == n_ia32_Shr_count
+ && n_ia32_Shl_count == n_ia32_Sar_count);
count = get_irn_n(node, n_ia32_Shl_count);
- }
- /* when shift count is zero the flags are not affected, so we can only
- * do this for constants != 0 */
- if (!is_ia32_Immediate(count))
- return 0;
-
- imm_attr = get_ia32_immediate_attr_const(count);
- if (imm_attr->symconst != NULL)
- return 0;
- if ((imm_attr->offset & 0x1f) == 0)
- return 0;
- return 1;
-
- default:
- break;
+check_shift_amount:
+ /* when shift count is zero the flags are not affected, so we can only
+ * do this for constants != 0 */
+ if (!is_ia32_Immediate(count))
+ return produces_no_flag;
+
+ imm_attr = get_ia32_immediate_attr_const(count);
+ if (imm_attr->symconst != NULL)
+ return produces_no_flag;
+ if ((imm_attr->offset & 0x1f) == 0)
+ return produces_no_flag;
+ break;
+
+ case iro_ia32_Mul:
+ return pn == pn_ia32_Mul_res_high ?
+ produces_flag_carry : produces_no_flag;
+
+ default:
+ return produces_no_flag;
}
- return 0;
+
+ return pn == pn_ia32_res ?
+ produces_flag_zero : produces_no_flag;
}
/**
res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
pn_ia32_res);
- reg = arch_get_irn_register(arch_env, node);
+ reg = arch_get_irn_register(node);
arch_set_irn_register(arch_env, res_proj, reg);
sched_add_before(node, new_node);
}
set_ia32_ls_mode(test, get_ia32_ls_mode(node));
- reg = arch_get_irn_register(arch_env, node);
+ reg = arch_get_irn_register(node);
arch_set_irn_register(arch_env, test, reg);
foreach_out_edge_safe(node, edge, tmp) {
}
sched_add_before(node, test);
+ copy_mark(node, test);
be_peephole_exchange(node, test);
}
ir_node *flags_proj;
ir_node *block;
ir_mode *flags_mode;
- int pn = -1;
+ int pn = pn_ia32_res;
ir_node *schedpoint;
const ir_edge_t *edge;
/* walk schedule up and abort when we find left or some other node destroys
the flags */
- schedpoint = sched_prev(node);
- while(schedpoint != left) {
+ schedpoint = node;
+ for (;;) {
schedpoint = sched_prev(schedpoint);
- if(arch_irn_is(arch_env, schedpoint, modify_flags))
+ if (schedpoint == left)
+ break;
+ if (arch_irn_is(arch_env, schedpoint, modify_flags))
return;
- if(schedpoint == block)
+ if (schedpoint == block)
panic("couldn't find left");
}
}
}
- if(!produces_zero_flag(left, pn))
- return;
+ switch (produces_test_flag(left, pn)) {
+ case produces_flag_zero:
+ break;
+
+ case produces_flag_carry:
+ foreach_out_edge(node, edge) {
+ ir_node *user = get_edge_src_irn(edge);
+ int pnc = get_ia32_condcode(user);
+
+ switch (pnc) {
+ case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
+ case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
+ default: panic("unexpected pn");
+ }
+ set_ia32_condcode(user, pnc);
+ }
+ break;
+
+ default:
+ return;
+ }
left = turn_into_mode_t(left);
case beo_Return:
/* the return node itself, ignore */
continue;
+ case iro_Start:
+ case beo_RegParams:
case beo_Barrier:
- /* ignore the barrier, no code generated */
+ /* ignore no code generated */
continue;
case beo_IncSP:
/* arg, IncSP 0 nodes might occur, ignore these */
}
}
- /* ensure, that the 3 byte return is generated
- * actually the emitter tests again if the block beginning has a label and
- * isn't just a fallthrough */
+ /* ensure, that the 3 byte return is generated */
be_Return_set_emit_pop(node, 1);
}
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
- spreg = arch_get_irn_register(cg->arch_env, curr_sp);
+ spreg = arch_get_irn_register(curr_sp);
push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
+ copy_mark(store, push);
if (first_push == NULL)
first_push = push;
be_set_IncSP_offset(irn, inc_ofs);
}
+#if 0
+static void peephole_store_incsp(ir_node *store)
+{
+ dbg_info *dbgi;
+ ir_node *node;
+ ir_node *block;
+ ir_node *noref;
+ ir_node *mem;
+ ir_node *push;
+ ir_node *val;
+ ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
+ if (!be_is_IncSP(am_base)
+ || get_nodes_block(am_base) != get_nodes_block(store))
+ return;
+ mem = get_irn_n(store, n_ia32_Store_mem);
+ if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
+ || !is_NoMem(mem))
+ return;
+
+ int incsp_offset = be_get_IncSP_offset(am_base);
+ if (incsp_offset <= 0)
+ return;
+
+ /* we have to be at offset 0 */
+ int my_offset = get_ia32_am_offs_int(store);
+ if (my_offset != 0) {
+ /* TODO here: find out wether there is a store with offset 0 before
+ * us and wether we can move it down to our place */
+ return;
+ }
+ ir_mode *ls_mode = get_ia32_ls_mode(store);
+ int my_store_size = get_mode_size_bytes(ls_mode);
+
+ if (my_offset + my_store_size > incsp_offset)
+ return;
+
+ /* correctness checking:
+ - noone else must write to that stackslot
+ (because after translation incsp won't allocate it anymore)
+ */
+ sched_foreach_reverse_from(store, node) {
+ int i, arity;
+
+ if (node == am_base)
+ break;
+
+ /* make sure noone else can use the space on the stack */
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *pred = get_irn_n(node, i);
+ if (pred != am_base)
+ continue;
+
+ if (i == n_ia32_base &&
+ (get_ia32_op_type(node) == ia32_AddrModeS
+ || get_ia32_op_type(node) == ia32_AddrModeD)) {
+ int node_offset = get_ia32_am_offs_int(node);
+ ir_mode *node_ls_mode = get_ia32_ls_mode(node);
+ int node_size = get_mode_size_bytes(node);
+ /* overlapping with our position? abort */
+ if (node_offset < my_offset + my_store_size
+ && node_offset + node_size >= my_offset)
+ return;
+ /* otherwise it's fine */
+ continue;
+ }
+
+ /* strange use of esp: abort */
+ return;
+ }
+ }
+
+ /* all ok, change to push */
+ dbgi = get_irn_dbg_info(store);
+ block = get_nodes_block(store);
+ noreg = ia32_new_NoReg_gp(cg);
+ val = get_ia32_
+
+ push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem,
+
+ create_push(dbgi, current_ir_graph, block, am_base, store);
+}
+#endif
+
/**
* Return true if a mode can be stored in the GP register set
*/
maxslot = -1;
pred_sp = be_get_IncSP_pred(irn);
for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
- ir_node *mem;
int offset;
int loadslot;
const arch_register_t *sreg, *dreg;
/* not a GP copy, ignore */
continue;
}
- dreg = arch_get_irn_register(arch_env, node);
- sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
+ dreg = arch_get_irn_register(node);
+ sreg = arch_get_irn_register(be_get_Copy_op(node));
if (regmask & copymask & (1 << sreg->index)) {
break;
}
* but we do not check this */
break;
}
- /* Load has to be attached to Spill-Mem */
- mem = skip_Proj(get_irn_n(node, n_ia32_mem));
- if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
- break;
/* should have NO index */
if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
if (loads[loadslot] != NULL)
break;
- dreg = arch_get_irn_register(arch_env, node);
+ dreg = arch_get_irn_register(node);
if (regmask & (1 << dreg->index)) {
/* this register is already used */
break;
const arch_register_t *reg;
mem = get_irn_n(load, n_ia32_mem);
- reg = arch_get_irn_register(arch_env, load);
+ reg = arch_get_irn_register(load);
pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
arch_set_irn_register(arch_env, pop, reg);
+ copy_mark(load, pop);
+
/* create stackpointer Proj */
pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
arch_set_irn_register(arch_env, pred_sp, esp);
/* transform Load->IncSP combinations to Pop where possible */
peephole_Load_IncSP_to_pop(node);
- if (arch_get_irn_register(arch_env, node) != esp)
+ if (arch_get_irn_register(node) != esp)
return;
/* replace IncSP -4 by Pop freereg when possible */
if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
return;
- reg = arch_get_irn_register(arch_env, node);
+ reg = arch_get_irn_register(node);
assert(be_peephole_get_reg_value(reg) == NULL);
/* create xor(produceval, produceval) */
sched_add_before(node, produceval);
sched_add_before(node, xor);
+ copy_mark(node, xor);
be_peephole_exchange(node, xor);
}
base = NULL;
base_reg = NULL;
} else {
- base_reg = arch_get_irn_register(arch_env, base);
+ base_reg = arch_get_irn_register(base);
}
if(is_noreg(cg, index)) {
index = NULL;
index_reg = NULL;
} else {
- index_reg = arch_get_irn_register(arch_env, index);
+ index_reg = arch_get_irn_register(index);
}
if(base == NULL && index == NULL) {
return;
}
- out_reg = arch_get_irn_register(arch_env, node);
+ out_reg = arch_get_irn_register(node);
scale = get_ia32_am_scale(node);
assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
/* check if we have immediates values (frame entities should already be
/* exchange the Add and the LEA */
sched_add_before(node, res);
+ copy_mark(node, res);
be_peephole_exchange(node, res);
}
/**
* Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
*/
-static void peephole_ia32_Imul_split(ir_node *imul) {
+static void peephole_ia32_Imul_split(ir_node *imul)
+{
const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
const arch_register_t *reg;
- ir_node *load, *block, *base, *index, *mem, *res, *noreg;
- dbg_info *dbgi;
- ir_graph *irg;
+ ir_node *res;
- if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
+ if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
/* no memory, imm form ignore */
return;
}
return;
/* fine, we can rebuild it */
- dbgi = get_irn_dbg_info(imul);
- block = get_nodes_block(imul);
- irg = current_ir_graph;
- base = get_irn_n(imul, n_ia32_IMul_base);
- index = get_irn_n(imul, n_ia32_IMul_index);
- mem = get_irn_n(imul, n_ia32_IMul_mem);
- load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
-
- /* copy all attributes */
- set_irn_pinned(load, get_irn_pinned(imul));
- set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
-
- set_ia32_am_scale(load, get_ia32_am_scale(imul));
- set_ia32_am_sc(load, get_ia32_am_sc(imul));
- set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
- if (is_ia32_am_sc_sign(imul))
- set_ia32_am_sc_sign(load);
- if (is_ia32_use_frame(imul))
- set_ia32_use_frame(load);
- set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
-
- sched_add_before(imul, load);
-
- mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
- res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
-
+ res = turn_back_am(imul);
arch_set_irn_register(arch_env, res, reg);
- be_peephole_new_node(res);
-
- set_irn_n(imul, n_ia32_IMul_mem, mem);
- noreg = get_irn_n(imul, n_ia32_IMul_left);
- set_irn_n(imul, n_ia32_IMul_left, res);
- set_ia32_op_type(imul, ia32_Normal);
}
/**
projects / libfirm / blobdiff