*/
/**
- * Project: libFIRM
- * File name: ir/be/ia32/ia32_optimize.c
- * Purpose: Implements several optimizations for IA32
- * Author: Christian Wuerdig
- * CVS-ID: $Id$
- * Copyright: (c) 2006 Universitaet Karlsruhe
- * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
+ * @file
+ * @brief Implements several optimizations for IA32.
+ * @author Christian Wuerdig
+ * @version $Id$
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#include "ia32_new_nodes.h"
#include "bearch_ia32_t.h"
-#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
+#include "gen_ia32_regalloc_if_t.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
#include "ia32_util.h"
is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
return 0;
+ if(get_ia32_frame_ent(irn) != NULL)
+ return IA32_AM_CAND_NONE;
+
left = get_irn_n(irn, 2);
arity = get_irn_arity(irn);
assert(arity == 5 || arity == 4);
cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
/* if the irn has a frame entity: we do not use address mode */
- return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
+ return cand;
}
/**
int i, arity;
if(get_irn_mode(node) == mode_T) {
- const ir_edge_t *edge;
- foreach_out_edge(node, edge) {
+ const ir_edge_t *edge, *next;
+ foreach_out_edge_safe(node, edge, next) {
ir_node *proj = get_edge_src_irn(edge);
try_remove_from_sched(proj);
}
/**
* Performs address calculation optimization (create LEAs if possible)
*/
-static void optimize_lea(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
-
+static void optimize_lea(ia32_code_gen_t *cg, ir_node *irn) {
if (! is_ia32_irn(irn))
return;
}
}
+static void optimize_conv_store(ia32_code_gen_t *cg, ir_node *node)
+{
+ ir_node *pred;
+
+ if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
+ return;
+
+ pred = get_irn_n(node, 2);
+ if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
+ return;
+
+ if(get_ia32_ls_mode(pred) != get_ia32_ls_mode(node))
+ return;
+
+ /* unnecessary conv, the store already does the conversion */
+ set_irn_n(node, 2, get_irn_n(pred, 2));
+ if(get_irn_n_edges(pred) == 0) {
+ be_kill_node(pred);
+ }
+}
+
+static void optimize_load_conv(ia32_code_gen_t *cg, ir_node *node)
+{
+ ir_node *pred, *predpred;
+
+ if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
+ return;
+
+ pred = get_irn_n(node, 2);
+ if(!is_Proj(pred))
+ return;
+
+ predpred = get_Proj_pred(pred);
+ if(!is_ia32_Load(predpred))
+ return;
+
+ /* unnecessary conv, the load already did the conversion */
+ exchange(node, pred);
+}
+
+static void optimize_node(ir_node *node, void *env)
+{
+ ia32_code_gen_t *cg = env;
+
+ optimize_load_conv(cg, node);
+ optimize_conv_store(cg, node);
+ optimize_lea(cg, node);
+}
+
/**
* Checks for address mode patterns and performs the
* necessary transformations.
int dest_possible;
int source_possible;
+ static const arch_register_req_t dest_out_reg_req_0 = {
+ arch_register_req_type_none,
+ NULL, /* regclass */
+ NULL, /* limit bitset */
+ -1, /* same pos */
+ -1 /* different pos */
+ };
+ static const arch_register_req_t *dest_am_out_reqs[] = {
+ &dest_out_reg_req_0
+ };
+
if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
return;
if (is_ia32_Lea(irn))
am_support = get_ia32_am_support(irn);
block = get_nodes_block(irn);
- DBG((dbg, LEVEL_1, "checking for AM\n"));
-
/* fold following patterns: */
/* - op -> Load into AMop with am_Source */
/* conditions: */
return;
orig_cand = cand;
- DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
+ DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F (candleft %d candright %d)... \n", irn,
+ cand & IA32_AM_CAND_LEFT, cand & IA32_AM_CAND_RIGHT));
left = get_irn_n(irn, 2);
if (get_irn_arity(irn) == 4) {
dest_possible = am_support & ia32_am_Dest ? 1 : 0;
source_possible = am_support & ia32_am_Source ? 1 : 0;
+ DBG((dbg, LEVEL_2, "\tdest_possible %d source_possible %d ... \n", dest_possible, source_possible));
+
if (dest_possible) {
addr_b = NULL;
addr_i = NULL;
}
if (store == NULL) {
+ DBG((dbg, LEVEL_2, "\tno store found, not using dest_mode\n"));
dest_possible = 0;
}
}
/* normalize nodes, we need the interesting load on the left side */
if (cand & IA32_AM_CAND_RIGHT) {
load = get_Proj_pred(right);
- if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
+ if (load_store_addr_is_equal(load, store, addr_b, addr_i)
+ && node_is_ia32_comm(irn)) {
+ DBG((dbg, LEVEL_2, "\texchanging left/right\n"));
exchange_left_right(irn, &left, &right, 3, 2);
need_exchange_on_fail ^= 1;
if (cand == IA32_AM_CAND_RIGHT)
#ifndef AGGRESSIVE_AM
/* we have to be the only user of the load */
if (get_irn_n_edges(left) > 1) {
+ DBG((dbg, LEVEL_2, "\tmatching load has too may users, not using dest_mode\n"));
dest_possible = 0;
}
#endif
} else {
+ DBG((dbg, LEVEL_2, "\tno matching load found, not using dest_mode"));
dest_possible = 0;
}
}
ir_node *storemem = get_irn_n(store, 3);
assert(get_irn_mode(loadmem) == mode_M);
assert(get_irn_mode(storemem) == mode_M);
- if(storemem != loadmem || !is_Proj(storemem)
- || get_Proj_pred(storemem) != load) {
+ /* TODO there could be a sync between store and load... */
+ if(storemem != loadmem && (!is_Proj(storemem) || get_Proj_pred(storemem) != load)) {
+ DBG((dbg, LEVEL_2, "\tload/store using different memories, not using dest_mode"));
dest_possible = 0;
}
}
if (dest_possible) {
/* Compare Load and Store address */
- if (!load_store_addr_is_equal(load, store, addr_b, addr_i))
+ if (!load_store_addr_is_equal(load, store, addr_b, addr_i)) {
+ DBG((dbg, LEVEL_2, "\taddresses not equal, not using dest_mode"));
dest_possible = 0;
+ }
}
if (dest_possible) {
set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
}
+ /* change node mode and out register requirements */
set_irn_mode(irn, mode_M);
+ set_ia32_out_req_all(irn, dest_am_out_reqs);
/* connect the memory Proj of the Store to the op */
- mem_proj = ia32_get_proj_for_mode(store, mode_M);
- edges_reroute(mem_proj, irn, irg);
+ edges_reroute(store, irn, irg);
/* clear remat flag */
set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
- try_remove_from_sched(load);
try_remove_from_sched(store);
+ try_remove_from_sched(load);
DBG_OPT_AM_D(load, store, irn);
DB((dbg, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
}
/**
- * Performs address mode optimization.
+ * Performs conv and address mode optimization.
*/
-void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
+void ia32_optimize_graph(ia32_code_gen_t *cg) {
/* if we are supposed to do AM or LEA optimization: recalculate edges */
- if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
-#if 0
- edges_deactivate(cg->irg);
- edges_activate(cg->irg);
-#endif
- }
- else {
+ if (! (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA))) {
/* no optimizations at all */
return;
}
/* invalidates the phase data */
if (cg->opt & IA32_OPT_LEA) {
- irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
+ irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
}
if (cg->dump)
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