if(get_irn_n_edges(pred_proj) == 1) {
result_conv = pred_proj;
set_ia32_ls_mode(pred, conv_mode);
+
+ /* Argh:We must change the opcode to 8bit AND copy the register constraints */
+ if (get_mode_size_bits(conv_mode) == 8) {
+ set_irn_op(pred, op_ia32_Conv_I2I8Bit);
+ set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
+ }
} else {
/* TODO: construct syncs/stuff here but we'll probably end up with
* 2 statements anyway */
result_conv = exact_copy(pred);
set_ia32_ls_mode(result_conv, conv_mode);
+
+ /* Argh:We must change the opcode to 8bit AND copy the register constraints */
+ if (get_mode_size_bits(conv_mode) == 8) {
+ set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
+ set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
+ }
}
} else {
/* if both convs have the same sign, then we can take the smaller one */
}
if (source_possible) {
+ const ia32_attr_t *attr_load = get_ia32_attr_const(load);
+ ia32_attr_t *attr_irn = get_ia32_attr(irn);
addr_b = get_irn_n(load, 0);
addr_i = get_irn_n(load, 1);
set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
set_ia32_op_type(irn, ia32_AddrModeS);
set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
+ attr_irn->data.need_64bit_stackent
+ = attr_load->data.need_64bit_stackent;
+ attr_irn->data.need_32bit_stackent
+ = attr_load->data.need_32bit_stackent;
/* set ls_mode if not already present (conv nodes already have ls_mode
set) */