if (mode_is_reference(get_irn_mode(irn))) {
set_irn_mode(irn, mode_Iu);
}
-
- /*
- Annotate mode of stored value to link field of the Store
- as floating point converts might be optimized and we would
- loose the mode.
- */
- if (get_irn_opcode(irn) == iro_Store) {
- set_irn_link(irn, get_irn_mode(get_Store_value(irn)));
- }
}
/**
/* do not create push if IncSp doesn't expand stack or expand size is different from register size */
if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
- be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
+ be_get_IncSP_offset(sp) != (unsigned) get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
return;
/* do not create push, if there is a path (inside the block) from the push value to IncSP */
ia32_optimize_CondJmp(irn, cg);
}
/* seems to be buggy when using Pushes */
-// else if (be_is_IncSP(irn))
-// ia32_optimize_IncSP(irn, cg);
+ else if (be_is_IncSP(irn))
+ ia32_optimize_IncSP(irn, cg);
else if (is_ia32_Store(irn))
ia32_create_Push(irn, cg);
}
ir_node *in, *load, *other, *left, *right;
int n, is_cand = 0, cand;
- if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn))
+ if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
+ is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
return 0;
left = get_irn_n(irn, 2);
return ret_val;
}
+/**
+ * Adds res before irn into schedule if irn was scheduled.
+ * @param irn The schedule point
+ * @param res The node to be scheduled
+ */
+static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
+ if (sched_is_scheduled(irn))
+ sched_add_before(irn, res);
+}
+
+/**
+ * Removes irn from schedule if it was scheduled. If irn is a mode_T node
+ * all it's Projs are removed as well.
+ * @param irn The irn to be removed from schedule
+ */
+static INLINE void try_remove_from_sched(ir_node *irn) {
+ if (sched_is_scheduled(irn)) {
+ if (get_irn_mode(irn) == mode_T) {
+ const ir_edge_t *edge;
+ foreach_out_edge(irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ if (sched_is_scheduled(proj))
+ sched_remove(proj);
+ }
+ }
+ sched_remove(irn);
+ }
+}
/**
* Folds Add or Sub to LEA if possible
entity *lea_ent = NULL;
ir_node *left, *right, *temp;
ir_node *base, *index;
+ int consumed_left_shift;
ia32_am_flavour_t am_flav;
DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
if (isadd) {
/* default for add -> make right operand to index */
- index = right;
- dolea = 1;
+ index = right;
+ dolea = 1;
+ consumed_left_shift = -1;
DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
temp = left;
if (is_ia32_Lea(left)) {
temp = right;
+ consumed_left_shift = 0;
}
/* check for SHL 1,2,3 */
scale = get_tarval_long(get_ia32_Immop_tarval(temp));
if (scale <= 3) {
- index = get_irn_n(temp, 2);
+ index = get_irn_n(temp, 2);
+ consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
}
if (left == right) {
base = noreg;
}
- else if (! is_ia32_Lea(left) && (index != right)) {
- /* index != right -> we found a good Shl */
- /* left != LEA -> this Shl was the left operand */
- /* -> base is right operand */
+ else if (consumed_left_shift == 1) {
+ /* -> base is right operand */
base = (right == lea_o) ? noreg : right;
}
}
DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
/* we will exchange it, report here before the Proj is created */
- if (shift && lea && lea_o)
+ if (shift && lea && lea_o) {
+ try_remove_from_sched(shift);
+ try_remove_from_sched(lea);
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
- else if (shift && lea)
+ }
+ else if (shift && lea) {
+ try_remove_from_sched(shift);
+ try_remove_from_sched(lea);
DBG_OPT_LEA3(irn, lea, shift, res);
- else if (shift && lea_o)
+ }
+ else if (shift && lea_o) {
+ try_remove_from_sched(shift);
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA3(irn, lea_o, shift, res);
- else if (lea && lea_o)
+ }
+ else if (lea && lea_o) {
+ try_remove_from_sched(lea);
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA3(irn, lea_o, lea, res);
- else if (shift)
+ }
+ else if (shift) {
+ try_remove_from_sched(shift);
DBG_OPT_LEA2(irn, shift, res);
- else if (lea)
+ }
+ else if (lea) {
+ try_remove_from_sched(lea);
DBG_OPT_LEA2(irn, lea, res);
- else if (lea_o)
+ }
+ else if (lea_o) {
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA2(irn, lea_o, res);
+ }
else
DBG_OPT_LEA1(irn, res);
/* get the result Proj of the Add/Sub */
+ try_add_to_sched(irn, res);
+ try_remove_from_sched(irn);
irn = ia32_get_res_proj(irn);
assert(irn && "Couldn't find result proj");
set_irn_n(irn, 0, get_irn_n(lea, 0));
set_irn_n(irn, 1, get_irn_n(lea, 1));
+ try_remove_from_sched(lea);
+
/* clear remat flag */
set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
/* clear remat flag */
set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+ try_remove_from_sched(load);
+ try_remove_from_sched(store);
DBG_OPT_AM_D(load, store, irn);
DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
set_Proj_proj(mem_proj, 1);
}
+ try_remove_from_sched(right);
+
DB((mod, LEVEL_1, "merged with %+F into source AM\n", right));
}
else {
projects / libfirm / blobdiff