#include "irgmod.h"
#include "irgwalk.h"
#include "height.h"
+#include "irbitset.h"
#include "../be_t.h"
#include "../beabi.h"
#include "ia32_dbg_stat.h"
#include "ia32_util.h"
+typedef struct _ia32_place_env_t {
+ ia32_code_gen_t *cg;
+ bitset_t *visited;
+} ia32_place_env_t;
+
typedef enum {
IA32_AM_CAND_NONE = 0,
IA32_AM_CAND_LEFT = 1,
return cnst;
}
-
-
/**
* Transforms (all) Const's into ia32_Const and places them in the
* block where they are used (or in the cfg-pred Block in case of Phi's).
* Additionally all reference nodes are changed into mode_Is nodes.
+ * NOTE: irn must be a firm constant!
*/
-void ia32_place_consts_set_modes(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
- ia32_transform_env_t tenv;
- ir_mode *mode;
- ir_node *pred, *cnst;
- int i;
- opcode opc;
-
- if (is_Block(irn))
- return;
+static void ia32_transform_const(ir_node *irn, void *env) {
+ ia32_code_gen_t *cg = env;
+ ir_node *cnst = NULL;
+ ia32_transform_env_t tenv;
+
+ tenv.cg = cg;
+ tenv.irg = cg->irg;
+ tenv.mode = get_irn_mode(irn);
+ tenv.dbg = get_irn_dbg_info(irn);
+ tenv.irn = irn;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
- mode = get_irn_mode(irn);
+ /* place const either in the smallest dominator of all its users or the original block */
+ if (cg->opt & IA32_OPT_PLACECNST)
+ tenv.block = node_users_smallest_common_dominator(irn, 1);
+ else
+ tenv.block = get_nodes_block(irn);
- /* transform all reference nodes into mode_Is nodes */
- if (mode_is_reference(mode)) {
- mode = mode_Is;
- set_irn_mode(irn, mode);
+ switch (get_irn_opcode(irn)) {
+ case iro_Const:
+ cnst = gen_Const(&tenv);
+ break;
+ case iro_SymConst:
+ cnst = gen_SymConst(&tenv);
+ break;
+ default:
+ assert(0 && "Wrong usage of ia32_transform_const!");
}
- /*
- Annotate mode of stored value to link field of the Store
- as floating point converts might be optimized and we would
- loose the mode.
- */
- if (get_irn_opcode(irn) == iro_Store) {
- set_irn_link(irn, get_irn_mode(get_Store_value(irn)));
- }
+ assert(cnst && "Could not create ia32 Const");
- tenv.block = get_nodes_block(irn);
- tenv.cg = cg;
- tenv.irg = cg->irg;
- DEBUG_ONLY(tenv.mod = cg->mod;)
+ /* set the new ia32 const */
+ exchange(irn, cnst);
+}
- /* Loop over all predecessors and check for Sym/Const nodes */
- for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
- pred = get_irn_n(irn, i);
- cnst = NULL;
- opc = get_irn_opcode(pred);
- tenv.irn = pred;
- tenv.mode = get_irn_mode(pred);
- tenv.dbg = get_irn_dbg_info(pred);
-
- /* If it's a Phi, then we need to create the */
- /* new Const in it's predecessor block */
- if (is_Phi(irn)) {
- tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
- }
+/**
+ * Transform all firm consts and assure, we visit each const only once.
+ */
+static void ia32_place_consts_walker(ir_node *irn, void *env) {
+ ia32_place_env_t *penv = env;
+ opcode opc = get_irn_opcode(irn);
- /* put the const into the block where the original const was */
- if (! (cg->opt & IA32_OPT_PLACECNST)) {
- tenv.block = get_nodes_block(pred);
- }
+ /* transform only firm consts which are not already visited */
+ if ((opc != iro_Const && opc != iro_SymConst) || bitset_is_set(penv->visited, get_irn_idx(irn)))
+ return;
- switch (opc) {
- case iro_Const:
- cnst = gen_Const(&tenv);
- break;
- case iro_SymConst:
- cnst = gen_SymConst(&tenv);
- break;
- default:
- break;
- }
+ /* mark const visited */
+ bitset_set(penv->visited, get_irn_idx(irn));
- /* if we found a const, then set it */
- if (cnst) {
- set_irn_n(irn, i, cnst);
- }
+ ia32_transform_const(irn, penv->cg);
+}
+
+/**
+ * Replace reference modes with mode_Iu and preserve store value modes.
+ */
+static void ia32_set_modes(ir_node *irn, void *env) {
+ if (is_Block(irn))
+ return;
+
+ /* transform all reference nodes into mode_Iu nodes */
+ if (mode_is_reference(get_irn_mode(irn))) {
+ set_irn_mode(irn, mode_Iu);
}
}
+/**
+ * Walks over the graph, transforms all firm consts into ia32 consts
+ * and places them into the "best" block.
+ * @param cg The ia32 codegenerator object
+ */
+static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) {
+ ia32_place_env_t penv;
+
+ penv.cg = cg;
+ penv.visited = bitset_irg_malloc(cg->irg);
+ irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, &penv);
+ bitset_free(penv.visited);
+}
+/* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */
+void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
+ /*
+ We need to transform the consts twice:
+ - the psi condition tree transformer needs existing constants to be ia32 constants
+ - the psi condition tree transformer inserts new firm constants which need to be transformed
+ */
+ ia32_transform_all_firm_consts(cg);
+ irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg);
+ ia32_transform_all_firm_consts(cg);
+}
/********************************************************************************************************
* _____ _ _ ____ _ _ _ _ _
/* do not create push if IncSp doesn't expand stack or expand size is different from register size */
if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
- be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
+ be_get_IncSP_offset(sp) != (unsigned) get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
return;
/* do not create push, if there is a path (inside the block) from the push value to IncSP */
ia32_optimize_CondJmp(irn, cg);
}
/* seems to be buggy when using Pushes */
-// else if (be_is_IncSP(irn))
-// ia32_optimize_IncSP(irn, cg);
+ else if (be_is_IncSP(irn))
+ ia32_optimize_IncSP(irn, cg);
else if (is_ia32_Store(irn))
ia32_create_Push(irn, cg);
}
ir_node *in, *load, *other, *left, *right;
int n, is_cand = 0, cand;
- if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn))
+ if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
+ is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
return 0;
left = get_irn_n(irn, 2);
load = get_Proj_pred(in);
other = right;
+ /* 8bit Loads are not supported, they cannot be used with every register */
+ if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
+ is_cand = 0;
+
/* If there is a data dependency of other irn from load: cannot use AM */
- if (get_nodes_block(other) == block) {
+ if (is_cand && get_nodes_block(other) == block) {
other = skip_Proj(other);
is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
/* this could happen in loops */
load = get_Proj_pred(in);
other = left;
+ /* 8bit Loads are not supported, they cannot be used with every register */
+ if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
+ is_cand = 0;
+
/* If there is a data dependency of other irn from load: cannot use load */
- if (get_nodes_block(other) == block) {
+ if (is_cand && get_nodes_block(other) == block) {
other = skip_Proj(other);
is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
/* this could happen in loops */
static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
int have_am_sc, ia32_code_gen_t *cg)
{
- ir_node *lea_base = get_irn_n(lea, 0);
- ir_node *lea_idx = get_irn_n(lea, 1);
entity *irn_ent = get_ia32_frame_ent(irn);
entity *lea_ent = get_ia32_frame_ent(lea);
int ret_val = 0;
return ret_val;
}
+/**
+ * Adds res before irn into schedule if irn was scheduled.
+ * @param irn The schedule point
+ * @param res The node to be scheduled
+ */
+static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
+ if (sched_is_scheduled(irn))
+ sched_add_before(irn, res);
+}
+
+/**
+ * Removes irn from schedule if it was scheduled. If irn is a mode_T node
+ * all it's Projs are removed as well.
+ * @param irn The irn to be removed from schedule
+ */
+static INLINE void try_remove_from_sched(ir_node *irn) {
+ if (sched_is_scheduled(irn)) {
+ if (get_irn_mode(irn) == mode_T) {
+ const ir_edge_t *edge;
+ foreach_out_edge(irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ if (sched_is_scheduled(proj))
+ sched_remove(proj);
+ }
+ }
+ sched_remove(irn);
+ }
+}
/**
* Folds Add or Sub to LEA if possible
entity *lea_ent = NULL;
ir_node *left, *right, *temp;
ir_node *base, *index;
+ int consumed_left_shift;
ia32_am_flavour_t am_flav;
DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
if (isadd) {
/* default for add -> make right operand to index */
- index = right;
- dolea = 1;
+ index = right;
+ dolea = 1;
+ consumed_left_shift = -1;
DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
temp = left;
if (is_ia32_Lea(left)) {
temp = right;
+ consumed_left_shift = 0;
}
/* check for SHL 1,2,3 */
scale = get_tarval_long(get_ia32_Immop_tarval(temp));
if (scale <= 3) {
- index = get_irn_n(temp, 2);
+ index = get_irn_n(temp, 2);
+ consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
}
if (left == right) {
base = noreg;
}
- else if (! is_ia32_Lea(left) && (index != right)) {
- /* index != right -> we found a good Shl */
- /* left != LEA -> this Shl was the left operand */
- /* -> base is right operand */
+ else if (consumed_left_shift == 1) {
+ /* -> base is right operand */
base = (right == lea_o) ? noreg : right;
}
}
DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
/* we will exchange it, report here before the Proj is created */
- if (shift && lea && lea_o)
+ if (shift && lea && lea_o) {
+ try_remove_from_sched(shift);
+ try_remove_from_sched(lea);
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
- else if (shift && lea)
+ }
+ else if (shift && lea) {
+ try_remove_from_sched(shift);
+ try_remove_from_sched(lea);
DBG_OPT_LEA3(irn, lea, shift, res);
- else if (shift && lea_o)
+ }
+ else if (shift && lea_o) {
+ try_remove_from_sched(shift);
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA3(irn, lea_o, shift, res);
- else if (lea && lea_o)
+ }
+ else if (lea && lea_o) {
+ try_remove_from_sched(lea);
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA3(irn, lea_o, lea, res);
- else if (shift)
+ }
+ else if (shift) {
+ try_remove_from_sched(shift);
DBG_OPT_LEA2(irn, shift, res);
- else if (lea)
+ }
+ else if (lea) {
+ try_remove_from_sched(lea);
DBG_OPT_LEA2(irn, lea, res);
- else if (lea_o)
+ }
+ else if (lea_o) {
+ try_remove_from_sched(lea_o);
DBG_OPT_LEA2(irn, lea_o, res);
+ }
else
DBG_OPT_LEA1(irn, res);
/* get the result Proj of the Add/Sub */
+ try_add_to_sched(irn, res);
+ try_remove_from_sched(irn);
irn = ia32_get_res_proj(irn);
assert(irn && "Couldn't find result proj");
set_irn_n(irn, 0, get_irn_n(lea, 0));
set_irn_n(irn, 1, get_irn_n(lea, 1));
+ try_remove_from_sched(lea);
+
/* clear remat flag */
set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
/* clear remat flag */
set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+ try_remove_from_sched(load);
+ try_remove_from_sched(store);
DBG_OPT_AM_D(load, store, irn);
DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
set_Proj_proj(mem_proj, 1);
}
+ try_remove_from_sched(right);
+
DB((mod, LEVEL_1, "merged with %+F into source AM\n", right));
}
else {
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