+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
+/**
+ * @file
+ * @brief Implements several optimizations for IA32.
+ * @author Matthias Braun, Christian Wuerdig
+ * @version $Id$
+ */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "irnode.h"
#include "irprog_t.h"
#include "ircons.h"
+#include "irtools.h"
#include "firm_types.h"
#include "iredges.h"
#include "tv.h"
#include "irgmod.h"
+#include "irgwalk.h"
+#include "height.h"
+#include "irbitset.h"
+#include "../be_t.h"
+#include "../beabi.h"
#include "../benode_t.h"
+#include "../besched_t.h"
#include "ia32_new_nodes.h"
#include "bearch_ia32_t.h"
+#include "gen_ia32_regalloc_if.h"
+#include "ia32_transform.h"
+#include "ia32_dbg_stat.h"
+#include "ia32_util.h"
-#undef is_NoMem
-#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
+
+typedef int is_op_func_t(const ir_node *n);
+typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
/**
- * creates a unique ident by adding a number to a tag
- *
- * @param tag the tag string, must contain a %d if a number
- * should be added
+ * checks if a node represents the NOREG value
*/
-static ident *unique_id(const char *tag)
-{
- static unsigned id = 0;
- char str[256];
-
- snprintf(str, sizeof(str), tag, ++id);
- return new_id_from_str(str);
+static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
+ return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
}
-
+/********************************************************************************************************
+ * _____ _ _ ____ _ _ _ _ _
+ * | __ \ | | | | / __ \ | | (_) (_) | | (_)
+ * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
+ * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
+ * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
+ * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
+ * | | | |
+ * |_| |_|
+ ********************************************************************************************************/
/**
- * Transforms a SymConst.
- *
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir SymConst node
- * @param mode mode of the SymConst
- * @return the created ia32 Const node
+ * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
*/
-static ir_node *gen_SymConst(ia32_transform_env_t *env) {
- ir_node *cnst;
- dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
-
- cnst = new_rd_ia32_Const(dbg, irg, block, mode);
- set_ia32_Const_attr(cnst, env->irn);
- return cnst;
-}
-/**
- * Get a primitive type for a mode.
- */
-static ir_type *get_prim_type(pmap *types, ir_mode *mode)
-{
- pmap_entry *e = pmap_find(types, mode);
- ir_type *res;
-
- if (! e) {
- char buf[64];
- snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
- res = new_type_primitive(new_id_from_str(buf), mode);
- pmap_insert(types, mode, res);
- }
- else
- res = e->value;
- return res;
-}
+// only optimize up to 48 stores behind IncSPs
+#define MAXPUSH_OPTIMIZE 48
/**
- * Get an entity that is initialized with a tarval
+ * Tries to create pushs from IncSP,Store combinations
*/
-static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
-{
- tarval *tv = get_Const_tarval(cnst);
- pmap_entry *e = pmap_find(cg->tv_ent, tv);
- entity *res;
- ir_graph *rem;
-
- if (! e) {
- ir_mode *mode = get_irn_mode(cnst);
- ir_type *tp = get_Const_type(cnst);
- if (tp == firm_unknown_type)
- tp = get_prim_type(cg->types, mode);
-
- res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
-
- set_entity_ld_ident(res, get_entity_ident(res));
- set_entity_visibility(res, visibility_local);
- set_entity_variability(res, variability_constant);
- set_entity_allocation(res, allocation_static);
-
- /* we create a new entity here: It's initialization must resist on the
- const code irg */
- rem = current_ir_graph;
- current_ir_graph = get_const_code_irg();
- set_atomic_ent_value(res, new_Const_type(tv, tp));
- current_ir_graph = rem;
- }
- else
- res = e->value;
- return res;
-}
+static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
+ int i;
+ int offset;
+ ir_node *node;
+ ir_node *stores[MAXPUSH_OPTIMIZE];
+ ir_node *block = get_nodes_block(irn);
+ ir_graph *irg = cg->irg;
+ ir_node *curr_sp;
+ ir_mode *spmode = get_irn_mode(irn);
+
+ memset(stores, 0, sizeof(stores));
+
+ assert(be_is_IncSP(irn));
+
+ offset = be_get_IncSP_offset(irn);
+ if(offset < 4)
+ return;
-/**
- * Transforms a Const.
- *
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir Const node
- * @param mode mode of the Const
- * @return the created ia32 Const node
- */
-static ir_node *gen_Const(ia32_transform_env_t *env) {
- ir_node *cnst;
- symconst_symbol sym;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
- ir_node *node = env->irn;
- dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
-
- if (mode_is_float(mode)) {
- sym.entity_p = get_entity_for_tv(env->cg, node);
-
- cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
- env->irn = cnst;
- cnst = gen_SymConst(env);
- }
- else {
- cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
- set_ia32_Const_attr(cnst, node);
- }
- return cnst;
-}
+ /*
+ * We first walk the schedule after the IncSP node as long as we find
+ * suitable stores that could be transformed to a push.
+ * We save them into the stores array which is sorted by the frame offset/4
+ * attached to the node
+ */
+ for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
+ ir_node *mem;
+ int offset;
+ int storeslot;
+
+ // it has to be a store
+ if(!is_ia32_Store(node))
+ break;
+
+ // it has to use our sp value
+ if(get_irn_n(node, n_ia32_base) != irn)
+ continue;
+ // store has to be attached to NoMem
+ mem = get_irn_n(node, n_ia32_mem);
+ if(!is_NoMem(mem)) {
+ continue;
+ }
+ /* unfortunately we can't support the full AMs possible for push at the
+ * moment. TODO: fix this */
+ if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
+ break;
+ offset = get_ia32_am_offs_int(node);
-/**
- * Transforms (all) Const's into ia32_Const and places them in the
- * block where they are used (or in the cfg-pred Block in case of Phi's)
- */
-void ia32_place_consts(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
- ia32_transform_env_t tenv;
- ir_mode *mode;
- ir_node *pred, *cnst;
- int i;
- opcode opc;
-
- if (is_Block(irn))
- return;
+ storeslot = offset / 4;
+ if(storeslot >= MAXPUSH_OPTIMIZE)
+ continue;
- mode = get_irn_mode(irn);
-
- tenv.arch_env = cg->arch_env;
- tenv.block = get_nodes_block(irn);
- tenv.cg = cg;
- tenv.irg = cg->irg;
- tenv.mod = cg->mod;
-
- /* Loop over all predecessors and check for Sym/Const nodes */
- for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
- pred = get_irn_n(irn, i);
- cnst = NULL;
- opc = get_irn_opcode(pred);
- tenv.irn = pred;
- tenv.mode = get_irn_mode(pred);
- tenv.dbg = get_irn_dbg_info(pred);
-
- /* If it's a Phi, then we need to create the */
- /* new Const in it's predecessor block */
- if (is_Phi(irn)) {
- tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
- }
+ // storing into the same slot twice is bad (and shouldn't happen...)
+ if(stores[storeslot] != NULL)
+ break;
- switch (opc) {
- case iro_Const:
- cnst = gen_Const(&tenv);
- break;
- case iro_SymConst:
- cnst = gen_SymConst(&tenv);
- break;
- default:
- break;
- }
+ // storing at half-slots is bad
+ if(offset % 4 != 0)
+ break;
- /* if we found a const, then set it */
- if (cnst) {
- set_irn_n(irn, i, cnst);
- }
+ stores[storeslot] = node;
}
-}
+ curr_sp = be_get_IncSP_pred(irn);
-/******************************************************************
- * _ _ __ __ _
- * /\ | | | | | \/ | | |
- * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
- * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
- * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
- * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
- *
- ******************************************************************/
-
-static int node_is_comm(const ir_node *irn) {
- if (is_ia32_Add(irn) ||
- is_ia32_fAdd(irn) ||
- is_ia32_Mul(irn) ||
- is_ia32_Mulh(irn) ||
- is_ia32_fMul(irn) ||
- is_ia32_And(irn) ||
- is_ia32_fAnd(irn) ||
- is_ia32_Or(irn) ||
- is_ia32_fOr(irn) ||
- is_ia32_Eor(irn) ||
- is_ia32_fEor(irn) ||
- is_ia32_Min(irn) ||
- is_ia32_fMin(irn) ||
- is_ia32_Max(irn) ||
- is_ia32_fMax(irn))
- {
- return 1;
+ // walk the stores in inverse order and create pushs for them
+ i = (offset / 4) - 1;
+ if(i >= MAXPUSH_OPTIMIZE) {
+ i = MAXPUSH_OPTIMIZE - 1;
}
- return 0;
-}
+ for( ; i >= 0; --i) {
+ const arch_register_t *spreg;
+ ir_node *push;
+ ir_node *val, *mem, *mem_proj;
+ ir_node *store = stores[i];
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
-static int ia32_get_irn_n_edges(const ir_node *irn) {
- const ir_edge_t *edge;
- int cnt = 0;
+ if(store == NULL || is_Bad(store))
+ break;
- foreach_out_edge(irn, edge) {
- cnt++;
- }
+ val = get_irn_n(store, n_ia32_unary_op);
+ mem = get_irn_n(store, n_ia32_mem);
+ spreg = arch_get_irn_register(cg->arch_env, curr_sp);
- return cnt;
-}
+ push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
-/**
- * Returns the first mode_M Proj connected to irn.
- */
-static ir_node *get_mem_proj(const ir_node *irn) {
- const ir_edge_t *edge;
- ir_node *src;
+ set_ia32_am_support(push, ia32_am_Source, ia32_am_unary);
+
+ sched_add_before(irn, push);
- assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
+ // create stackpointer proj
+ curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
+ arch_set_irn_register(cg->arch_env, curr_sp, spreg);
- foreach_out_edge(irn, edge) {
- src = get_edge_src_irn(edge);
+ // create memory proj
+ mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
- assert(is_Proj(src) && "Proj expected");
+ // use the memproj now
+ exchange(store, mem_proj);
- if (get_irn_mode(src) == mode_M)
- return src;
+ // we can remove the store now
+ sched_remove(store);
+
+ offset -= 4;
}
- return NULL;
+ be_set_IncSP_offset(irn, offset);
+
+ // can we remove the IncSP now?
+ if(offset == 0) {
+ const ir_edge_t *edge, *next;
+
+ foreach_out_edge_safe(irn, edge, next) {
+ ir_node *arg = get_edge_src_irn(edge);
+ int pos = get_edge_src_pos(edge);
+
+ set_irn_n(arg, pos, curr_sp);
+ }
+
+ set_irn_n(irn, 0, new_Bad());
+ sched_remove(irn);
+ } else {
+ set_irn_n(irn, 0, curr_sp);
+ }
}
/**
- * Returns the Proj with number 0 connected to irn.
+ * Tries to optimize two following IncSP.
*/
-static ir_node *get_res_proj(const ir_node *irn) {
- const ir_edge_t *edge;
- ir_node *src;
+static void ia32_optimize_IncSP(ir_node *node)
+{
+ int pred_offs;
+ int curr_offs;
+ int offs;
+ ir_node *pred = be_get_IncSP_pred(node);
+ ir_node *predpred;
- assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
+ if(!be_is_IncSP(pred))
+ return;
- foreach_out_edge(irn, edge) {
- src = get_edge_src_irn(edge);
+ if(get_irn_n_edges(pred) > 1)
+ return;
- assert(is_Proj(src) && "Proj expected");
+ pred_offs = be_get_IncSP_offset(pred);
+ curr_offs = be_get_IncSP_offset(node);
- if (get_Proj_proj(src) == 0)
- return src;
+ if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
+ if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
+ return;
+ }
+ offs = 0;
+ } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
+ if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
+ return;
+ }
+ offs = 0;
+ } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
+ || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
+ return;
+ } else {
+ offs = curr_offs + pred_offs;
}
- return NULL;
-}
+ be_set_IncSP_offset(node, offs);
+ /* rewire dependency edges */
+ predpred = be_get_IncSP_pred(pred);
+ edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
+
+ /* Omit the IncSP */
+ be_set_IncSP_pred(node, predpred);
+ sched_remove(pred);
+ be_kill_node(pred);
+}
/**
- * Determines if irn is a Proj and if is_op_func returns true for it's predecessor.
+ * Performs Peephole Optimizations.
*/
-static int pred_is_specific_node(const ir_node *irn, int (*is_op_func)(const ir_node *n)) {
- if (is_Proj(irn) && is_op_func(get_Proj_pred(irn))) {
- return 1;
+static void ia32_peephole_optimize_node(ir_node *node, void *env) {
+ ia32_code_gen_t *cg = env;
+
+ if (be_is_IncSP(node)) {
+ ia32_optimize_IncSP(node);
+
+ if (cg->opt & IA32_OPT_PUSHARGS)
+ ia32_create_Pushs(node, cg);
}
+}
- return 0;
+void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
+ irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
}
+/******************************************************************
+ * _ _ __ __ _
+ * /\ | | | | | \/ | | |
+ * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
+ * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
+ * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
+ * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
+ *
+ ******************************************************************/
+
/**
- * Folds Add or Sub to LEA if possible
+ * Removes node from schedule if it is not used anymore. If irn is a mode_T node
+ * all it's Projs are removed as well.
+ * @param irn The irn to be removed from schedule
*/
-static ir_node *fold_addr(ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
- ir_graph *irg = get_irn_irg(irn);
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
- ir_node *block = get_nodes_block(irn);
- ir_node *res = irn;
- char *offs = NULL;
- char *new_offs = NULL;
- int scale = 0;
- int isadd = 0;
- int dolea = 0;
- ir_node *left, *right, *temp;
- ir_node *base, *index;
- ia32_am_flavour_t am_flav;
-
- if (is_ia32_Add(irn))
- isadd = 1;
-
- left = get_irn_n(irn, 2);
- right = get_irn_n(irn, 3);
-
- /* "normalize" arguments in case of add */
- if (isadd) {
- /* put LEA == ia32_am_O as right operand */
- if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
- temp = left;
- left = right;
- right = temp;
+static INLINE void try_kill(ir_node *node)
+{
+ if(get_irn_mode(node) == mode_T) {
+ const ir_edge_t *edge, *next;
+ foreach_out_edge_safe(node, edge, next) {
+ ir_node *proj = get_edge_src_irn(edge);
+ try_kill(proj);
}
+ }
- /* put LEA != ia32_am_O as left operand */
- if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
- temp = left;
- left = right;
- right = temp;
- }
+ if(get_irn_n_edges(node) != 0)
+ return;
- /* put SHL as right operand */
- if (pred_is_specific_node(left, is_ia32_Shl)) {
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
- temp = left;
- left = right;
- right = temp;
- }
+ if (sched_is_scheduled(node)) {
+ sched_remove(node);
}
- /* Left operand could already be a LEA */
- if (is_ia32_Lea(left)) {
- DBG((mod, LEVEL_1, "\tgot LEA as left operand\n"));
+ be_kill_node(node);
+}
- base = get_irn_n(left, 0);
- index = get_irn_n(left, 1);
- offs = get_ia32_am_offs(left);
- scale = get_ia32_am_scale(left);
- }
- else {
- base = left;
- index = noreg;
- offs = NULL;
- scale = 0;
+static void optimize_conv_store(ir_node *node)
+{
+ ir_node *pred;
+ ir_mode *conv_mode;
+ ir_mode *store_mode;
- }
+ if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
+ return;
- /* check if operand is either const or right operand is AMConst (LEA with ia32_am_O) */
- if (get_ia32_cnst(irn)) {
- DBG((mod, LEVEL_1, "\tfound op with imm"));
+ pred = get_irn_n(node, 2);
+ if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
+ return;
- new_offs = get_ia32_cnst(irn);
- dolea = 1;
- }
- else if (is_ia32_Lea(right) && get_ia32_am_flavour(right) == ia32_am_O) {
- DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
+ /* the store only stores the lower bits, so we only need the conv
+ * it it shrinks the mode */
+ conv_mode = get_ia32_ls_mode(pred);
+ store_mode = get_ia32_ls_mode(node);
+ if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
+ return;
- new_offs = get_ia32_am_offs(right);
- dolea = 1;
+ set_irn_n(node, 2, get_irn_n(pred, 2));
+ if(get_irn_n_edges(pred) == 0) {
+ be_kill_node(pred);
}
- /* we can only get an additional index if there isn't already one */
- else if (isadd && be_is_NoReg(index)) {
- /* default for add -> make right operand to index */
- index = right;
- dolea = 1;
-
- DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
- /* check for SHL 1,2,3 */
- if (pred_is_specific_node(right, is_ia32_Shl)) {
- temp = get_Proj_pred(right);
-
- if (get_ia32_Immop_tarval(temp)) {
- scale = get_tarval_long(get_ia32_Immop_tarval(temp));
-
- if (scale <= 3) {
- scale = 1 << scale;
- index = get_irn_n(temp, 2);
-
- DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
- }
+}
+
+static void optimize_load_conv(ir_node *node)
+{
+ ir_node *pred, *predpred;
+ ir_mode *load_mode;
+ ir_mode *conv_mode;
+
+ if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
+ return;
+
+ pred = get_irn_n(node, 2);
+ if(!is_Proj(pred))
+ return;
+
+ predpred = get_Proj_pred(pred);
+ if(!is_ia32_Load(predpred))
+ return;
+
+ /* the load is sign extending the upper bits, so we only need the conv
+ * if it shrinks the mode */
+ load_mode = get_ia32_ls_mode(predpred);
+ conv_mode = get_ia32_ls_mode(node);
+ if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
+ return;
+
+ if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
+ /* change the load if it has only 1 user */
+ if(get_irn_n_edges(pred) == 1) {
+ ir_mode *newmode;
+ if(get_mode_sign(conv_mode)) {
+ newmode = find_signed_mode(load_mode);
+ } else {
+ newmode = find_unsigned_mode(load_mode);
}
+ assert(newmode != NULL);
+ set_ia32_ls_mode(predpred, newmode);
+ } else {
+ /* otherwise we have to keep the conv */
+ return;
}
}
- /* ok, we can create a new LEA */
- if (dolea) {
- res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
+ /* kill the conv */
+ exchange(node, pred);
+}
+
+static void optimize_conv_conv(ir_node *node)
+{
+ ir_node *pred_proj, *pred, *result_conv;
+ ir_mode *pred_mode, *conv_mode;
- /* add the old offset of a previous LEA */
- if (offs) {
- add_ia32_am_offs(res, offs);
- }
+ if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
+ return;
+
+ assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
+ pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
+ if(is_Proj(pred_proj))
+ pred = get_Proj_pred(pred_proj);
+ else
+ pred = pred_proj;
+
+ if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
+ return;
- /* add the new offset */
- if (isadd) {
- if (new_offs) {
- add_ia32_am_offs(res, new_offs);
+ /* we know that after a conv, the upper bits are sign extended
+ * so we only need the 2nd conv if it shrinks the mode */
+ conv_mode = get_ia32_ls_mode(node);
+ pred_mode = get_ia32_ls_mode(pred);
+ /* if 2nd conv is smaller then first conv, then we can always take the 2nd
+ * conv */
+ if(get_mode_size_bits(conv_mode) <= get_mode_size_bits(pred_mode)) {
+ if(get_irn_n_edges(pred_proj) == 1) {
+ result_conv = pred_proj;
+ set_ia32_ls_mode(pred, conv_mode);
+
+ /* Argh:We must change the opcode to 8bit AND copy the register constraints */
+ if (get_mode_size_bits(conv_mode) == 8) {
+ set_irn_op(pred, op_ia32_Conv_I2I8Bit);
+ set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
+ }
+ } else {
+ /* TODO: construct syncs/stuff here but we'll probably end up with
+ * 2 statements anyway */
+ if(get_irn_mode(pred) == mode_T) {
+ return;
}
- }
- else {
- sub_ia32_am_offs(res, new_offs);
- }
- /* set scale */
- set_ia32_am_scale(res, scale);
+ result_conv = exact_copy(pred);
+ set_ia32_ls_mode(result_conv, conv_mode);
- am_flav = ia32_am_N;
- /* determine new am flavour */
- if (offs || new_offs) {
- am_flav |= ia32_O;
- }
- if (! be_is_NoReg(base)) {
- am_flav |= ia32_B;
- }
- if (! be_is_NoReg(index)) {
- am_flav |= ia32_I;
+ /* Argh:We must change the opcode to 8bit AND copy the register constraints */
+ if (get_mode_size_bits(conv_mode) == 8) {
+ set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
+ set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
+ }
}
- if (scale > 0) {
- am_flav |= ia32_S;
+ } else {
+ /* if both convs have the same sign, then we can take the smaller one */
+ if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
+ result_conv = pred_proj;
+ } else {
+ /* no optimisation possible if smaller conv is sign-extend */
+ if(mode_is_signed(pred_mode)) {
+ return;
+ }
+ /* we can take the smaller conv if it is unsigned */
+ result_conv = pred_proj;
}
- set_ia32_am_flavour(res, am_flav);
-
- set_ia32_op_type(res, ia32_AddrModeS);
-
- DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
-
- /* get the result Proj of the Add/Sub */
- irn = get_res_proj(irn);
+ }
- assert(irn && "Couldn't find result proj");
+ /* kill the conv */
+ exchange(node, result_conv);
- /* exchange the old op with the new LEA */
- exchange(irn, res);
+ if(get_irn_n_edges(pred) == 0) {
+ be_kill_node(pred);
}
+ optimize_conv_conv(result_conv);
+}
+
+static void optimize_node(ir_node *node, void *env)
+{
+ (void) env;
- return res;
+ optimize_load_conv(node);
+ optimize_conv_store(node);
+ optimize_conv_conv(node);
}
/**
- * Optimizes a pattern around irn to address mode if possible.
+ * Performs conv and address mode optimization.
*/
-void ia32_optimize_am(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
- ir_graph *irg = cg->irg;
- firm_dbg_module_t *mod = cg->mod;
- ir_node *res = irn;
- dbg_info *dbg;
- ir_mode *mode;
- ir_node *block, *noreg_gp, *noreg_fp;
- ir_node *left, *right, *temp;
- ir_node *store, *mem_proj;
- ir_node *succ, *addr_b, *addr_i;
- int check_am_src = 0;
-
- if (! is_ia32_irn(irn))
- return;
-
- dbg = get_irn_dbg_info(irn);
- mode = get_irn_mode(irn);
- block = get_nodes_block(irn);
- noreg_gp = ia32_new_NoReg_gp(cg);
- noreg_fp = ia32_new_NoReg_fp(cg);
-
- DBG((mod, LEVEL_1, "checking for AM\n"));
-
- /* 1st part: check for address calculations and transform the into Lea */
-
- /* Following cases can occur: */
- /* - Sub (l, imm) -> LEA [base - offset] */
- /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
- /* - Add (l, imm) -> LEA [base + offset] */
- /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
- /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
- /* - Add (l, r) -> LEA [base + index * scale] */
- /* with scale > 1 iff l/r == shl (1,2,3) */
-
- if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
- left = get_irn_n(irn, 2);
- right = get_irn_n(irn, 3);
-
- /* Do not try to create a LEA if one of the operands is a Load. */
- if (! pred_is_specific_node(left, is_ia32_Load) &&
- ! pred_is_specific_node(right, is_ia32_Load))
- {
- res = fold_addr(irn, mod, noreg_gp);
- }
- }
-
- /* 2nd part: fold following patterns:
- /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
- /* - Store -> LEA into Store } it might be better to keep the LEA */
- /* - op -> Load into AMop with am_Source
- /* conditions: */
- /* - op is am_Source capable AND */
- /* - the Load is only used by this op AND */
- /* - the Load is in the same block */
- /* - Store -> op -> Load into AMop with am_Dest */
- /* conditions: */
- /* - op is am_Dest capable AND */
- /* - the Store uses the same address as the Load AND */
- /* - the Load is only used by this op AND */
- /* - the Load and Store are in the same block AND */
- /* - nobody else uses the result of the op */
-
- if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
- /* 1st: check for Load/Store -> LEA */
- if (is_ia32_Load(irn) || is_ia32_fLoad(irn) ||
- is_ia32_Store(irn) || is_ia32_fStore(irn))
- {
- left = get_irn_n(irn, 0);
-
- if (is_ia32_Lea(left)) {
- /* get the AM attributes from the LEA */
- add_ia32_am_offs(irn, get_ia32_am_offs(left));
- set_ia32_am_scale(irn, get_ia32_am_scale(left));
- set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
- set_ia32_op_type(irn, get_ia32_op_type(left));
-
- /* set base and index */
- set_irn_n(irn, 0, get_irn_n(left, 0));
- set_irn_n(irn, 1, get_irn_n(left, 1));
- }
- }
- /* check if at least one operand is a Load */
- else if (pred_is_specific_node(get_irn_n(irn, 2), is_ia32_Load) ||
- pred_is_specific_node(get_irn_n(irn, 2), is_ia32_fLoad) ||
- pred_is_specific_node(get_irn_n(irn, 3), is_ia32_Load) ||
- pred_is_specific_node(get_irn_n(irn, 3), is_ia32_fLoad))
- {
-
- /* normalize commutative ops */
- if (node_is_comm(irn)) {
- left = get_irn_n(irn, 2);
- right = get_irn_n(irn, 3);
-
- /* assure that Left operand is always a Load if there is one */
- if (pred_is_specific_node(right, is_ia32_Load) ||
- pred_is_specific_node(right, is_ia32_fLoad))
- {
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
-
- temp = left;
- left = right;
- right = temp;
- }
- }
+void ia32_optimize_graph(ia32_code_gen_t *cg)
+{
+ irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
- /* check for Store -> op -> Load */
-
- /* Store -> op -> Load optimization is only possible if supported by op */
- if (get_ia32_am_support(irn) & ia32_am_Dest) {
-
- /* An address mode capable op always has a result Proj. */
- /* If this Proj is used by more than one other node, we don't need to */
- /* check further, otherwise we check for Store and remember the address, */
- /* the Store points to. */
-
- succ = get_res_proj(irn);
- assert(succ && "Couldn't find result proj");
-
- addr_b = NULL;
- addr_i = NULL;
- store = NULL;
-
- /* now check for users and Store */
- if (ia32_get_irn_n_edges(succ) == 1) {
- succ = get_edge_src_irn(get_irn_out_edge_first(succ));
-
- if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
- store = succ;
- addr_b = get_irn_n(store, 0);
-
- /* Could be that the Store is connected to the address */
- /* calculating LEA while the Load is already transformed. */
- if (is_ia32_Lea(addr_b)) {
- succ = addr_b;
- addr_b = get_irn_n(succ, 0);
- addr_i = get_irn_n(succ, 1);
- }
- else {
- addr_i = noreg_gp;
- }
- }
- }
-
- if (store) {
- /* we found a Store as single user: Now check for Load */
- left = get_irn_n(irn, 2);
- right = get_irn_n(irn, 3);
-
- /* Could be that the right operand is also a Load, so we make */
- /* sure that the "interesting" Load is always the left one */
-
- /* right != NoMem means, we have a "binary" operation */
- if (! is_NoMem(right) &&
- (pred_is_specific_node(right, is_ia32_Load) ||
- pred_is_specific_node(right, is_ia32_fLoad)))
- {
- if ((addr_b == get_irn_n(get_Proj_pred(right), 0)) &&
- (addr_i == get_irn_n(get_Proj_pred(right), 1)))
- {
- /* We exchange left and right, so it's easier to kill */
- /* the correct Load later and to handle unary operations. */
- set_irn_n(irn, 2, right);
- set_irn_n(irn, 3, left);
-
- temp = left;
- left = right;
- right = temp;
- }
- }
-
- /* skip the Proj for easier access */
- left = get_Proj_pred(left);
-
- /* Compare Load and Store address */
- if ((addr_b == get_irn_n(left, 0)) && (addr_i == get_irn_n(left, 1)))
- {
- /* Left Load is from same address, so we can */
- /* disconnect the Load and Store here */
-
- /* set new base, index and attributes */
- set_irn_n(irn, 0, addr_b);
- set_irn_n(irn, 1, addr_i);
- add_ia32_am_offs(irn, get_ia32_am_offs(left));
- set_ia32_am_scale(irn, get_ia32_am_scale(left));
- set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
- set_ia32_op_type(irn, ia32_AddrModeD);
-
- /* connect to Load memory */
- if (get_irn_arity(irn) == 5) {
- /* binary AMop */
- set_irn_n(irn, 4, get_irn_n(left, 2));
- }
- else {
- /* unary AMop */
- set_irn_n(irn, 3, get_irn_n(left, 2));
- }
-
- /* disconnect from Load */
- set_irn_n(irn, 2, noreg_gp);
-
- /* connect the memory Proj of the Store to the op */
- mem_proj = get_mem_proj(store);
- set_Proj_pred(mem_proj, irn);
- set_Proj_proj(mem_proj, 1);
- }
- } /* if (store) */
- else if (get_ia32_am_support(irn) & ia32_am_Source) {
- /* There was no store, check if we still can optimize for source address mode */
- check_am_src = 1;
- }
- } /* if (support AM Dest) */
- else {
- /* op doesn't support am AM Dest -> check for AM Source */
- check_am_src = 1;
- }
+ if (cg->dump)
+ be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
+}
- /* optimize op -> Load iff Load is only used by this op */
- if (check_am_src) {
- left = get_irn_n(irn, 2);
-
- if (ia32_get_irn_n_edges(left) == 1) {
- left = get_Proj_pred(left);
-
- addr_b = get_irn_n(left, 0);
- addr_i = get_irn_n(left, 1);
-
- /* set new base, index and attributes */
- set_irn_n(irn, 0, addr_b);
- set_irn_n(irn, 1, addr_i);
- add_ia32_am_offs(irn, get_ia32_am_offs(left));
- set_ia32_am_scale(irn, get_ia32_am_scale(left));
- set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
- set_ia32_op_type(irn, ia32_AddrModeS);
-
- /* connect to Load memory */
- if (get_irn_arity(irn) == 5) {
- /* binary AMop */
- set_irn_n(irn, 4, get_irn_n(left, 2));
- }
- else {
- /* unary AMop */
- set_irn_n(irn, 3, get_irn_n(left, 2));
- }
-
- /* disconnect from Load */
- set_irn_n(irn, 2, noreg_gp);
-
- /* If Load has a memory Proj, connect it to the op */
- mem_proj = get_mem_proj(left);
- if (mem_proj) {
- set_Proj_pred(mem_proj, irn);
- set_Proj_proj(mem_proj, 1);
- }
- }
- }
- }
- }
+void ia32_init_optimize(void)
+{
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");
}
projects / libfirm / blobdiff