tenv.irn = irn;
DEBUG_ONLY(tenv.mod = cg->mod;)
-#if 1
+#if 0
/* place const either in the smallest dominator of all its users or the original block */
if (cg->opt & IA32_OPT_PLACECNST)
tenv.block = node_users_smallest_common_dominator(irn, 1);
ir_node *push;
ir_node *val, *mem;
ir_node *store = stores[i];
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
if(store == NULL || is_Bad(store))
break;
spreg = arch_get_irn_register(cg->arch_env, curr_sp);
// create a push
- push = new_rd_ia32_Push(NULL, irg, block, curr_sp, val, mem);
+ push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
if(get_ia32_immop_type(store) != ia32_ImmNone) {
copy_ia32_Immop_attr(push, store);
}
n = ia32_get_irn_n_edges(in);
is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
}
+#else
+ (void) n;
#endif
is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
*/
static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
ir_node *in, *load, *other, *left, *right;
- int n, is_cand = 0, cand;
+ int is_cand = 0, cand;
if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
#ifndef AGGRESSIVE_AM
+ int n;
n = ia32_get_irn_n_edges(in);
is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
#endif
if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
#ifndef AGGRESSIVE_AM
+ int n;
n = ia32_get_irn_n_edges(in);
is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
#endif
}
}
-
/**
* Checks for address mode patterns and performs the
* necessary transformations.
ia32_am_opt_env_t *am_opt_env = env;
ia32_code_gen_t *cg = am_opt_env->cg;
heights_t *h = am_opt_env->h;
- ir_node *block, *noreg_gp, *noreg_fp;
- ir_node *left, *right;
+ ir_node *block, *left, *right;
ir_node *store, *load, *mem_proj;
ir_node *succ, *addr_b, *addr_i;
int check_am_src = 0;
if (! is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
return;
- block = get_nodes_block(irn);
- noreg_gp = ia32_new_NoReg_gp(cg);
- noreg_fp = ia32_new_NoReg_fp(cg);
+ block = get_nodes_block(irn);
DBG((mod, LEVEL_1, "checking for AM\n"));
if (get_irn_arity(irn) == 5) {
/* binary AMop */
set_irn_n(irn, 4, get_irn_n(load, 2));
- set_irn_n(irn, 2, noreg_gp);
+ set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
}
else {
/* unary AMop */
set_irn_n(irn, 3, get_irn_n(load, 2));
- set_irn_n(irn, 2, noreg_gp);
+ set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
}
/* connect the memory Proj of the Store to the op */
set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
/* disconnect from Load */
- set_irn_n(irn, 3, noreg_gp);
+ set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
DBG_OPT_AM_S(right, irn);