removed firm proj num translation function, existing projs are renumbered instead

[libfirm] / ir / be / ia32 / ia32_optimize.c

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index 8dd663a..212676a 100644 (file)
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -35,6 +35,8 @@
 #include "ia32_dbg_stat.h"
 #include "ia32_util.h"
 
+#define AGGRESSIVE_AM
+
 typedef enum {
        IA32_AM_CAND_NONE  = 0,
        IA32_AM_CAND_LEFT  = 1,
@@ -239,11 +241,29 @@ static void ia32_transform_const(ir_node *irn, void *env) {
        tenv.irn  = irn;
        DEBUG_ONLY(tenv.mod = cg->mod;)
 
+#if 0
        /* place const either in the smallest dominator of all its users or the original block */
        if (cg->opt & IA32_OPT_PLACECNST)
                tenv.block = node_users_smallest_common_dominator(irn, 1);
        else
                tenv.block = get_nodes_block(irn);
+#else
+       {
+               ir_node *afterstart = NULL;
+               ir_node *startblock = get_irg_start_block(tenv.irg);
+               const ir_edge_t *edge;
+
+               foreach_block_succ(startblock, edge) {
+                       ir_node *block = get_edge_src_irn(edge);
+                       if (block != startblock) {
+                               afterstart = block;
+                               break;
+                       }
+               }
+               assert(afterstart != NULL);
+               tenv.block = afterstart;
+       }
+#endif
 
        switch (get_irn_opcode(irn)) {
                case iro_Const:
@@ -542,6 +562,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
                ir_node *push;
                ir_node *val, *mem;
                ir_node *store = stores[i];
+               ir_node *noreg = ia32_new_NoReg_gp(cg);
 
                if(store == NULL || is_Bad(store))
                        break;
@@ -551,7 +572,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
                spreg = arch_get_irn_register(cg->arch_env, curr_sp);
 
                // create a push
-               push = new_rd_ia32_Push(NULL, irg, block, curr_sp, val, mem);
+               push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
                if(get_ia32_immop_type(store) != ia32_ImmNone) {
                        copy_ia32_Immop_attr(push, store);
                }
@@ -735,6 +756,7 @@ static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
 
        in = left;
 
+#ifndef AGGRESSIVE_AM
        if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
                n         = ia32_get_irn_n_edges(in);
                is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
@@ -746,6 +768,9 @@ static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
                n         = ia32_get_irn_n_edges(in);
                is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
        }
+#else
+       (void) n;
+#endif
 
        is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
 
@@ -768,7 +793,7 @@ static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
  */
 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
        ir_node *in, *load, *other, *left, *right;
-       int      n, is_cand = 0, cand;
+       int      is_cand = 0, cand;
 
        if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
                is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
@@ -780,8 +805,11 @@ static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const i
        in = left;
 
        if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
+#ifndef AGGRESSIVE_AM
+               int n;
                n         = ia32_get_irn_n_edges(in);
                is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
+#endif
 
                load  = get_Proj_pred(in);
                other = right;
@@ -804,8 +832,11 @@ static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const i
        is_cand = 0;
 
        if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
+#ifndef AGGRESSIVE_AM
+               int n;
                n         = ia32_get_irn_n_edges(in);
                is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
+#endif
 
                load  = get_Proj_pred(in);
                other = left;
@@ -1460,7 +1491,6 @@ static void optimize_lea(ir_node *irn, void *env) {
        }
 }
 
-
 /**
  * Checks for address mode patterns and performs the
  * necessary transformations.
@@ -1470,8 +1500,7 @@ static void optimize_am(ir_node *irn, void *env) {
        ia32_am_opt_env_t *am_opt_env = env;
        ia32_code_gen_t   *cg         = am_opt_env->cg;
        heights_t         *h          = am_opt_env->h;
-       ir_node           *block, *noreg_gp, *noreg_fp;
-       ir_node           *left, *right;
+       ir_node           *block, *left, *right;
        ir_node           *store, *load, *mem_proj;
        ir_node           *succ, *addr_b, *addr_i;
        int               check_am_src          = 0;
@@ -1481,9 +1510,7 @@ static void optimize_am(ir_node *irn, void *env) {
        if (! is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
                return;
 
-       block    = get_nodes_block(irn);
-       noreg_gp = ia32_new_NoReg_gp(cg);
-       noreg_fp = ia32_new_NoReg_fp(cg);
+       block = get_nodes_block(irn);
 
        DBG((mod, LEVEL_1, "checking for AM\n"));
 
@@ -1610,12 +1637,12 @@ static void optimize_am(ir_node *irn, void *env) {
                                        if (get_irn_arity(irn) == 5) {
                                                /* binary AMop */
                                                set_irn_n(irn, 4, get_irn_n(load, 2));
-                                               set_irn_n(irn, 2, noreg_gp);
+                                               set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
                                        }
                                        else {
                                                /* unary AMop */
                                                set_irn_n(irn, 3, get_irn_n(load, 2));
-                                               set_irn_n(irn, 2, noreg_gp);
+                                               set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
                                        }
 
                                        /* connect the memory Proj of the Store to the op */
@@ -1708,7 +1735,7 @@ static void optimize_am(ir_node *irn, void *env) {
                        set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
 
                        /* disconnect from Load */
-                       set_irn_n(irn, 3, noreg_gp);
+                       set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
 
                        DBG_OPT_AM_S(right, irn);