block = get_nodes_block(node);
- if (get_Block_n_cfgpreds(block) == 1) {
- ir_node *pred = get_Block_cfgpred(block, 0);
-
- if (is_Jmp(pred)) {
- /* The block of the return has only one predecessor,
- which jumps directly to this block.
- This jump will be encoded as a fall through, so we
- ignore it here.
- However, the predecessor might be empty, so it must be
- ensured that empty blocks are gone away ... */
- return;
- }
- }
-
/* check if this return is the first on the block */
sched_foreach_reverse_from(node, irn) {
switch (get_irn_opcode(irn)) {
return;
}
}
- /* yep, return is the first real instruction in this block */
-#if 0
- {
- /* add an rep prefix to the return */
- ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block);
- keep_alive(rep);
- sched_add_before(node, rep);
- }
-#else
- /* ensure, that the 3 byte return is generated */
+
+ /* ensure, that the 3 byte return is generated
+ * actually the emitter tests again if the block beginning has a label and
+ * isn't just a fallthrough */
be_Return_set_emit_pop(node, 1);
-#endif
}
/* only optimize up to 48 stores behind IncSPs */
*/
static void peephole_IncSP_Store_to_push(ir_node *irn)
{
- int i, maxslot, inc_ofs;
- ir_node *node;
- ir_node *stores[MAXPUSH_OPTIMIZE];
- ir_node *block = get_nodes_block(irn);
- ir_graph *irg = cg->irg;
- ir_node *curr_sp;
- ir_mode *spmode = get_irn_mode(irn);
+ int i, maxslot, inc_ofs;
+ ir_node *node;
+ ir_node *stores[MAXPUSH_OPTIMIZE];
+ ir_node *block;
+ ir_graph *irg;
+ ir_node *curr_sp;
+ ir_mode *spmode;
memset(stores, 0, sizeof(stores));
/*
* We first walk the schedule after the IncSP node as long as we find
- * suitable stores that could be transformed to a push.
+ * suitable Stores that could be transformed to a Push.
* We save them into the stores array which is sorted by the frame offset/4
* attached to the node
*/
curr_sp = be_get_IncSP_pred(irn);
- /* walk through the stores and create Pushs for them */
+ /* walk through the Stores and create Pushs for them */
+ block = get_nodes_block(irn);
+ spmode = get_irn_mode(irn);
+ irg = cg->irg;
for (i = 0; i <= maxslot; ++i) {
const arch_register_t *spreg;
ir_node *push;
/* use the memproj now */
exchange(store, mem_proj);
- /* we can remove the store now */
+ /* we can remove the Store now */
sched_remove(store);
inc_ofs -= 4;
be_set_IncSP_pred(irn, curr_sp);
}
+/**
+ * Return true if a mode can be stored in the GP register set
+ */
+static INLINE int mode_needs_gp_reg(ir_mode *mode) {
+ if (mode == mode_fpcw)
+ return 0;
+ if (get_mode_size_bits(mode) > 32)
+ return 0;
+ return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
+}
+
+/**
+ * Tries to create Pops from Load, IncSP combinations.
+ * The Loads are replaced by Pops, the IncSP is modified
+ * (possibly into IncSP 0, but not removed).
+ */
+static void peephole_Load_IncSP_to_pop(ir_node *irn)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ int i, maxslot, inc_ofs, ofs;
+ ir_node *node, *pred_sp, *block;
+ ir_node *loads[MAXPUSH_OPTIMIZE];
+ ir_graph *irg;
+ unsigned regmask = 0;
+ unsigned copymask = ~0;
+
+ memset(loads, 0, sizeof(loads));
+ assert(be_is_IncSP(irn));
+
+ inc_ofs = -be_get_IncSP_offset(irn);
+ if (inc_ofs < 4)
+ return;
+
+ /*
+ * We first walk the schedule before the IncSP node as long as we find
+ * suitable Loads that could be transformed to a Pop.
+ * We save them into the stores array which is sorted by the frame offset/4
+ * attached to the node
+ */
+ maxslot = -1;
+ pred_sp = be_get_IncSP_pred(irn);
+ for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
+ ir_node *mem;
+ int offset;
+ int loadslot;
+ const arch_register_t *sreg, *dreg;
+
+ /* it has to be a Load */
+ if (!is_ia32_Load(node)) {
+ if (be_is_Copy(node)) {
+ if (!mode_needs_gp_reg(get_irn_mode(node))) {
+ /* not a GP copy, ignore */
+ continue;
+ }
+ dreg = arch_get_irn_register(arch_env, node);
+ sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
+ if (regmask & copymask & (1 << sreg->index)) {
+ break;
+ }
+ if (regmask & copymask & (1 << dreg->index)) {
+ break;
+ }
+ /* we CAN skip Copies if neither the destination nor the source
+ * is not in our regmask, ie none of our future Pop will overwrite it */
+ regmask |= (1 << dreg->index) | (1 << sreg->index);
+ copymask &= ~((1 << dreg->index) | (1 << sreg->index));
+ continue;
+ }
+ break;
+ }
+
+ /* we can handle only GP loads */
+ if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
+ continue;
+
+ /* it has to use our predecessor sp value */
+ if (get_irn_n(node, n_ia32_base) != pred_sp) {
+ /* it would be ok if this load does not use a Pop result,
+ * but we do not check this */
+ break;
+ }
+ /* Load has to be attached to Spill-Mem */
+ mem = skip_Proj(get_irn_n(node, n_ia32_mem));
+ if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
+ break;
+
+ /* should have NO index */
+ if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
+ break;
+
+ offset = get_ia32_am_offs_int(node);
+ /* we should NEVER access uninitialized stack BELOW the current SP */
+ assert(offset >= 0);
+
+ /* storing at half-slots is bad */
+ if ((offset & 3) != 0)
+ break;
+
+ if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
+ continue;
+ /* ignore those outside the possible windows */
+ if (offset > inc_ofs - 4)
+ continue;
+ loadslot = offset >> 2;
+
+ /* loading from the same slot twice is bad (and shouldn't happen...) */
+ if (loads[loadslot] != NULL)
+ break;
+
+ dreg = arch_get_irn_register(arch_env, node);
+ if (regmask & (1 << dreg->index)) {
+ /* this register is already used */
+ break;
+ }
+ regmask |= 1 << dreg->index;
+
+ loads[loadslot] = node;
+ if (loadslot > maxslot)
+ maxslot = loadslot;
+ }
+
+ if (maxslot < 0)
+ return;
+
+ /* find the first slot */
+ for (i = maxslot; i >= 0; --i) {
+ ir_node *load = loads[i];
+
+ if (load == NULL)
+ break;
+ }
+
+ ofs = inc_ofs - (maxslot + 1) * 4;
+ inc_ofs = (i+1) * 4;
+
+ /* create a new IncSP if needed */
+ block = get_nodes_block(irn);
+ irg = cg->irg;
+ if (inc_ofs > 0) {
+ pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
+ sched_add_before(irn, pred_sp);
+ }
+
+ /* walk through the Loads and create Pops for them */
+ for (++i; i <= maxslot; ++i) {
+ ir_node *load = loads[i];
+ ir_node *mem, *pop;
+ const ir_edge_t *edge, *tmp;
+ const arch_register_t *reg;
+
+ mem = get_irn_n(load, n_ia32_mem);
+ reg = arch_get_irn_register(arch_env, load);
+
+ pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
+ arch_set_irn_register(arch_env, pop, reg);
+
+ /* create stackpointer Proj */
+ pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
+ arch_set_irn_register(arch_env, pred_sp, esp);
+
+ sched_add_before(irn, pop);
+
+ /* rewire now */
+ foreach_out_edge_safe(load, edge, tmp) {
+ ir_node *proj = get_edge_src_irn(edge);
+
+ set_Proj_pred(proj, pop);
+ }
+
+
+ /* we can remove the Load now */
+ sched_remove(load);
+ kill_node(load);
+ }
+ be_set_IncSP_offset(irn, -ofs);
+ be_set_IncSP_pred(irn, pred_sp);
+
+}
+
+
/**
* Find a free GP register if possible, else return NULL.
*/
int offset;
/* first optimize incsp->incsp combinations */
- be_peephole_IncSP_IncSP(node);
+ node = be_peephole_IncSP_IncSP(node);
/* transform IncSP->Store combinations to Push where possible */
peephole_IncSP_Store_to_push(node);
+ /* transform Load->IncSP combinations to Pop where possible */
+ peephole_Load_IncSP_to_pop(node);
+
if (arch_get_irn_register(arch_env, node) != esp)
return;
projects / libfirm / blobdiff