* @file
* @brief Implements several optimizations for IA32.
* @author Matthias Braun, Christian Wuerdig
- * @version $Id$
*/
#include "config.h"
#include "irdump.h"
#include "error.h"
-#include "../be_t.h"
-#include "../beabi.h"
-#include "../benode.h"
-#include "../besched.h"
-#include "../bepeephole.h"
+#include "be_t.h"
+#include "beabi.h"
+#include "benode.h"
+#include "besched.h"
+#include "bepeephole.h"
#include "ia32_new_nodes.h"
#include "ia32_optimize.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
-#include "ia32_util.h"
#include "ia32_architecture.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-static void copy_mark(const ir_node *old, ir_node *new)
+static void copy_mark(const ir_node *old, ir_node *newn)
{
if (is_ia32_is_reload(old))
- set_ia32_is_reload(new);
+ set_ia32_is_reload(newn);
if (is_ia32_is_spill(old))
- set_ia32_is_spill(new);
+ set_ia32_is_spill(newn);
if (is_ia32_is_remat(old))
- set_ia32_is_remat(new);
+ set_ia32_is_remat(newn);
}
typedef enum produces_flag_t {
produces_no_flag,
- produces_flag_zero,
- produces_flag_carry
+ produces_zero_sign,
+ produces_zero_in_carry
} produces_flag_t;
/**
- * Return which usable flag the given node produces
+ * Return which usable flag the given node produces about the result.
+ * That is zero (ZF) and sign(SF).
+ * We do not check for carry (CF) or overflow (OF).
*
* @param node the node to check
* @param pn the projection number of the used result
*/
-static produces_flag_t produces_test_flag(ir_node *node, int pn)
+static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
{
ir_node *count;
const ia32_immediate_attr_t *imm_attr;
case iro_ia32_ShlD:
case iro_ia32_ShrD:
- assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
+ assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
count = get_irn_n(node, n_ia32_ShlD_count);
goto check_shift_amount;
case iro_ia32_Shl:
case iro_ia32_Shr:
case iro_ia32_Sar:
- assert(n_ia32_Shl_count == n_ia32_Shr_count
- && n_ia32_Shl_count == n_ia32_Sar_count);
+ assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
+ && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
count = get_irn_n(node, n_ia32_Shl_count);
check_shift_amount:
/* when shift count is zero the flags are not affected, so we can only
case iro_ia32_Mul:
return pn == pn_ia32_Mul_res_high ?
- produces_flag_carry : produces_no_flag;
+ produces_zero_in_carry : produces_no_flag;
default:
return produces_no_flag;
}
- return pn == pn_ia32_res ?
- produces_flag_zero : produces_no_flag;
+ return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
}
/**
ir_node *op;
ia32_attr_t const *attr;
int ins_permuted;
- int cmp_unsigned;
ir_node *test;
arch_register_t const *reg;
ir_edge_t const *edge;
noreg = ia32_new_NoReg_gp(irg);
nomem = get_irg_no_mem(current_ir_graph);
op = get_irn_n(node, n_ia32_Cmp_left);
- attr = get_irn_generic_attr(node);
+ attr = get_ia32_attr(node);
ins_permuted = attr->data.ins_permuted;
- cmp_unsigned = attr->data.cmp_unsigned;
if (is_ia32_Cmp(node)) {
test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
- op, op, ins_permuted, cmp_unsigned);
+ op, op, ins_permuted);
} else {
test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
- op, op, ins_permuted, cmp_unsigned);
+ op, op, ins_permuted);
}
set_ia32_ls_mode(test, get_ia32_ls_mode(node));
- reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
- arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
+ reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
+ arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
foreach_out_edge_safe(node, edge, tmp) {
ir_node *const user = get_edge_src_irn(edge);
ir_node *left = get_irn_n(node, n_ia32_Test_left);
ir_node *right = get_irn_n(node, n_ia32_Test_right);
- assert(n_ia32_Test_left == n_ia32_Test8Bit_left
- && n_ia32_Test_right == n_ia32_Test8Bit_right);
+ assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
+ && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
if (left == right) { /* we need a test for 0 */
ir_node *block = get_nodes_block(node);
int pn = pn_ia32_res;
+ ir_node *op = left;
ir_node *flags_proj;
ir_mode *flags_mode;
+ ir_mode *op_mode;
ir_node *schedpoint;
const ir_edge_t *edge;
+ produces_flag_t produced;
if (get_nodes_block(left) != block)
return;
- if (is_Proj(left)) {
- pn = get_Proj_proj(left);
- left = get_Proj_pred(left);
+ if (is_Proj(op)) {
+ pn = get_Proj_proj(op);
+ op = get_Proj_pred(op);
}
/* walk schedule up and abort when we find left or some other node
schedpoint = node;
for (;;) {
schedpoint = sched_prev(schedpoint);
- if (schedpoint == left)
+ if (schedpoint == op)
break;
if (arch_irn_is(schedpoint, modify_flags))
return;
panic("couldn't find left");
}
- /* make sure only Lg/Eq tests are used */
+ produced = check_produces_zero_sign(op, pn);
+ if (produced == produces_no_flag)
+ return;
+
+ /* make sure users only look at the sign/zero flag */
foreach_out_edge(node, edge) {
- ir_node *user = get_edge_src_irn(edge);
- int pnc = get_ia32_condcode(user);
+ ir_node *user = get_edge_src_irn(edge);
+ ia32_condition_code_t cc = get_ia32_condcode(user);
- if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
- return;
+ if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
+ continue;
+ if (produced == produces_zero_sign
+ && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
+ continue;
}
+ return;
}
- switch (produces_test_flag(left, pn)) {
- case produces_flag_zero:
- break;
+ op_mode = get_ia32_ls_mode(op);
+ if (op_mode == NULL)
+ op_mode = get_irn_mode(op);
- case produces_flag_carry:
- foreach_out_edge(node, edge) {
- ir_node *user = get_edge_src_irn(edge);
- int pnc = get_ia32_condcode(user);
-
- switch (pnc) {
- case pn_Cmp_Eq: pnc = ia32_pn_Cmp_not_carry; break;
- case pn_Cmp_Lg: pnc = ia32_pn_Cmp_carry; break;
- default: panic("unexpected pn");
- }
- set_ia32_condcode(user, pnc);
- }
- break;
+ /* Make sure we operate on the same bit size */
+ if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
+ return;
- default:
- return;
+ if (produced == produces_zero_in_carry) {
+ /* patch users to look at the carry instead of the zero flag */
+ foreach_out_edge(node, edge) {
+ ir_node *user = get_edge_src_irn(edge);
+ ia32_condition_code_t cc = get_ia32_condcode(user);
+
+ switch (cc) {
+ case ia32_cc_equal: cc = ia32_cc_above_equal; break;
+ case ia32_cc_not_equal: cc = ia32_cc_below; break;
+ default: panic("unexpected pn");
+ }
+ set_ia32_condcode(user, cc);
+ }
}
- if (get_irn_mode(left) != mode_T) {
- set_irn_mode(left, mode_T);
+ if (get_irn_mode(op) != mode_T) {
+ set_irn_mode(op, mode_T);
/* If there are other users, reroute them to result proj */
- if (get_irn_n_edges(left) != 2) {
- ir_node *res = new_r_Proj(left, mode_Iu, pn_ia32_res);
+ if (get_irn_n_edges(op) != 2) {
+ ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
- edges_reroute(left, res, current_ir_graph);
+ edges_reroute(op, res);
/* Reattach the result proj to left */
- set_Proj_pred(res, left);
+ set_Proj_pred(res, op);
}
+ } else {
+ if (get_irn_n_edges(left) == 2)
+ kill_node(left);
}
flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
- flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags);
+ flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
assert(get_irn_mode(node) != mode_T);
offset = imm->offset;
if (get_ia32_op_type(node) == ia32_AddrModeS) {
- ia32_attr_t *const attr = get_irn_generic_attr(node);
+ ia32_attr_t *const attr = get_ia32_attr(node);
if ((offset & 0xFFFFFF00) == 0) {
/* attr->am_offs += 0; */
} else if ((offset & 0xFFFF00FF) == 0) {
- ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
- set_irn_n(node, n_ia32_Test_right, imm);
+ ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>8);
+ set_irn_n(node, n_ia32_Test_right, imm_node);
attr->am_offs += 1;
} else if ((offset & 0xFF00FFFF) == 0) {
- ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
- set_irn_n(node, n_ia32_Test_right, imm);
+ ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>16);
+ set_irn_n(node, n_ia32_Test_right, imm_node);
attr->am_offs += 2;
} else if ((offset & 0x00FFFFFF) == 0) {
- ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
- set_irn_n(node, n_ia32_Test_right, imm);
+ ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>24);
+ set_irn_n(node, n_ia32_Test_right, imm_node);
attr->am_offs += 3;
} else {
return;
*/
static void peephole_ia32_Return(ir_node *node)
{
- ir_node *block, *irn;
+ ir_node *irn;
if (!ia32_cg_config.use_pad_return)
return;
- block = get_nodes_block(node);
-
/* check if this return is the first on the block */
sched_foreach_reverse_from(node, irn) {
switch (get_irn_opcode(irn)) {
continue;
case iro_Start:
case beo_Start:
- case beo_Barrier:
/* ignore no code generated */
continue;
case beo_IncSP:
mem = get_irn_n(store, n_ia32_mem);
spreg = arch_get_irn_register(curr_sp);
- push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
+ push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
+ mem, val, curr_sp);
copy_mark(store, push);
if (first_push == NULL)
/* create memory Proj */
mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
+ /* rewire Store Projs */
+ foreach_out_edge_safe(store, edge, next) {
+ ir_node *proj = get_edge_src_irn(edge);
+ if (!is_Proj(proj))
+ continue;
+ switch (get_Proj_proj(proj)) {
+ case pn_ia32_Store_M:
+ exchange(proj, mem_proj);
+ break;
+ default:
+ panic("unexpected Proj on Store->IncSp");
+ }
+ }
+
/* use the memproj now */
- be_peephole_exchange(store, mem_proj);
+ be_peephole_exchange(store, push);
inc_ofs -= 4;
}
ir_node *val = ia32_new_NoReg_gp(cg);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_graph *irg = get_irn_irg(block);
- ir_node *nomem = new_r_NoMem(irg);
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
sched_add_before(schedpoint, push);
/* we have to be at offset 0 */
int my_offset = get_ia32_am_offs_int(store);
if (my_offset != 0) {
- /* TODO here: find out wether there is a store with offset 0 before
- * us and wether we can move it down to our place */
+ /* TODO here: find out whether there is a store with offset 0 before
+ * us and whether we can move it down to our place */
return;
}
ir_mode *ls_mode = get_ia32_ls_mode(store);
*/
static inline int mode_needs_gp_reg(ir_mode *mode)
{
- if (mode == mode_fpcw)
+ if (mode == ia32_mode_fpcw)
return 0;
if (get_mode_size_bits(mode) > 32)
return 0;
int i, maxslot, inc_ofs, ofs;
ir_node *node, *pred_sp, *block;
ir_node *loads[MAXPUSH_OPTIMIZE];
- ir_graph *irg;
unsigned regmask = 0;
unsigned copymask = ~0;
if (loads[loadslot] != NULL)
break;
- dreg = arch_irn_get_register(node, pn_ia32_Load_res);
+ dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
if (regmask & (1 << dreg->index)) {
/* this register is already used */
break;
/* create a new IncSP if needed */
block = get_nodes_block(irn);
- irg = get_irn_irg(irn);
if (inc_ofs > 0) {
pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
sched_add_before(irn, pred_sp);
const arch_register_t *reg;
mem = get_irn_n(load, n_ia32_mem);
- reg = arch_irn_get_register(load, pn_ia32_Load_res);
+ reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
- arch_irn_set_register(pop, pn_ia32_Load_res, reg);
+ arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
copy_mark(load, pop);
if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
continue;
- if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
+ if (be_peephole_get_value(reg->global_index) == NULL)
return reg;
}
ir_node *val;
ir_node *in[1];
- pop = new_bd_ia32_Pop(dbgi, block, new_r_NoMem(irg), stack);
+ pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
arch_set_irn_register(stack, esp);
const arch_register_t *reg;
ir_node *block;
dbg_info *dbgi;
- ir_node *xor;
+ ir_node *xorn;
/* try to transform a mov 0, reg to xor reg reg */
if (attr->offset != 0 || attr->symconst != NULL)
if (ia32_cg_config.use_mov_0)
return;
/* xor destroys the flags, so no-one must be using them */
- if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
+ if (be_peephole_get_value(REG_EFLAGS) != NULL)
return;
reg = arch_get_irn_register(node);
/* create xor(produceval, produceval) */
block = get_nodes_block(node);
dbgi = get_irn_dbg_info(node);
- xor = new_bd_ia32_Xor0(dbgi, block);
- arch_set_irn_register(xor, reg);
+ xorn = new_bd_ia32_Xor0(dbgi, block);
+ arch_set_irn_register(xorn, reg);
- sched_add_before(node, xor);
+ sched_add_before(node, xorn);
- copy_mark(node, xor);
- be_peephole_exchange(node, xor);
+ copy_mark(node, xorn);
+ be_peephole_exchange(node, xorn);
}
static inline int is_noreg(const ir_node *node)
assert(is_ia32_Lea(node));
/* we can only do this if it is allowed to clobber the flags */
- if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
+ if (be_peephole_get_value(REG_EFLAGS) != NULL)
return;
base = get_irn_n(node, n_ia32_Lea_base);
block = get_nodes_block(node);
irg = get_irn_irg(node);
noreg = ia32_new_NoReg_gp(irg);
- nomem = new_r_NoMem(irg);
+ nomem = get_irg_no_mem(irg);
res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
arch_set_irn_register(res, out_reg);
set_ia32_commutative(res);
block = get_nodes_block(node);
irg = get_irn_irg(node);
noreg = ia32_new_NoReg_gp(irg);
- nomem = new_r_NoMem(irg);
+ nomem = get_irg_no_mem(irg);
res = new_bd_ia32_Shl(dbgi, block, op1, op2);
arch_set_irn_register(res, out_reg);
goto exchange;
return;
/* fine, we can rebuild it */
- res = turn_back_am(imul);
+ res = ia32_turn_back_am(imul);
arch_set_irn_register(res, reg);
}
/**
* Replace xorps r,r and xorpd r,r by pxor r,r
*/
-static void peephole_ia32_xZero(ir_node *xor)
+static void peephole_ia32_xZero(ir_node *xorn)
{
- set_irn_op(xor, op_ia32_xPzero);
+ set_irn_op(xorn, op_ia32_xPzero);
}
/**
if (get_mode_size_bits(smaller_mode) != 16 ||
!mode_is_signed(smaller_mode) ||
eax != arch_get_irn_register(val) ||
- eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
+ eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
return;
dbgi = get_irn_dbg_info(node);
/* Perform peephole-optimizations. */
void ia32_peephole_optimization(ir_graph *irg)
{
- /* register peephole optimisations */
+ /* we currently do it in 2 passes because:
+ * Lea -> Add could be usefull as flag producer for Test later
+ */
+
+ /* pass 1 */
clear_irp_opcodes_generic_func();
- register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
- register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
- register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
- register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
- register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
- register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
- if (! ia32_cg_config.use_imul_mem_imm32)
- register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
- if (ia32_cg_config.use_pxor)
- register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
+ register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
if (ia32_cg_config.use_short_sex_eax)
register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
+ if (ia32_cg_config.use_pxor)
+ register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
+ if (! ia32_cg_config.use_imul_mem_imm32)
+ register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
+ be_peephole_opt(irg);
+ /* pass 2 */
+ clear_irp_opcodes_generic_func();
+ register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
+ register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
+ register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
+ register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
+ register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
be_peephole_opt(irg);
}
/**
* Removes node from schedule if it is not used anymore. If irn is a mode_T node
- * all it's Projs are removed as well.
+ * all its Projs are removed as well.
* @param irn The irn to be removed from schedule
*/
static inline void try_kill(ir_node *node)
if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
return;
- assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
+ assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
pred_proj = get_irn_n(node, n_ia32_Store_val);
if (is_Proj(pred_proj)) {
pred = get_Proj_pred(pred_proj);
if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
return;
- assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
+ assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
pred = get_irn_n(node, n_ia32_Conv_I2I_val);
if (!is_Proj(pred))
return;
if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
return;
- assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
+ assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
if (is_Proj(pred_proj))
pred = get_Proj_pred(pred_proj);
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
+ const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
set_irn_op(pred, op_ia32_Conv_I2I8Bit);
- arch_set_in_register_reqs(pred,
- arch_get_in_register_reqs(node));
+ arch_set_irn_register_reqs_in(pred, reqs);
}
} else {
/* we don't want to end up with 2 loads, so we better do nothing */
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
+ const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
- arch_set_in_register_reqs(result_conv,
- arch_get_in_register_reqs(node));
+ arch_set_irn_register_reqs_in(result_conv, reqs);
}
}
} else {
projects / libfirm / blobdiff