DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-static ia32_code_gen_t *cg;
-
static void copy_mark(const ir_node *old, ir_node *new)
{
if (is_ia32_is_reload(old))
static void peephole_ia32_Cmp(ir_node *const node)
{
ir_node *right;
+ ir_graph *irg;
ia32_immediate_attr_t const *imm;
dbg_info *dbgi;
ir_node *block;
return;
dbgi = get_irn_dbg_info(node);
+ irg = get_irn_irg(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
+ noreg = ia32_new_NoReg_gp(irg);
nomem = get_irg_no_mem(current_ir_graph);
op = get_irn_n(node, n_ia32_Cmp_left);
attr = get_irn_generic_attr(node);
flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags);
- arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
+ arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
assert(get_irn_mode(node) != mode_T);
} else if (offset < 256) {
arch_register_t const* const reg = arch_get_irn_register(left);
- if (reg != &ia32_gp_regs[REG_EAX] &&
- reg != &ia32_gp_regs[REG_EBX] &&
- reg != &ia32_gp_regs[REG_ECX] &&
- reg != &ia32_gp_regs[REG_EDX]) {
+ if (reg != &ia32_registers[REG_EAX] &&
+ reg != &ia32_registers[REG_EBX] &&
+ reg != &ia32_registers[REG_ECX] &&
+ reg != &ia32_registers[REG_EDX]) {
return;
}
} else {
}
/* only optimize up to 48 stores behind IncSPs */
-#define MAXPUSH_OPTIMIZE 48
+#define MAXPUSH_OPTIMIZE 48
/**
* Tries to create Push's from IncSP, Store combinations.
/* walk through the Stores and create Pushs for them */
block = get_nodes_block(irn);
spmode = get_irn_mode(irn);
- irg = cg->irg;
+ irg = get_irn_irg(irn);
for (; i >= 0; --i) {
const arch_register_t *spreg;
ir_node *push;
ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i];
- ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
static ir_node *create_push(dbg_info *dbgi, ir_node *block,
ir_node *stack, ir_node *schedpoint)
{
- const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *esp = &ia32_registers[REG_ESP];
ir_node *val = ia32_new_NoReg_gp(cg);
ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *nomem = new_NoMem();
+ ir_graph *irg = get_irn_irg(block);
+ ir_node *nomem = new_r_NoMem(irg);
ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
sched_add_before(schedpoint, push);
*/
static void peephole_Load_IncSP_to_pop(ir_node *irn)
{
- const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *esp = &ia32_registers[REG_ESP];
int i, maxslot, inc_ofs, ofs;
ir_node *node, *pred_sp, *block;
ir_node *loads[MAXPUSH_OPTIMIZE];
/* create a new IncSP if needed */
block = get_nodes_block(irn);
- irg = cg->irg;
+ irg = get_irn_irg(irn);
if (inc_ofs > 0) {
pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
sched_add_before(irn, pred_sp);
int i;
for (i = 0; i < N_ia32_gp_REGS; ++i) {
- const arch_register_t *reg = &ia32_gp_regs[i];
+ const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
if (arch_register_type_is(reg, ignore))
continue;
if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
- return &ia32_gp_regs[i];
+ return reg;
}
return NULL;
ir_node *stack, ir_node *schedpoint,
const arch_register_t *reg)
{
- const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *esp = &ia32_registers[REG_ESP];
+ ir_graph *irg = get_irn_irg(block);
ir_node *pop;
ir_node *keep;
ir_node *val;
ir_node *in[1];
- pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack);
+ pop = new_bd_ia32_Pop(dbgi, block, new_r_NoMem(irg), stack);
stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
arch_set_irn_register(stack, esp);
*/
static void peephole_be_IncSP(ir_node *node)
{
- const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *esp = &ia32_registers[REG_ESP];
const arch_register_t *reg;
dbg_info *dbgi;
ir_node *block;
if (ia32_cg_config.use_mov_0)
return;
/* xor destroys the flags, so no-one must be using them */
- if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
+ if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
return;
reg = arch_get_irn_register(node);
be_peephole_exchange(node, xor);
}
-static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
+static inline int is_noreg(const ir_node *node)
{
- return node == cg->noreg_gp;
+ return is_ia32_NoReg_GP(node);
}
ir_node *ia32_immediate_from_long(long val)
ir_node *start_block = get_irg_start_block(irg);
ir_node *immediate
= new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
- arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
+ arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
return immediate;
}
res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
offset);
- arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
+ arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
return res;
}
*/
static void peephole_ia32_Lea(ir_node *node)
{
+ ir_graph *irg;
ir_node *base;
ir_node *index;
const arch_register_t *base_reg;
assert(is_ia32_Lea(node));
/* we can only do this if it is allowed to clobber the flags */
- if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
+ if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
return;
base = get_irn_n(node, n_ia32_Lea_base);
index = get_irn_n(node, n_ia32_Lea_index);
- if (is_noreg(cg, base)) {
+ if (is_noreg(base)) {
base = NULL;
base_reg = NULL;
} else {
base_reg = arch_get_irn_register(base);
}
- if (is_noreg(cg, index)) {
+ if (is_noreg(index)) {
index = NULL;
index_reg = NULL;
} else {
make_add:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
- nomem = new_NoMem();
+ irg = get_irn_irg(node);
+ noreg = ia32_new_NoReg_gp(irg);
+ nomem = new_r_NoMem(irg);
res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
arch_set_irn_register(res, out_reg);
set_ia32_commutative(res);
make_shl:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
- nomem = new_NoMem();
+ irg = get_irn_irg(node);
+ noreg = ia32_new_NoReg_gp(irg);
+ nomem = new_r_NoMem(irg);
res = new_bd_ia32_Shl(dbgi, block, op1, op2);
arch_set_irn_register(res, out_reg);
goto exchange;
*/
static void peephole_ia32_Conv_I2I(ir_node *node)
{
- const arch_register_t *eax = &ia32_gp_regs[REG_EAX];
+ const arch_register_t *eax = &ia32_registers[REG_EAX];
ir_mode *smaller_mode = get_ia32_ls_mode(node);
ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
dbg_info *dbgi;
}
/* Perform peephole-optimizations. */
-void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
+void ia32_peephole_optimization(ir_graph *irg)
{
- cg = new_cg;
-
/* register peephole optimisations */
clear_irp_opcodes_generic_func();
register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
if (ia32_cg_config.use_short_sex_eax)
register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
- be_peephole_opt(cg->irg);
+ be_peephole_opt(irg);
}
/**
/**
* Performs conv and address mode optimization.
*/
-void ia32_optimize_graph(ia32_code_gen_t *cg)
+void ia32_optimize_graph(ir_graph *irg)
{
- irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
-
- if (cg->dump)
- dump_ir_graph(cg->irg, "opt");
+ irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
}
void ia32_init_optimize(void)
projects / libfirm / blobdiff