#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
+#include "gen_ia32_machine.h"
/**
* Returns the ident of a SymConst.
return NULL;
}
-
+/**
+ * returns true if a node has x87 registers
+ */
+int ia32_has_x87_register(const ir_node *n) {
+ assert(is_ia32_irn(n) && "Need ia32 node.");
+ return is_irn_machine_user(n, 0);
+}
/***********************************************************************************
* _ _ _ __
slots = get_ia32_slots(n);
if (slots && n_res > 0) {
for (i = 0; i < n_res; i++) {
- fprintf(F, "reg #%d = %s\n", i, slots[i] ? slots[i]->name : "n/a");
+ const arch_register_t *reg;
+
+ /* retrieve "real" x87 register */
+ if (ia32_has_x87_register(n))
+ reg = get_ia32_attr(n)->x87[i + 2];
+ else
+ reg = slots[i];
+
+ fprintf(F, "reg #%d = %s\n", i, reg ? arch_register_get_name(reg) : "n/a");
}
fprintf(F, "\n");
}
ia32_attr_t *attr = get_ia32_attr(node);
static char res[64];
- snprintf(res, sizeof(res), "%+ld", attr->am_offs);
+ snprintf(res, sizeof(res), "%+d", attr->am_offs);
return res;
}
/**
* Gets the addressmode offset as long.
*/
-long get_ia32_am_offs_long(const ir_node *node) {
+int get_ia32_am_offs_int(const ir_node *node) {
ia32_attr_t *attr = get_ia32_attr(node);
return attr->am_offs;
}
ia32_attr_t *attr = get_ia32_attr(node);
int res, o;
- if (! offset || strlen(offset) < 1)
+ if (offset == NULL || offset[0] == '\0')
return;
- res = sscanf(offset, "%d", &o);
+ if (offset[0] == '-')
+ res = sscanf(offset, "%d", &o);
+ else
+ res = sscanf(offset, "%u", &o);
assert(res == 1);
if (op == '-')
extend_ia32_am_offs(node, (char *)offset, '+');
}
+void add_ia32_am_offs_int(ir_node *node, int offset) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->am_offs += offset;
+}
+
/**
* Sub an offset for addrmode.
*/
*/
const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
ia32_attr_t *attr = get_ia32_attr(node);
- return attr->in_req[pos];
+ return attr->in_req != NULL ? attr->in_req[pos] : NULL;
}
/**
*/
const ia32_register_req_t *get_ia32_out_req(const ir_node *node, int pos) {
ia32_attr_t *attr = get_ia32_attr(node);
- return attr->out_req[pos];
+ return attr->out_req != NULL ? attr->out_req[pos] : NULL;
}
/**
attr->pn_code = code;
}
+/**
+ * Sets the flags for the n'th out.
+ */
+void set_ia32_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+ attr->out_flags[pos] = flags;
+}
+
+/**
+ * Gets the flags for the n'th out.
+ */
+arch_irn_flags_t get_ia32_out_flags(const ir_node *node, int pos) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return pos < (int)attr->data.n_res ? attr->out_flags[pos] : arch_irn_flags_none;
+}
+
+/**
+ * Get the list of available execution units.
+ */
+const be_execution_unit_t ***get_ia32_exec_units(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->exec_units;
+}
+
#ifndef NDEBUG
/**
* Checks if node is a Load or xLoad/vfLoad.
*/
int is_ia32_Ld(const ir_node *node) {
- return is_ia32_Load(node) || is_ia32_xLoad(node) || is_ia32_vfld(node) || is_ia32_fld(node);
+ int op = get_ia32_irn_opcode(node);
+ return op == iro_ia32_Load || op == iro_ia32_xLoad || op == iro_ia32_vfld || op == iro_ia32_fld;
}
/**
* Checks if node is a Store or xStore/vfStore.
*/
int is_ia32_St(const ir_node *node) {
- return is_ia32_Store(node) || is_ia32_xStore(node) || is_ia32_vfst(node) || is_ia32_fst(node) || is_ia32_fstp(node);
+ int op = get_ia32_irn_opcode(node);
+ return op == iro_ia32_Store || op == iro_ia32_xStore || op == iro_ia32_vfst || op == iro_ia32_fst || op == iro_ia32_fstp;
}
/**
* Checks if node is a Const or xConst/vfConst.
*/
int is_ia32_Cnst(const ir_node *node) {
- return is_ia32_Const(node) || is_ia32_xConst(node) || is_ia32_vfConst(node);
+ int op = get_ia32_irn_opcode(node);
+ return op == iro_ia32_Const || op == iro_ia32_xConst || op == iro_ia32_vfConst;
}
/**
const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
ia32_attr_t *attr = get_ia32_attr(node);
- assert(is_ia32_irn(node) && "Not an ia32 node.");
assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
int get_ia32_out_regnr(const ir_node *node, int pos) {
ia32_attr_t *attr = get_ia32_attr(node);
- assert(is_ia32_irn(node) && "Not an ia32 node.");
assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
ia32_attr_t *attr = get_ia32_attr(node);
- assert(is_ia32_irn(node) && "Not an ia32 node.");
assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
* Initializes the nodes attributes.
*/
void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs,
- const ia32_register_req_t **out_reqs, int n_res, unsigned latency)
+ const ia32_register_req_t **out_reqs, const be_execution_unit_t ***execution_units,
+ int n_res, unsigned latency)
{
ia32_attr_t *attr = get_ia32_attr(node);
+
set_ia32_flags(node, flags);
set_ia32_in_req_all(node, in_reqs);
set_ia32_out_req_all(node, out_reqs);
set_ia32_latency(node, latency);
+ set_ia32_n_res(node, n_res);
+
+ attr->exec_units = execution_units;
+
+ attr->out_flags = NEW_ARR_D(int, get_irg_obstack(get_irn_irg(node)), n_res);
+ memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
- attr->data.n_res = n_res;
memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
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