- Improved addressmode optimisation for conv nodes

[libfirm] / ir / be / ia32 / ia32_new_nodes.c

diff --git a/ir/be/ia32/ia32_new_nodes.c b/ir/be/ia32/ia32_new_nodes.c
index b2f73f7..e509b21 100644 (file)
--- a/ir/be/ia32/ia32_new_nodes.c
+++ b/ir/be/ia32/ia32_new_nodes.c
@@ -69,7 +69,13 @@ static ident *get_sc_ident(ir_node *symc) {
        return NULL;
 }
 
-
+/**
+ * returns true if a node has x87 registers
+ */
+int ia32_has_x87_register(const ir_node *n) {
+       assert(is_ia32_irn(n) && "Need ia32 node.");
+       return is_irn_machine_user(n, 0);
+}
 
 /***********************************************************************************
  *      _                                   _       _             __
@@ -225,7 +231,15 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
                        slots = get_ia32_slots(n);
                        if (slots && n_res > 0) {
                                for (i = 0; i < n_res; i++) {
-                                       fprintf(F, "reg #%d = %s\n", i, slots[i] ? slots[i]->name : "n/a");
+                                       const arch_register_t *reg;
+
+                                       /* retrieve "real" x87 register */
+                                       if (ia32_has_x87_register(n))
+                                               reg = get_ia32_attr(n)->x87[i + 2];
+                                       else
+                                               reg = slots[i];
+
+                                       fprintf(F, "reg #%d = %s\n", i, reg ? arch_register_get_name(reg) : "n/a");
                                }
                                fprintf(F, "\n");
                        }
@@ -962,7 +976,7 @@ void set_ia32_out_req_all(ir_node *node, const ia32_register_req_t **reqs) {
  */
 const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
        ia32_attr_t *attr = get_ia32_attr(node);
-       return attr->in_req[pos];
+       return attr->in_req != NULL ? attr->in_req[pos] : NULL;
 }
 
 /**
@@ -970,7 +984,7 @@ const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
  */
 const ia32_register_req_t *get_ia32_out_req(const ir_node *node, int pos) {
        ia32_attr_t *attr = get_ia32_attr(node);
-       return attr->out_req[pos];
+       return attr->out_req != NULL ? attr->out_req[pos] : NULL;
 }
 
 /**
@@ -1061,6 +1075,23 @@ void set_ia32_pncode(ir_node *node, long code) {
        attr->pn_code     = code;
 }
 
+/**
+ * Sets the flags for the n'th out.
+ */
+void set_ia32_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
+       ia32_attr_t *attr = get_ia32_attr(node);
+       assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+       attr->out_flags[pos] = flags;
+}
+
+/**
+ * Gets the flags for the n'th out.
+ */
+arch_irn_flags_t get_ia32_out_flags(const ir_node *node, int pos) {
+       ia32_attr_t *attr = get_ia32_attr(node);
+       return pos < (int)attr->data.n_res ? attr->out_flags[pos] : arch_irn_flags_none;
+}
+
 #ifndef NDEBUG
 
 /**
@@ -1274,7 +1305,6 @@ int is_ia32_Cnst(const ir_node *node) {
 const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
        ia32_attr_t *attr = get_ia32_attr(node);
 
-       assert(is_ia32_irn(node) && "Not an ia32 node.");
        assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
        assert(attr->slots[pos]  && "No register assigned");
 
@@ -1287,7 +1317,6 @@ const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
 int get_ia32_out_regnr(const ir_node *node, int pos) {
        ia32_attr_t *attr = get_ia32_attr(node);
 
-       assert(is_ia32_irn(node) && "Not an ia32 node.");
        assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
        assert(attr->slots[pos]  && "No register assigned");
 
@@ -1300,7 +1329,6 @@ int get_ia32_out_regnr(const ir_node *node, int pos) {
 const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
        ia32_attr_t *attr = get_ia32_attr(node);
 
-       assert(is_ia32_irn(node) && "Not an ia32 node.");
        assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
        assert(attr->slots[pos]  && "No register assigned");
 
@@ -1319,6 +1347,9 @@ void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_regi
        set_ia32_out_req_all(node, out_reqs);
        set_ia32_latency(node, latency);
 
+       attr->out_flags = NEW_ARR_D(int, get_irg_obstack(get_irn_irg(node)), n_res);
+       memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
+
        attr->data.n_res = n_res;
        memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
 }