case dump_node_nodeattr_txt:
if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
- char *pref = is_ia32_ImmSymConst(n) ? "SymC" : "";
+ char *pref = is_ia32_ImmSymConst(n) ? "SymC" : "";
const char *cnst = get_ia32_cnst(n);
fprintf(F, "[%s%s]", pref, cnst ? cnst : "NONE");
extend_ia32_am_offs(node, (char *)offset, '-');
}
+/**
+ * Returns the symconst ident associated to addrmode.
+ */
+ident *get_ia32_am_sc(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->am_sc;
+}
+
+/**
+ * Sets the symconst ident associated to addrmode.
+ */
+void set_ia32_am_sc(ir_node *node, ident *sc) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->am_sc = sc;
+}
+
+/**
+ * Sets the sign bit for address mode symconst.
+ */
+void set_ia32_am_sc_sign(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.am_sc_sign = 1;
+}
+
+/**
+ * Clears the sign bit for address mode symconst.
+ */
+void clear_ia32_am_sc_sign(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.am_sc_sign = 0;
+}
+
+/**
+ * Returns the sign bit for address mode symconst.
+ */
+int is_ia32_am_sc_sign(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->data.am_sc_sign;
+}
+
/**
* Gets the addr mode const.
*/
return attr->data.is_commutative;
}
+/**
+ * Sets node emit_cl.
+ */
+void set_ia32_emit_cl(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.emit_cl = 1;
+}
+
+/**
+ * Clears node emit_cl.
+ */
+void clear_ia32_emit_cl(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.emit_cl = 0;
+}
+
+/**
+ * Checks if node is commutative.
+ */
+int is_ia32_emit_cl(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->data.emit_cl;
+}
+
/**
* Gets the mode of the stored/loaded value (only set for Store/Load)
*/
* Checks if node is a Load or fLoad/vfLoad.
*/
int is_ia32_Ld(const ir_node *node) {
- return is_ia32_Load(node) || is_ia32_fLoad(node) || is_ia32_vfld(node);
+ return is_ia32_Load(node) || is_ia32_fLoad(node) || is_ia32_vfld(node) || is_ia32_fld(node);
}
/**
* Checks if node is a Store or fStore/vfStore.
*/
int is_ia32_St(const ir_node *node) {
- return is_ia32_Store(node) || is_ia32_fStore(node) || is_ia32_vfst(node);
+ return is_ia32_Store(node) || is_ia32_fStore(node) || is_ia32_vfst(node) || is_ia32_fst(node) || is_ia32_fstp(node);
}
/**
ia32_attr_t *attr = get_ia32_attr(node);
if (num) {
- attr->slots = NEW_ARR_D(arch_register_t*, get_irg_obstack(get_irn_irg(node)), num);
+ attr->slots = (const arch_register_t **)NEW_ARR_D(arch_register_t*, get_irg_obstack(get_irn_irg(node)), num);
memset(attr->slots, 0, sizeof(attr->slots[0]) * num);
}
else {
memcpy(attr_new, attr_old, sizeof(*attr_new));
/* copy the register slots */
- attr_new->slots = NEW_ARR_D(arch_register_t*, get_irg_obstack(get_irn_irg(new_node)), n_res);
+ attr_new->slots = (const arch_register_t **)NEW_ARR_D(arch_register_t*, get_irg_obstack(get_irn_irg(new_node)), n_res);
memcpy((void *)attr_new->slots, (void *)attr_old->slots, sizeof(attr_new->slots[0]) * n_res);
}