/**
* This file implements the creation of the achitecture specific firm opcodes
- * and the coresponding node constructors for the $arch assembler irg.
+ * and the coresponding node constructors for the ia32 assembler irg.
* @author Christian Wuerdig
* $Id$
*/
#include "config.h"
#endif
-#ifdef _WIN32
+#ifdef HAVE_MALLOC_H
#include <malloc.h>
-#else
+#endif
+
+#ifdef HAVE_ALLOCA_H
#include <alloca.h>
#endif
#include "ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
-#ifdef obstack_chunk_alloc
-# undef obstack_chunk_alloc
-# define obstack_chunk_alloc xmalloc
-#else
-# define obstack_chunk_alloc xmalloc
-# define obstack_chunk_free free
-#endif
-
-extern int obstack_printf(struct obstack *obst, char *fmt, ...);
-
/**
* Returns the ident of a SymConst.
* @param symc The SymConst
* @param reason indicates which kind of information should be dumped
* @return 0 on success or != 0 on failure
*/
-static int dump_node_ia32(ir_node *n, FILE *F, dump_reason_t reason) {
+static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
ir_mode *mode = NULL;
int bad = 0;
int i, n_res, am_flav, flags;
break;
case dump_node_nodeattr_txt:
- if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
- char *pref = is_ia32_ImmSymConst(n) ? "SymC" : "";
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n) || is_ia32_Cnst(n)) {
+ char *pref = is_ia32_ImmSymConst(n) || (get_ia32_op_type(n) == ia32_SymConst) ? "SymC " : "";
const char *cnst = get_ia32_cnst(n);
fprintf(F, "[%s%s]", pref, cnst ? cnst : "NONE");
}
fprintf(F, "\n");
+ /* dump immop type */
+ fprintf(F, "immediate = ");
+ switch (get_ia32_immop_type(n)) {
+ case ia32_ImmNone:
+ fprintf(F, "None");
+ break;
+ case ia32_ImmConst:
+ fprintf(F, "Const");
+ break;
+ case ia32_ImmSymConst:
+ fprintf(F, "SymConst");
+ break;
+ default:
+ fprintf(F, "unknown (%d)", get_ia32_immop_type(n));
+ break;
+ }
+ fprintf(F, "\n");
/* dump supported am */
fprintf(F, "AM support = ");
/* commutative */
fprintf(F, "commutative = %d\n", is_ia32_commutative(n));
+ /* emit cl */
+ fprintf(F, "emit cl instead of ecx = %d\n", is_ia32_emit_cl(n));
+
+ /* got lea */
+ fprintf(F, "got loea = %d\n", is_ia32_got_lea(n));
+
+ /* got reload */
+ fprintf(F, "got reload = %d\n", is_ia32_got_reload(n));
+
+ /* dump latency */
+ fprintf(F, "latency = %d\n", get_ia32_latency(n));
+
/* dump flags */
fprintf(F, "flags =");
flags = get_ia32_flags(n);
if (flags & arch_irn_flags_ignore) {
fprintf(F, " ignore");
}
+ if (flags & arch_irn_flags_modify_sp) {
+ fprintf(F, " modify_sp");
+ }
}
fprintf(F, " (%d)\n", flags);
}
fprintf(F, "\n");
+ /* dump modes */
+ fprintf(F, "ls_mode = ");
+ if (get_ia32_ls_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_ls_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ fprintf(F, "res_mode = ");
+ if (get_ia32_res_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_res_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ fprintf(F, "src_mode = ");
+ if (get_ia32_src_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_src_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ fprintf(F, "tgt_mode = ");
+ if (get_ia32_tgt_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_tgt_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
#ifndef NDEBUG
/* dump original ir node name */
fprintf(F, "orig node = ");
*/
static ident *get_ident_for_tv(tarval *tv) {
char buf[1024];
-
- assert(tarval_snprintf(buf, sizeof(buf), tv));
+ int len = tarval_snprintf(buf, sizeof(buf), tv);
+ assert(len);
return new_id_from_str(buf);
}
return NULL;
}
+ if (! attr->plain_offs)
+ attr->plain_offs = (struct obstack *)_new_arr_d(get_irg_obstack(get_irn_irg(node)), 1, sizeof(*(attr->plain_offs)));
+ else
+ obstack_free(attr->plain_offs, NULL);
+
+ obstack_init(attr->plain_offs);
+
size = obstack_object_size(attr->am_offs);
if (size > 0) {
- res = xmalloc(size + 2);
+ res = obstack_alloc(attr->plain_offs, size + 2);
res[0] = attr->data.offs_sign ? '-' : '+';
memcpy(&res[1], obstack_base(attr->am_offs), size);
res[size + 1] = '\0';
if (! attr->am_offs) {
/* obstack is not initialized */
- attr->am_offs = xcalloc(1, sizeof(*(attr->am_offs)));
+ attr->am_offs = (struct obstack *)_new_arr_d(get_irg_obstack(get_irn_irg(node)), 1, sizeof(*(attr->am_offs)));
obstack_init(attr->am_offs);
attr->data.offs_sign = (op == '-') ? 1 : 0;
}
/**
- * Checks if node is commutative.
+ * Checks if node needs %cl.
*/
int is_ia32_emit_cl(const ir_node *node) {
ia32_attr_t *attr = get_ia32_attr(node);
return attr->data.emit_cl;
}
+/**
+ * Sets node got_lea.
+ */
+void set_ia32_got_lea(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.got_lea = 1;
+}
+
+/**
+ * Clears node got_lea.
+ */
+void clear_ia32_got_lea(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.got_lea = 0;
+}
+
+/**
+ * Checks if node got lea.
+ */
+int is_ia32_got_lea(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->data.got_lea;
+}
+
+/**
+ * Sets node got_reload.
+ */
+void set_ia32_got_reload(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.got_reload = 1;
+}
+
+/**
+ * Clears node got_reload.
+ */
+void clear_ia32_got_reload(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.got_reload = 0;
+}
+
+/**
+ * Checks if node got reload.
+ */
+int is_ia32_got_reload(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->data.got_reload;
+}
+
/**
* Gets the mode of the stored/loaded value (only set for Store/Load)
*/
}
/**
- * Gets the frame entity assigned to this node;
+ * Gets the frame entity assigned to this node.
*/
entity *get_ia32_frame_ent(const ir_node *node) {
ia32_attr_t *attr = get_ia32_attr(node);
}
/**
- * Sets the frame entity for this node;
+ * Sets the frame entity for this node.
*/
void set_ia32_frame_ent(ir_node *node, entity *ent) {
ia32_attr_t *attr = get_ia32_attr(node);
attr->frame_ent = ent;
+ set_ia32_use_frame(node);
+}
+
+
+/**
+ * Gets the instruction latency.
+ */
+unsigned get_ia32_latency(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->latency;
+}
+
+/**
+* Sets the instruction latency.
+*/
+void set_ia32_latency(ir_node *node, unsigned latency) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->latency = latency;
}
/**
*/
void set_ia32_Const_attr(ir_node *ia32_cnst, ir_node *cnst) {
ia32_attr_t *attr = get_ia32_attr(ia32_cnst);
+ ir_mode *mode;
assert(is_ia32_Cnst(ia32_cnst) && "Need ia32_Const to set Const attr");
case iro_Const:
attr->data.tp = ia32_Const;
attr->cnst_val.tv = get_Const_tarval(cnst);
+ mode = get_tarval_mode(attr->cnst_val.tv);
+ if (mode_is_reference(mode) &&
+ get_mode_null(mode) == attr->cnst_val.tv)
+ attr->cnst_val.tv = get_mode_null(mode_Is);
attr->cnst = get_ident_for_tv(attr->cnst_val.tv);
break;
case iro_SymConst:
}
/**
- * Checks if node is a Load or fLoad/vfLoad.
+ * Checks if node is a Load or xLoad/vfLoad.
*/
int is_ia32_Ld(const ir_node *node) {
- return is_ia32_Load(node) || is_ia32_fLoad(node) || is_ia32_vfld(node) || is_ia32_fld(node);
+ return is_ia32_Load(node) || is_ia32_xLoad(node) || is_ia32_vfld(node) || is_ia32_fld(node);
}
/**
- * Checks if node is a Store or fStore/vfStore.
+ * Checks if node is a Store or xStore/vfStore.
*/
int is_ia32_St(const ir_node *node) {
- return is_ia32_Store(node) || is_ia32_fStore(node) || is_ia32_vfst(node) || is_ia32_fst(node) || is_ia32_fstp(node);
+ return is_ia32_Store(node) || is_ia32_xStore(node) || is_ia32_vfst(node) || is_ia32_fst(node) || is_ia32_fstp(node);
}
/**
- * Checks if node is a Const or fConst/vfConst.
+ * Checks if node is a Const or xConst/vfConst.
*/
int is_ia32_Cnst(const ir_node *node) {
- return is_ia32_Const(node) || is_ia32_fConst(node) || is_ia32_vfConst(node);
+ return is_ia32_Const(node) || is_ia32_xConst(node) || is_ia32_vfConst(node);
}
/**
ia32_attr_t *attr = get_ia32_attr(node);
assert(is_ia32_irn(node) && "Not an ia32 node.");
- assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
ia32_attr_t *attr = get_ia32_attr(node);
assert(is_ia32_irn(node) && "Not an ia32 node.");
- assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
ia32_attr_t *attr = get_ia32_attr(node);
assert(is_ia32_irn(node) && "Not an ia32 node.");
- assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
}
-/**
- * Allocates num register slots for node.
- */
-void alloc_ia32_reg_slots(ir_node *node, int num) {
- ia32_attr_t *attr = get_ia32_attr(node);
-
- if (num) {
- attr->slots = (const arch_register_t **)NEW_ARR_D(arch_register_t*, get_irg_obstack(get_irn_irg(node)), num);
- memset(attr->slots, 0, sizeof(attr->slots[0]) * num);
- }
- else {
- attr->slots = NULL;
- }
-
- attr->data.n_res = num;
-}
-
/**
* Initializes the nodes attributes.
*/
void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs,
- const ia32_register_req_t **out_reqs, int n_res)
+ const ia32_register_req_t **out_reqs, int n_res, unsigned latency)
{
+ ia32_attr_t *attr = get_ia32_attr(node);
set_ia32_flags(node, flags);
set_ia32_in_req_all(node, in_reqs);
set_ia32_out_req_all(node, out_reqs);
- alloc_ia32_reg_slots(node, n_res);
+ set_ia32_latency(node, latency);
+
+ attr->data.n_res = n_res;
+ memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
}
/***************************************************************************************
return !equ;
}
-/* copies the ia32 attributes */
-static void ia32_copy_attr(const ir_node *old_node, ir_node *new_node) {
- ia32_attr_t *attr_old = get_ia32_attr(old_node);
- ia32_attr_t *attr_new = get_ia32_attr(new_node);
- int n_res = get_ia32_n_res(old_node);
+/* compare converts */
+int ia32_compare_conv_attr(ia32_attr_t *a, ia32_attr_t *b) {
+ int equ = ! ia32_compare_immop_attr(a, b);
- /* copy the attributes */
- memcpy(attr_new, attr_old, sizeof(*attr_new));
+ equ = equ ? (a->src_mode == b->src_mode) && (a->tgt_mode == b->tgt_mode) : equ;
- /* copy the register slots */
- attr_new->slots = (const arch_register_t **)NEW_ARR_D(arch_register_t*, get_irg_obstack(get_irn_irg(new_node)), n_res);
- memcpy((void *)attr_new->slots, (void *)attr_old->slots, sizeof(attr_new->slots[0]) * n_res);
-}
-
-/**
- * Registers the ia32_copy_attr function for all ia32 opcodes.
- */
-void ia32_register_copy_attr_func(void) {
- unsigned i, f = get_ia32_opcode_first(), l = get_ia32_opcode_last();
-
- for (i = f; i < l; i++) {
- ir_op *op = get_irp_opcode(i);
- op->ops.copy_attr = ia32_copy_attr;
- }
-}
-
-static void ia32_register_additional_opcodes(int n) {
- /* we don't need any additional opcodes */
+ return !equ;
}
/* Include the generated constructor functions */