}
fprintf(F, "\n");
+ /* dump immop type */
+ fprintf(F, "immediate = ");
+ switch (get_ia32_immop_type(n)) {
+ case ia32_ImmNone:
+ fprintf(F, "None");
+ break;
+ case ia32_ImmConst:
+ fprintf(F, "Const");
+ break;
+ case ia32_ImmSymConst:
+ fprintf(F, "SymConst");
+ break;
+ default:
+ fprintf(F, "unknown (%d)", get_ia32_immop_type(n));
+ break;
+ }
+ fprintf(F, "\n");
/* dump supported am */
fprintf(F, "AM support = ");
/* commutative */
fprintf(F, "commutative = %d\n", is_ia32_commutative(n));
+ /* emit cl */
+ fprintf(F, "emit cl instead of ecx = %d\n", is_ia32_emit_cl(n));
+
+ /* got lea */
+ fprintf(F, "got loea = %d\n", is_ia32_got_lea(n));
+
+ /* got reload */
+ fprintf(F, "got reload = %d\n", is_ia32_got_reload(n));
+
+ /* dump latency */
+ fprintf(F, "latency = %d\n", get_ia32_latency(n));
+
/* dump flags */
fprintf(F, "flags =");
flags = get_ia32_flags(n);
if (flags & arch_irn_flags_ignore) {
fprintf(F, " ignore");
}
+ if (flags & arch_irn_flags_modify_sp) {
+ fprintf(F, " modify_sp");
+ }
}
fprintf(F, " (%d)\n", flags);
}
fprintf(F, "\n");
+ /* dump modes */
+ fprintf(F, "ls_mode = ");
+ if (get_ia32_ls_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_ls_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ fprintf(F, "res_mode = ");
+ if (get_ia32_res_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_res_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ fprintf(F, "src_mode = ");
+ if (get_ia32_src_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_src_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ fprintf(F, "tgt_mode = ");
+ if (get_ia32_tgt_mode(n)) {
+ ir_fprintf(F, "%+F", get_ia32_tgt_mode(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
#ifndef NDEBUG
/* dump original ir node name */
fprintf(F, "orig node = ");
*/
static ident *get_ident_for_tv(tarval *tv) {
char buf[1024];
-
- assert(tarval_snprintf(buf, sizeof(buf), tv));
+ int len = tarval_snprintf(buf, sizeof(buf), tv);
+ assert(len);
return new_id_from_str(buf);
}
return attr->data.got_lea;
}
+/**
+ * Sets node got_reload.
+ */
+void set_ia32_got_reload(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.got_reload = 1;
+}
+
+/**
+ * Clears node got_reload.
+ */
+void clear_ia32_got_reload(ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->data.got_reload = 0;
+}
+
+/**
+ * Checks if node got reload.
+ */
+int is_ia32_got_reload(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->data.got_reload;
+}
+
/**
* Gets the mode of the stored/loaded value (only set for Store/Load)
*/
}
/**
- * Gets the frame entity assigned to this node;
+ * Gets the frame entity assigned to this node.
*/
entity *get_ia32_frame_ent(const ir_node *node) {
ia32_attr_t *attr = get_ia32_attr(node);
}
/**
- * Sets the frame entity for this node;
+ * Sets the frame entity for this node.
*/
void set_ia32_frame_ent(ir_node *node, entity *ent) {
ia32_attr_t *attr = get_ia32_attr(node);
attr->frame_ent = ent;
+ set_ia32_use_frame(node);
+}
+
+
+/**
+ * Gets the instruction latency.
+ */
+unsigned get_ia32_latency(const ir_node *node) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ return attr->latency;
+}
+
+/**
+* Sets the instruction latency.
+*/
+void set_ia32_latency(ir_node *node, unsigned latency) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+ attr->latency = latency;
}
/**
*/
void set_ia32_Const_attr(ir_node *ia32_cnst, ir_node *cnst) {
ia32_attr_t *attr = get_ia32_attr(ia32_cnst);
+ ir_mode *mode;
assert(is_ia32_Cnst(ia32_cnst) && "Need ia32_Const to set Const attr");
case iro_Const:
attr->data.tp = ia32_Const;
attr->cnst_val.tv = get_Const_tarval(cnst);
+ mode = get_tarval_mode(attr->cnst_val.tv);
+ if (mode_is_reference(mode) &&
+ get_mode_null(mode) == attr->cnst_val.tv)
+ attr->cnst_val.tv = get_mode_null(mode_Is);
attr->cnst = get_ident_for_tv(attr->cnst_val.tv);
break;
case iro_SymConst:
ia32_attr_t *attr = get_ia32_attr(node);
assert(is_ia32_irn(node) && "Not an ia32 node.");
- assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_name(attr->slots[pos]);
ia32_attr_t *attr = get_ia32_attr(node);
assert(is_ia32_irn(node) && "Not an ia32 node.");
- assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return arch_register_get_index(attr->slots[pos]);
ia32_attr_t *attr = get_ia32_attr(node);
assert(is_ia32_irn(node) && "Not an ia32 node.");
- assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
assert(attr->slots[pos] && "No register assigned");
return attr->slots[pos];
* Initializes the nodes attributes.
*/
void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs,
- const ia32_register_req_t **out_reqs, int n_res)
+ const ia32_register_req_t **out_reqs, int n_res, unsigned latency)
{
ia32_attr_t *attr = get_ia32_attr(node);
set_ia32_flags(node, flags);
set_ia32_in_req_all(node, in_reqs);
set_ia32_out_req_all(node, out_reqs);
+ set_ia32_latency(node, latency);
attr->data.n_res = n_res;
memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
projects / libfirm / blobdiff