/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
* to int conversion which are specified as truncation in the C standard we have
* to spill, change and restore the fpu rounding mode between spills.
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include "ia32_fpu.h"
#include "ia32_new_nodes.h"
set_entity_allocation(ent, allocation_static);
cnst_irg = get_const_code_irg();
- cnst = new_r_Const(cnst_irg, get_irg_start_block(cnst_irg), mode, tv);
+ cnst = new_r_Const(cnst_irg, tv);
set_atomic_ent_value(ent, cnst);
return ent;
/* we don't spill the fpcw in unsafe mode */
if(ia32_cg_config.use_unsafe_floatconv) {
- ir_graph *irg = get_irn_irg(state);
ir_node *block = get_nodes_block(state);
if(force == 1 || !is_ia32_ChangeCW(state)) {
- ir_node *spill = new_rd_ia32_FnstCWNOP(NULL, irg, block, state);
+ ir_node *spill = new_bd_ia32_FnstCWNOP(NULL, block, state);
sched_add_after(after, spill);
return spill;
}
ir_node *nomem = new_NoMem();
ir_node *frame = get_irg_frame(irg);
- spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, nomem, state);
+ spill = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state);
set_ia32_op_type(spill, ia32_AddrModeD);
/* use mode_Iu, as movl has a shorter opcode than movw */
set_ia32_ls_mode(spill, mode_Iu);
static ir_node *create_fldcw_ent(ia32_code_gen_t *cg, ir_node *block,
ir_entity *entity)
{
- ir_graph *irg = get_irn_irg(block);
ir_node *nomem = new_NoMem();
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *reload;
- reload = new_rd_ia32_FldCW(NULL, irg, block, noreg, noreg, nomem);
+ reload = new_bd_ia32_FldCW(NULL, block, noreg, noreg, nomem);
set_ia32_op_type(reload, ia32_AddrModeS);
set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
set_ia32_am_sc(reload, entity);
set_ia32_use_frame(reload);
- arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
+ arch_set_irn_register(reload, &ia32_fp_cw_regs[REG_FPCW]);
return reload;
}
}
if(spill != NULL) {
- reload = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, spill);
+ reload = new_bd_ia32_FldCW(NULL, block, frame, noreg, spill);
set_ia32_op_type(reload, ia32_AddrModeS);
set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
set_ia32_use_frame(reload);
- arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
+ arch_set_irn_register(reload, &ia32_fp_cw_regs[REG_FPCW]);
sched_add_before(before, reload);
} else {
ir_node *or_const;
assert(last_state != NULL);
- cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, nomem,
+ cwstore = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem,
last_state);
set_ia32_op_type(cwstore, ia32_AddrModeD);
set_ia32_ls_mode(cwstore, lsmode);
set_ia32_use_frame(cwstore);
sched_add_before(before, cwstore);
- load = new_rd_ia32_Load(NULL, irg, block, frame, noreg, cwstore);
+ load = new_bd_ia32_Load(NULL, block, frame, noreg, cwstore);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_ls_mode(load, lsmode);
set_ia32_use_frame(load);
load_res = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
/* TODO: make the actual mode configurable in ChangeCW... */
- or_const = new_rd_ia32_Immediate(NULL, irg, get_irg_start_block(irg),
+ or_const = new_bd_ia32_Immediate(NULL, get_irg_start_block(irg),
NULL, 0, 3072);
- arch_set_irn_register(cg->arch_env, or_const,
- &ia32_gp_regs[REG_GP_NOREG]);
- or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, nomem, load_res,
+ arch_set_irn_register(or_const, &ia32_gp_regs[REG_GP_NOREG]);
+ or = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res,
or_const);
sched_add_before(before, or);
- store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, nomem, or);
+ store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, or);
set_ia32_op_type(store, ia32_AddrModeD);
/* use mode_Iu, as movl has a shorter opcode than movw */
set_ia32_ls_mode(store, mode_Iu);
set_ia32_use_frame(store);
sched_add_before(before, store);
- fldcw = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, store);
+ fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store);
set_ia32_op_type(fldcw, ia32_AddrModeS);
set_ia32_ls_mode(fldcw, lsmode);
set_ia32_use_frame(fldcw);
- arch_set_irn_register(cg->arch_env, fldcw, &ia32_fp_cw_regs[REG_FPCW]);
+ arch_set_irn_register(fldcw, &ia32_fp_cw_regs[REG_FPCW]);
sched_add_before(before, fldcw);
reload = fldcw;
}
typedef struct collect_fpu_mode_nodes_env_t {
- const arch_env_t *arch_env;
ir_node **state_nodes;
} collect_fpu_mode_nodes_env_t;
if(!mode_is_data(get_irn_mode(node)))
return;
- reg = arch_get_irn_register(env->arch_env, node);
+ reg = arch_get_irn_register(node);
if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
ARR_APP1(ir_node*, env->state_nodes, node);
}
int i, len;
/* do ssa construction for the fpu modes */
- env.arch_env = be_get_birg_arch_env(birg);
env.state_nodes = NEW_ARR_F(ir_node*, 0);
irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env);
len = ARR_LEN(phis);
for(i = 0; i < len; ++i) {
ir_node *phi = phis[i];
- be_set_phi_flags(env.arch_env, phi, arch_irn_flags_ignore);
- arch_set_irn_register(env.arch_env, phi, reg);
+ arch_set_irn_register(phi, reg);
}
be_ssa_construction_destroy(&senv);
DEL_ARR_F(env.state_nodes);
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