/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
#include "ia32_fpu.h"
#include "ia32_new_nodes.h"
+#include "ia32_architecture.h"
#include "gen_ia32_regalloc_if.h"
#include "ircons.h"
#include "../bessaconstr.h"
#include "../beirg_t.h"
+static ir_entity *fpcw_round = NULL;
+static ir_entity *fpcw_truncate = NULL;
+
+static ir_entity *create_ent(int value, const char *name)
+{
+ ir_mode *mode = mode_Hu;
+ ir_type *type = new_type_primitive(new_id_from_str("_fpcw_type"), mode);
+ ir_type *glob = get_glob_type();
+ ir_graph *cnst_irg;
+ ir_entity *ent;
+ ir_node *cnst;
+ tarval *tv;
+
+ set_type_alignment_bytes(type, 4);
+
+ tv = new_tarval_from_long(value, mode);
+ ent = new_entity(glob, new_id_from_str(name), type);
+ set_entity_ld_ident(ent, get_entity_ident(ent));
+ set_entity_visibility(ent, visibility_local);
+ set_entity_variability(ent, variability_constant);
+ set_entity_allocation(ent, allocation_static);
+
+ cnst_irg = get_const_code_irg();
+ cnst = new_r_Const(cnst_irg, get_irg_start_block(cnst_irg), mode, tv);
+ set_atomic_ent_value(ent, cnst);
+
+ return ent;
+}
+
+static void create_fpcw_entities(void)
+{
+ fpcw_round = create_ent(0xc7f, "_fpcw_round");
+ fpcw_truncate = create_ent(0x37f, "_fpcw_truncate");
+}
+
static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
ir_node *after)
{
ia32_code_gen_t *cg = env;
ir_node *spill = NULL;
+ /* we don't spill the fpcw in unsafe mode */
+ if(ia32_cg_config.use_unsafe_floatconv) {
+ ir_graph *irg = get_irn_irg(state);
+ ir_node *block = get_nodes_block(state);
+ if(force == 1 || !is_ia32_ChangeCW(state)) {
+ ir_node *spill = new_rd_ia32_FnstCWNOP(NULL, irg, block, state);
+ sched_add_after(after, spill);
+ return spill;
+ }
+ return NULL;
+ }
+
if(force == 1 || !is_ia32_ChangeCW(state)) {
ir_graph *irg = get_irn_irg(state);
ir_node *block = get_nodes_block(state);
ir_node *nomem = new_NoMem();
ir_node *frame = get_irg_frame(irg);
- spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, state,
- nomem);
- set_ia32_am_support(spill, ia32_am_Dest);
+ spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, nomem, state);
set_ia32_op_type(spill, ia32_AddrModeD);
- set_ia32_am_flavour(spill, ia32_B);
- set_ia32_ls_mode(spill, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
+ /* use mode_Iu, as movl has a shorter opcode than movw */
+ set_ia32_ls_mode(spill, mode_Iu);
set_ia32_use_frame(spill);
sched_add_after(after, spill);
return spill;
}
+static ir_node *create_fldcw_ent(ia32_code_gen_t *cg, ir_node *block,
+ ir_entity *entity)
+{
+ ir_graph *irg = get_irn_irg(block);
+ ir_node *nomem = new_NoMem();
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *reload;
+
+ reload = new_rd_ia32_FldCW(NULL, irg, block, noreg, noreg, nomem);
+ set_ia32_op_type(reload, ia32_AddrModeS);
+ set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
+ set_ia32_am_sc(reload, entity);
+ set_ia32_use_frame(reload);
+ arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
+
+ return reload;
+}
+
static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
ir_node *spill, ir_node *before,
ir_node *last_state)
{
- ia32_code_gen_t *cg = env;
- ir_graph *irg = get_irn_irg(state);
- ir_node *block = get_nodes_block(before);
- ir_node *frame = get_irg_frame(irg);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *reload = NULL;
+ ia32_code_gen_t *cg = env;
+ ir_graph *irg = get_irn_irg(state);
+ ir_node *block = get_nodes_block(before);
+ ir_node *frame = get_irg_frame(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *reload = NULL;
+
+ if(ia32_cg_config.use_unsafe_floatconv) {
+ if(fpcw_round == NULL) {
+ create_fpcw_entities();
+ }
+ if(spill != NULL) {
+ reload = create_fldcw_ent(cg, block, fpcw_round);
+ } else {
+ reload = create_fldcw_ent(cg, block, fpcw_truncate);
+ }
+ sched_add_before(before, reload);
+ return reload;
+ }
if(spill != NULL) {
reload = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, spill);
- set_ia32_am_support(reload, ia32_am_Source);
set_ia32_op_type(reload, ia32_AddrModeS);
- set_ia32_am_flavour(reload, ia32_B);
set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
set_ia32_use_frame(reload);
arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
ir_node *nomem = new_NoMem();
ir_node *cwstore, *load, *load_res, *or, *store, *fldcw;
+ ir_node *or_const;
assert(last_state != NULL);
- cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, last_state,
- nomem);
- set_ia32_am_support(cwstore, ia32_am_Dest);
+ cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, nomem,
+ last_state);
set_ia32_op_type(cwstore, ia32_AddrModeD);
- set_ia32_am_flavour(cwstore, ia32_B);
set_ia32_ls_mode(cwstore, lsmode);
set_ia32_use_frame(cwstore);
sched_add_before(before, cwstore);
load = new_rd_ia32_Load(NULL, irg, block, frame, noreg, cwstore);
- set_ia32_am_support(load, ia32_am_Source);
set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_am_flavour(load, ia32_B);
set_ia32_ls_mode(load, lsmode);
set_ia32_use_frame(load);
sched_add_before(before, load);
load_res = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
-#ifdef SCHEDULE_PROJS
- sched_add_before(before, load_res);
-#endif
/* TODO: make the actual mode configurable in ChangeCW... */
- or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, load_res, noreg,
- nomem);
- set_ia32_Immop_tarval(or, new_tarval_from_long(3072, mode_Iu));
+ or_const = new_rd_ia32_Immediate(NULL, irg, get_irg_start_block(irg),
+ NULL, 0, 3072);
+ arch_set_irn_register(cg->arch_env, or_const,
+ &ia32_gp_regs[REG_GP_NOREG]);
+ or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, nomem, load_res,
+ or_const);
sched_add_before(before, or);
- store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, or, nomem);
- set_ia32_am_support(store, ia32_am_Dest);
+ store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, nomem, or);
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_B);
- set_ia32_ls_mode(store, lsmode);
+ /* use mode_Iu, as movl has a shorter opcode than movw */
+ set_ia32_ls_mode(store, mode_Iu);
set_ia32_use_frame(store);
sched_add_before(before, store);
fldcw = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, store);
- set_ia32_am_support(fldcw, ia32_am_Source);
set_ia32_op_type(fldcw, ia32_AddrModeS);
- set_ia32_am_flavour(fldcw, ia32_B);
set_ia32_ls_mode(fldcw, lsmode);
set_ia32_use_frame(fldcw);
arch_set_irn_register(cg->arch_env, fldcw, &ia32_fp_cw_regs[REG_FPCW]);
ir_node **state_nodes;
} collect_fpu_mode_nodes_env_t;
-static
-void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
+static void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
{
collect_fpu_mode_nodes_env_t *env = data;
+ const arch_register_t *reg;
+
+ if(!mode_is_data(get_irn_mode(node)))
+ return;
- const arch_register_t *reg = arch_get_irn_register(env->arch_env, node);
+ reg = arch_get_irn_register(env->arch_env, node);
if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
ARR_APP1(ir_node*, env->state_nodes, node);
}
projects / libfirm / blobdiff