ia32_x87: remove the distinction between vfp and fp concepts

[libfirm] / ir / be / ia32 / ia32_fpu.c

diff --git a/ir/be/ia32/ia32_fpu.c b/ir/be/ia32/ia32_fpu.c
index 9a27116..54e0680 100644 (file)
--- a/ir/be/ia32/ia32_fpu.c
+++ b/ir/be/ia32/ia32_fpu.c
@@ -21,7 +21,6 @@
  * @file
  * @brief   Handles fpu rounding modes
  * @author  Matthias Braun
- * @version $Id$
  *
  * The problem we deal with here is that the x86 ABI says the user can control
  * the fpu rounding mode, which means that when we do some operations like float
@@ -40,15 +39,15 @@
 #include "tv.h"
 #include "array.h"
 
-#include "../beirgmod.h"
-#include "../bearch.h"
-#include "../besched.h"
-#include "../beabi.h"
-#include "../benode.h"
-#include "../bestate.h"
-#include "../beutil.h"
-#include "../bessaconstr.h"
-#include "../beirg.h"
+#include "beirgmod.h"
+#include "bearch.h"
+#include "besched.h"
+#include "beabi.h"
+#include "benode.h"
+#include "bestate.h"
+#include "beutil.h"
+#include "bessaconstr.h"
+#include "beirg.h"
 
 static ir_entity *fpcw_round    = NULL;
 static ir_entity *fpcw_truncate = NULL;
@@ -61,7 +60,7 @@ static ir_entity *create_ent(int value, const char *name)
        ir_graph  *cnst_irg;
        ir_entity *ent;
        ir_node   *cnst;
-       tarval    *tv;
+       ir_tarval *tv;
 
        set_type_alignment_bytes(type, 4);
 
@@ -87,7 +86,6 @@ static void create_fpcw_entities(void)
 static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
                                       ir_node *after)
 {
-       ir_node *spill = NULL;
        (void) env;
 
        /* we don't spill the fpcw in unsafe mode */
@@ -105,25 +103,26 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
                ir_graph *irg = get_irn_irg(state);
                ir_node *block = get_nodes_block(state);
                ir_node *noreg = ia32_new_NoReg_gp(irg);
-               ir_node *nomem = new_r_NoMem(irg);
+               ir_node *nomem = get_irg_no_mem(irg);
                ir_node *frame = get_irg_frame(irg);
-
-               spill = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state);
+               ir_node *spill
+                       = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state);
                set_ia32_op_type(spill, ia32_AddrModeD);
                /* use mode_Iu, as movl has a shorter opcode than movw */
                set_ia32_ls_mode(spill, mode_Iu);
                set_ia32_use_frame(spill);
 
                sched_add_after(skip_Proj(after), spill);
+               return spill;
        }
 
-       return spill;
+       return NULL;
 }
 
 static ir_node *create_fldcw_ent(ir_node *block, ir_entity *entity)
 {
        ir_graph *irg   = get_irn_irg(block);
-       ir_node  *nomem = new_r_NoMem(irg);
+       ir_node  *nomem = get_irg_no_mem(irg);
        ir_node  *noreg = ia32_new_NoReg_gp(irg);
        ir_node  *reload;
 
@@ -171,8 +170,9 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
                sched_add_before(before, reload);
        } else {
                ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
-               ir_node *nomem  = new_r_NoMem(irg);
-               ir_node *cwstore, *load, *load_res, *or, *store, *fldcw;
+               ir_node *nomem  = get_irg_no_mem(irg);
+               ir_node *cwstore, *load, *load_res, *orn, *store, *fldcw;
+               ir_node *store_proj;
                ir_node *or_const;
 
                assert(last_state != NULL);
@@ -195,18 +195,19 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
                or_const = new_bd_ia32_Immediate(NULL, get_irg_start_block(irg),
                                                 NULL, 0, 0, 3072);
                arch_set_irn_register(or_const, &ia32_registers[REG_GP_NOREG]);
-               or = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res,
+               orn = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res,
                                    or_const);
-               sched_add_before(before, or);
+               sched_add_before(before, orn);
 
-               store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, or);
+               store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, orn);
                set_ia32_op_type(store, ia32_AddrModeD);
                /* use mode_Iu, as movl has a shorter opcode than movw */
                set_ia32_ls_mode(store, mode_Iu);
                set_ia32_use_frame(store);
+               store_proj = new_r_Proj(store, mode_M, pn_ia32_Store_M);
                sched_add_before(before, store);
 
-               fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store);
+               fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store_proj);
                set_ia32_op_type(fldcw, ia32_AddrModeS);
                set_ia32_ls_mode(fldcw, lsmode);
                set_ia32_use_frame(fldcw);
@@ -225,7 +226,7 @@ typedef struct collect_fpu_mode_nodes_env_t {
 
 static void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
 {
-       collect_fpu_mode_nodes_env_t *env = data;
+       collect_fpu_mode_nodes_env_t *env = (collect_fpu_mode_nodes_env_t*)data;
        const arch_register_t *reg;
 
        if (!mode_is_data(get_irn_mode(node)))
@@ -245,14 +246,12 @@ static void rewire_fpu_mode_nodes(ir_graph *irg)
        ir_node *initial_value;
        ir_node **phis;
        be_lv_t *lv = be_get_irg_liveness(irg);
-       int i, len;
+       size_t i, len;
 
        /* do ssa construction for the fpu modes */
        env.state_nodes = NEW_ARR_F(ir_node*, 0);
        irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env);
 
-       initial_value = be_abi_get_ignore_irn(be_get_irg_abi(irg), reg);
-
        /* nothing needs to be done, in fact we must not continue as for endless
         * loops noone is using the initial_value and it will point to a bad node
         * now
@@ -262,6 +261,7 @@ static void rewire_fpu_mode_nodes(ir_graph *irg)
                return;
        }
 
+       initial_value = be_get_initial_reg_value(irg, reg);
        be_ssa_construction_init(&senv, irg);
        be_ssa_construction_add_copies(&senv, env.state_nodes,
                                       ARR_LEN(env.state_nodes));
@@ -275,7 +275,7 @@ static void rewire_fpu_mode_nodes(ir_graph *irg)
                        be_liveness_update(lv, env.state_nodes[i]);
                }
        } else {
-               be_liveness_invalidate(be_get_irg_liveness(irg));
+               be_invalidate_live_sets(irg);
        }
 
        /* set registers for the phis */
@@ -288,7 +288,7 @@ static void rewire_fpu_mode_nodes(ir_graph *irg)
        be_ssa_construction_destroy(&senv);
        DEL_ARR_F(env.state_nodes);
 
-       be_liveness_invalidate(be_get_irg_liveness(irg));
+       be_invalidate_live_sets(irg);
 }
 
 void ia32_setup_fpu_mode(ir_graph *irg)