ConvI2I8Bit is also a transformed Load

[libfirm] / ir / be / ia32 / ia32_fpu.c

diff --git a/ir/be/ia32/ia32_fpu.c b/ir/be/ia32/ia32_fpu.c
index faf9f57..53eecf5 100644 (file)
--- a/ir/be/ia32/ia32_fpu.c
+++ b/ir/be/ia32/ia32_fpu.c
@@ -64,11 +64,8 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
                ir_node *nomem = new_NoMem();
                ir_node *frame = get_irg_frame(irg);
 
-               spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, state,
-                                          nomem);
-               set_ia32_am_support(spill, ia32_am_Dest);
+               spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, nomem, state);
                set_ia32_op_type(spill, ia32_AddrModeD);
-               set_ia32_am_flavour(spill, ia32_B);
                set_ia32_ls_mode(spill, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
                set_ia32_use_frame(spill);
 
@@ -91,9 +88,7 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
 
        if(spill != NULL) {
                reload = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, spill);
-               set_ia32_am_support(reload, ia32_am_Source);
                set_ia32_op_type(reload, ia32_AddrModeS);
-               set_ia32_am_flavour(reload, ia32_B);
                set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
                set_ia32_use_frame(reload);
                arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
@@ -103,46 +98,41 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
                ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
                ir_node *nomem = new_NoMem();
                ir_node *cwstore, *load, *load_res, *or, *store, *fldcw;
+               ir_node *or_const;
 
                assert(last_state != NULL);
-               cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, last_state,
-                                            nomem);
-               set_ia32_am_support(cwstore, ia32_am_Dest);
+               cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, nomem,
+                                            last_state);
                set_ia32_op_type(cwstore, ia32_AddrModeD);
-               set_ia32_am_flavour(cwstore, ia32_B);
                set_ia32_ls_mode(cwstore, lsmode);
                set_ia32_use_frame(cwstore);
                sched_add_before(before, cwstore);
 
                load = new_rd_ia32_Load(NULL, irg, block, frame, noreg, cwstore);
-               set_ia32_am_support(load, ia32_am_Source);
                set_ia32_op_type(load, ia32_AddrModeS);
-               set_ia32_am_flavour(load, ia32_B);
                set_ia32_ls_mode(load, lsmode);
                set_ia32_use_frame(load);
                sched_add_before(before, load);
 
                load_res = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
-               sched_add_before(before, load_res);
 
                /* TODO: make the actual mode configurable in ChangeCW... */
-               or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, load_res, noreg,
-                                   nomem);
-               set_ia32_Immop_tarval(or, new_tarval_from_long(3072, mode_Iu));
+               or_const = new_rd_ia32_Immediate(NULL, irg, get_irg_start_block(irg),
+                                                NULL, 0, 3072);
+               arch_set_irn_register(cg->arch_env, or_const,
+                                     &ia32_gp_regs[REG_GP_NOREG]);
+               or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, nomem, load_res,
+                                   or_const);
                sched_add_before(before, or);
 
-               store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, or, nomem);
-               set_ia32_am_support(store, ia32_am_Dest);
+               store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, nomem, or);
                set_ia32_op_type(store, ia32_AddrModeD);
-               set_ia32_am_flavour(store, ia32_B);
                set_ia32_ls_mode(store, lsmode);
                set_ia32_use_frame(store);
                sched_add_before(before, store);
 
                fldcw = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, store);
-               set_ia32_am_support(fldcw, ia32_am_Source);
                set_ia32_op_type(fldcw, ia32_AddrModeS);
-               set_ia32_am_flavour(fldcw, ia32_B);
                set_ia32_ls_mode(fldcw, lsmode);
                set_ia32_use_frame(fldcw);
                arch_set_irn_register(cg->arch_env, fldcw, &ia32_fp_cw_regs[REG_FPCW]);
@@ -163,8 +153,12 @@ static
 void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
 {
        collect_fpu_mode_nodes_env_t *env = data;
+       const arch_register_t *reg;
 
-       const arch_register_t *reg = arch_get_irn_register(env->arch_env, node);
+       if(!mode_is_data(get_irn_mode(node)))
+               return;
+
+       reg = arch_get_irn_register(env->arch_env, node);
        if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
                ARR_APP1(ir_node*, env->state_nodes, node);
        }
@@ -210,6 +204,8 @@ void rewire_fpu_mode_nodes(be_irg_t *birg)
                for(i = 0; i < len; ++i) {
                        be_liveness_update(lv, env.state_nodes[i]);
                }
+       } else {
+               be_liveness_invalidate(birg->lv);
        }
 
        /* set registers for the phis */
@@ -222,6 +218,8 @@ void rewire_fpu_mode_nodes(be_irg_t *birg)
        }
        be_ssa_construction_destroy(&senv);
        DEL_ARR_F(env.state_nodes);
+
+       be_liveness_invalidate(be_get_birg_liveness(birg));
 }
 
 void ia32_setup_fpu_mode(ia32_code_gen_t *cg)