/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
ir_graph *irg;
ir_node *in1, *in2, *noreg, *nomem, *res;
ir_node *noreg_fp, *block;
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
- const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
- int i, arity;
+ dbg_info *dbg;
+ const arch_register_t *in1_reg, *in2_reg, *out_reg;
- /* Return if not a Sub or xSub */
- if (!is_ia32_Sub(irn) && !is_ia32_xSub(irn))
- return;
/* fix_am will solve this for AddressMode variants */
if(get_ia32_op_type(irn) != ia32_Normal)
return;
in2_reg = arch_get_irn_register(cg->arch_env, in2);
out_reg = get_ia32_out_reg(irn, 0);
- assert(get_irn_mode(irn) != mode_T);
-
irg = cg->irg;
block = get_nodes_block(irn);
if (out_reg != in2_reg)
return;
+ dbg = get_irn_dbg_info(irn);
+
/* generate the neg src2 */
- if(mode_is_float(mode)) {
+ if(is_ia32_xSub(irn)) {
int size;
ir_entity *entity;
ir_mode *op_mode = get_ia32_ls_mode(irn);
+ assert(get_irn_mode(irn) != mode_T);
+
res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp);
size = get_mode_size_bits(op_mode);
entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
set_ia32_am_sc(res, entity);
set_ia32_op_type(res, ia32_AddrModeS);
set_ia32_ls_mode(res, op_mode);
- } else {
- res = new_rd_ia32_Neg(dbg, irg, block, in2);
- }
- arch_set_irn_register(cg->arch_env, res, in2_reg);
- /* add to schedule */
- sched_add_before(irn, res);
+ arch_set_irn_register(cg->arch_env, res, in2_reg);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
- /* generate the add */
- if (mode_is_float(mode)) {
+ /* generate the add */
res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
+
+ /* exchange the add and the sub */
+ edges_reroute(irn, res, irg);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
} else {
- res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
- set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);
- set_ia32_commutative(res);
- }
+ ir_node *res_proj = NULL;
+ ir_node *flags_proj = NULL;
+ const ir_edge_t *edge;
+
+ if(get_irn_mode(irn) == mode_T) {
+ /* collect the Proj uses */
+ foreach_out_edge(irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ long pn = get_Proj_proj(proj);
+ if(pn == pn_ia32_Sub_res) {
+ assert(res_proj == NULL);
+ res_proj = proj;
+ } else {
+ assert(pn == pn_ia32_Sub_flags);
+ assert(flags_proj == NULL);
+ flags_proj = proj;
+ }
+ }
+ }
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
- /* copy register */
- slots = get_ia32_slots(res);
- slots[0] = in2_reg;
+ if (flags_proj == NULL) {
+ res = new_rd_ia32_Neg(dbg, irg, block, in2);
+ arch_set_irn_register(cg->arch_env, res, in2_reg);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
+
+ /* generate the add */
+ res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
+ arch_set_irn_register(cg->arch_env, res, out_reg);
+ set_ia32_commutative(res);
+
+ /* exchange the add and the sub */
+ edges_reroute(irn, res, irg);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
+ } else {
+ ir_node *stc, *cmc, *not, *adc;
+ ir_node *adc_flags;
+
+ /*
+ * ARG, the above technique does NOT set the flags right.
+ * So, we must produce the following code:
+ * t1 = ~b
+ * t2 = a + ~b + Carry
+ * Complement Carry
+ *
+ * a + -b = a + (~b + 1) would sat the carry flag IF a == b ...
+ */
+ not = new_rd_ia32_Not(dbg, irg, block, in2);
+ arch_set_irn_register(cg->arch_env, not, in2_reg);
+ sched_add_before(irn, not);
+
+ stc = new_rd_ia32_Stc(dbg, irg, block);
+ arch_set_irn_register(cg->arch_env, stc,
+ &ia32_flags_regs[REG_EFLAGS]);
+
+ adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not,
+ in1, stc);
+ arch_set_irn_register(cg->arch_env, adc, out_reg);
+ sched_add_before(irn, adc);
+
+ adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags);
+
+ cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags);
+ sched_add_before(irn, cmc);
+
+ exchange(flags_proj, cmc);
+ if(res_proj != NULL) {
+ set_Proj_pred(res_proj, adc);
+ set_Proj_proj(res_proj, pn_ia32_Adc_res);
+ }
- /* exchange the add and the sub */
- edges_reroute(irn, res, irg);
+ res = adc;
+ }
+ }
- /* add to schedule */
- sched_add_before(irn, res);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
/* remove the old sub */
sched_remove(irn);
- arity = get_irn_arity(irn);
- for(i = 0; i < arity; ++i) {
- set_irn_n(irn, i, new_Bad());
- }
+ be_kill_node(irn);
DBG_OPT_SUB2NEGADD(irn, res);
}
! is_ia32_CMov(irn);
}
+/**
+ * Returns the index of the "same" register.
+ * On the x86, we should have only one.
+ */
static int get_first_same(const arch_register_req_t* req)
{
const unsigned other = req->other_same;
int i;
- for (i = 0;; ++i) {
+ for (i = 0; i < 32; ++i) {
if (other & (1U << i)) return i;
}
+ assert(! "same position not found");
+ return 32;
}
/**
const arch_register_t *out_reg, *in_reg;
int n_res, i;
ir_node *in_node, *block;
- ia32_op_type_t op_tp;
- if(!is_ia32_irn(node))
- return;
-
- /* some nodes are just a bit less efficient, but need no fixing if the
- * should be same requirement is not fulfilled */
- if(!need_constraint_copy(node))
- return;
-
- op_tp = get_ia32_op_type(node);
reqs = get_ia32_out_req_all(node);
n_res = get_ia32_n_res(node);
block = get_nodes_block(node);
}
/* for commutative nodes we can simply swap the left/right */
- if(is_ia32_commutative(node) && uses_out_reg_pos == n_ia32_binary_right) {
+ if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
ia32_swap_left_right(node);
DBG((dbg, LEVEL_1, "swapped left/right input of %+F to resolve "
"should be same constraint\n", node));
next = sched_next(irn);
/* check if there is a sub which need to be transformed */
- ia32_transform_sub_to_neg_add(irn, cg);
+ if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
+ ia32_transform_sub_to_neg_add(irn, cg);
+ }
}
/* second: insert copies and finish irg */
for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
next = sched_next(irn);
- assure_should_be_same_requirements(cg, irn);
+ if (is_ia32_irn(irn)) {
+ /* some nodes are just a bit less efficient, but need no fixing if the
+ * should be same requirement is not fulfilled */
+ if (need_constraint_copy(irn))
+ assure_should_be_same_requirements(cg, irn);
+ }
}
}
projects / libfirm / blobdiff