* register -> base or index is broken then.
* Solution: Turn back this address mode into explicit Load + Operation.
*/
-static void fix_am_source(ir_node *irn, void *env) {
+static void fix_am_source(ir_node *irn, void *env)
+{
ia32_code_gen_t *cg = env;
const arch_env_t *arch_env = cg->arch_env;
ir_node *base;
if (get_ia32_am_arity(irn) != ia32_am_binary)
return;
- base = get_irn_n(irn, 0);
- index = get_irn_n(irn, 1);
+ base = get_irn_n(irn, n_ia32_base);
+ index = get_irn_n(irn, n_ia32_index);
reg_base = arch_get_irn_register(arch_env, base);
reg_index = arch_get_irn_register(arch_env, index);
/* copy address mode information to load */
set_ia32_op_type(load, ia32_AddrModeS);
ia32_copy_am_attrs(load, irn);
+ if (is_ia32_is_reload(irn))
+ set_ia32_is_reload(load);
/* insert the load into schedule */
sched_add_before(irn, load);
foreach_out_edge_safe(irn, edge, next) {
ir_node *node = get_edge_src_irn(edge);
int pn = get_Proj_proj(node);
- if(pn == 0) {
+ if (pn == pn_ia32_res) {
exchange(node, irn);
- } else if(pn == pn_ia32_mem) {
+ } else if (pn == pn_ia32_mem) {
set_Proj_pred(node, load);
set_Proj_proj(node, pnmem);
+ } else {
+ panic("Unexpected Proj");
}
}
set_irn_mode(irn, mode_Iu);