* register -> base or index is broken then.
* Solution: Turn back this address mode into explicit Load + Operation.
*/
-static void fix_am_source(ir_node *irn, void *env) {
+static void fix_am_source(ir_node *irn, void *env)
+{
ia32_code_gen_t *cg = env;
const arch_env_t *arch_env = cg->arch_env;
ir_node *base;
/* copy address mode information to load */
set_ia32_op_type(load, ia32_AddrModeS);
ia32_copy_am_attrs(load, irn);
+ if (is_ia32_is_reload(irn))
+ set_ia32_is_reload(load);
/* insert the load into schedule */
sched_add_before(irn, load);
} else if (pn == pn_ia32_mem) {
set_Proj_pred(node, load);
set_Proj_proj(node, pnmem);
+ } else {
+ panic("Unexpected Proj");
}
}
set_irn_mode(irn, mode_Iu);