#include "bearch_ia32_t.h"
#include "ia32_finish.h"
#include "ia32_new_nodes.h"
-#include "ia32_map_regs.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
ir_graph *irg;
ir_node *in1, *in2, *noreg, *nomem, *res;
ir_node *noreg_fp, *block;
- dbg_info *dbg;
+ dbg_info *dbgi;
const arch_register_t *in1_reg, *in2_reg, *out_reg;
/* fix_am will solve this for AddressMode variants */
irg = get_irn_irg(irn);
noreg = ia32_new_NoReg_gp(irg);
noreg_fp = ia32_new_NoReg_xmm(irg);
- nomem = new_r_NoMem(irg);
+ nomem = get_irg_no_mem(irg);
in1 = get_irn_n(irn, n_ia32_binary_left);
in2 = get_irn_n(irn, n_ia32_binary_right);
in1_reg = arch_get_irn_register(in1);
return;
block = get_nodes_block(irn);
- dbg = get_irn_dbg_info(irn);
+ dbgi = get_irn_dbg_info(irn);
/* generate the neg src2 */
if (is_ia32_xSub(irn)) {
assert(get_irn_mode(irn) != mode_T);
- res = new_bd_ia32_xXor(dbg, block, noreg, noreg, nomem, in2, noreg_fp);
+ res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp);
size = get_mode_size_bits(op_mode);
entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
set_ia32_am_sc(res, entity);
sched_add_before(irn, res);
/* generate the add */
- res = new_bd_ia32_xAdd(dbg, block, noreg, noreg, nomem, res, in1);
+ res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1);
set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
/* exchange the add and the sub */
- edges_reroute(irn, res, irg);
+ edges_reroute(irn, res);
/* add to schedule */
sched_add_before(irn, res);
} else {
ir_node *res_proj = NULL;
ir_node *flags_proj = NULL;
+ ir_node *carry;
const ir_edge_t *edge;
if (get_irn_mode(irn) == mode_T) {
/* collect the Proj uses */
+ assert(pn_ia32_Sub_res == pn_ia32_Sbb_res);
+ assert(pn_ia32_Sub_flags == pn_ia32_Sbb_flags);
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
}
}
- if (flags_proj == NULL) {
- res = new_bd_ia32_Neg(dbg, block, in2);
- arch_set_irn_register(res, in2_reg);
-
- /* add to schedule */
- sched_add_before(irn, res);
-
- /* generate the add */
- res = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, res, in1);
- arch_set_irn_register(res, out_reg);
- set_ia32_commutative(res);
-
- /* exchange the add and the sub */
- edges_reroute(irn, res, irg);
-
- /* add to schedule */
- sched_add_before(irn, res);
- } else {
- ir_node *stc, *cmc, *nnot, *adc;
- ir_node *adc_flags;
-
+ if (is_ia32_Sbb(irn)) {
+ /* Feed borrow (in CF) as carry (via CMC) into NOT+ADC. */
+ carry = get_irn_n(irn, n_ia32_Sbb_eflags);
+ carry = new_bd_ia32_Cmc(dbgi, block, carry);
+ goto carry;
+ } else if (flags_proj != 0) {
/*
* ARG, the above technique does NOT set the flags right.
* So, we must produce the following code:
* t2 = a + ~b + Carry
* Complement Carry
*
- * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
+ * a + -b = a + (~b + 1) would set the carry flag wrong IFF both a and b are zero.
*/
- nnot = new_bd_ia32_Not(dbg, block, in2);
+ ir_node *cmc;
+ ir_node *nnot;
+ ir_node *adc;
+ ir_node *adc_flags;
+
+ carry = new_bd_ia32_Stc(dbgi, block);
+
+carry:
+ nnot = new_bd_ia32_Not(dbgi, block, in2);
arch_set_irn_register(nnot, in2_reg);
sched_add_before(irn, nnot);
- stc = new_bd_ia32_Stc(dbg, block);
- arch_set_irn_register(stc, &ia32_registers[REG_EFLAGS]);
- sched_add_before(irn, stc);
+ arch_set_irn_register(carry, &ia32_registers[REG_EFLAGS]);
+ sched_add_before(irn, carry);
- adc = new_bd_ia32_Adc(dbg, block, noreg, noreg, nomem, nnot, in1, stc);
+ adc = new_bd_ia32_Adc(dbgi, block, noreg, noreg, nomem, nnot, in1, carry);
arch_set_irn_register(adc, out_reg);
sched_add_before(irn, adc);
adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
- cmc = new_bd_ia32_Cmc(dbg, block, adc_flags);
- arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
- sched_add_before(irn, cmc);
+ if (flags_proj != NULL) {
+ cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
+ arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
+ sched_add_before(irn, cmc);
+ exchange(flags_proj, cmc);
+ }
- exchange(flags_proj, cmc);
if (res_proj != NULL) {
set_Proj_pred(res_proj, adc);
set_Proj_proj(res_proj, pn_ia32_Adc_res);
}
res = adc;
+ } else {
+ res = new_bd_ia32_Neg(dbgi, block, in2);
+ arch_set_irn_register(res, in2_reg);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
+
+ /* generate the add */
+ res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, res, in1);
+ arch_set_irn_register(res, out_reg);
+ set_ia32_commutative(res);
+
+ /* exchange the add and the sub */
+ edges_reroute(irn, res);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
}
}
for (i = 0; i < n_res; i++) {
int i2, arity;
int same_pos;
- ir_node *perm;
- ir_node *in[2];
- ir_node *perm_proj0;
- ir_node *perm_proj1;
ir_node *uses_out_reg;
const arch_register_req_t *req = arch_get_out_register_req(node, i);
const arch_register_class_t *cls;
uses_out_reg_pos = -1;
for (i2 = 0; i2 < arity; ++i2) {
ir_node *in = get_irn_n(node, i2);
- const arch_register_t *in_reg;
+ const arch_register_t *other_in_reg;
if (!mode_is_data(get_irn_mode(in)))
continue;
- in_reg = arch_get_irn_register(in);
+ other_in_reg = arch_get_irn_register(in);
- if (in_reg != out_reg)
+ if (other_in_reg != out_reg)
continue;
if (uses_out_reg != NULL && in != uses_out_reg) {
continue;
}
-#ifdef DEBUG_libfirm
- ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
-#endif
- /* the out reg is used as node input: we need to permutate our input
- * and the other (this is allowed, since the other node can't be live
- * after! the operation as we will override the register. */
- in[0] = in_node;
- in[1] = uses_out_reg;
- perm = be_new_Perm(cls, block, 2, in);
-
- perm_proj0 = new_r_Proj(perm, get_irn_mode(in[0]), 0);
- perm_proj1 = new_r_Proj(perm, get_irn_mode(in[1]), 1);
-
- arch_set_irn_register(perm_proj0, out_reg);
- arch_set_irn_register(perm_proj1, in_reg);
-
- sched_add_before(node, perm);
-
- DBG((dbg, LEVEL_1,
- "created perm %+F for should be same argument at input %d of %+F (need permutate with %+F)\n",
- perm, same_pos, node, uses_out_reg));
-
- /* use the perm results */
- for (i2 = 0; i2 < arity; ++i2) {
- ir_node *in = get_irn_n(node, i2);
-
- if (in == in_node) {
- set_irn_n(node, i2, perm_proj0);
- } else if (in == uses_out_reg) {
- set_irn_n(node, i2, perm_proj1);
- }
- }
+ panic("Unresolved should_be_same constraint");
}
}
out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
continue;
- load_res = turn_back_am(irn);
+ load_res = ia32_turn_back_am(irn);
arch_set_irn_register(load_res, out_reg);
DBG((dbg, LEVEL_3,
next = sched_next(irn);
/* check if there is a sub which need to be transformed */
- if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
+ if (is_ia32_Sub(irn) || is_ia32_Sbb(irn) || is_ia32_xSub(irn)) {
ia32_transform_sub_to_neg_add(irn);
}
}
projects / libfirm / blobdiff