+/*
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
/**
- * This file implements functions to finalize the irg for emit.
- * @author Christian Wuerdig
- * $Id$
+ * @file
+ * @brief This file implements functions to finalize the irg for emit.
+ * @author Christian Wuerdig
+ * @version $Id$
*/
+#include "config.h"
#include "irnode.h"
#include "ircons.h"
#include "irgmod.h"
#include "irgwalk.h"
+#include "iredges.h"
+#include "irprintf.h"
#include "pdeq.h"
+#include "error.h"
#include "../bearch.h"
-#include "../besched_t.h"
-#include "../benode_t.h"
+#include "../besched.h"
+#include "../benode.h"
#include "bearch_ia32_t.h"
#include "ia32_finish.h"
#include "ia32_new_nodes.h"
-#include "ia32_map_regs.h"
+#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
#include "gen_ia32_regalloc_if.h"
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
+
/**
- * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
+ * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
* THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
*/
-static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
- ia32_transform_env_t tenv;
+static void ia32_transform_sub_to_neg_add(ir_node *irn)
+{
+ ir_graph *irg;
ir_node *in1, *in2, *noreg, *nomem, *res;
- const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
+ ir_node *noreg_fp, *block;
+ dbg_info *dbgi;
+ const arch_register_t *in1_reg, *in2_reg, *out_reg;
- /* Return if AM node or not a Sub or xSub */
- if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
+ /* fix_am will solve this for AddressMode variants */
+ if (get_ia32_op_type(irn) != ia32_Normal)
return;
- noreg = ia32_new_NoReg_gp(cg);
- nomem = new_rd_NoMem(cg->irg);
- in1 = get_irn_n(irn, 2);
- in2 = get_irn_n(irn, 3);
- in1_reg = arch_get_irn_register(cg->arch_env, in1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2);
- out_reg = get_ia32_out_reg(irn, 0);
-
- tenv.block = get_nodes_block(irn);
- tenv.dbg = get_irn_dbg_info(irn);
- tenv.irg = cg->irg;
- tenv.irn = irn;
- tenv.mode = get_ia32_res_mode(irn);
- tenv.cg = cg;
- DEBUG_ONLY(tenv.mod = cg->mod;)
+ irg = get_irn_irg(irn);
+ noreg = ia32_new_NoReg_gp(irg);
+ noreg_fp = ia32_new_NoReg_xmm(irg);
+ nomem = get_irg_no_mem(irg);
+ in1 = get_irn_n(irn, n_ia32_binary_left);
+ in2 = get_irn_n(irn, n_ia32_binary_right);
+ in1_reg = arch_get_irn_register(in1);
+ in2_reg = arch_get_irn_register(in2);
+ out_reg = arch_irn_get_register(irn, 0);
+
+ if (out_reg == in1_reg)
+ return;
/* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
- if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
- /* generate the neg src2 */
- res = gen_Minus_ex(&tenv, in2);
- arch_set_irn_register(cg->arch_env, res, in2_reg);
+ if (out_reg != in2_reg)
+ return;
- /* add to schedule */
- sched_add_before(irn, get_Proj_pred(res));
- sched_add_before(irn, res);
+ block = get_nodes_block(irn);
+ dbgi = get_irn_dbg_info(irn);
- /* generate the add */
- if (mode_is_float(tenv.mode)) {
- res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
- set_ia32_am_support(res, ia32_am_Source);
- }
- else {
- res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
- set_ia32_am_support(res, ia32_am_Full);
- set_ia32_commutative(res);
- }
- set_ia32_res_mode(res, tenv.mode);
+ /* generate the neg src2 */
+ if (is_ia32_xSub(irn)) {
+ int size;
+ ir_entity *entity;
+ ir_mode *op_mode = get_ia32_ls_mode(irn);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
- /* copy register */
- slots = get_ia32_slots(res);
- slots[0] = in2_reg;
+ assert(get_irn_mode(irn) != mode_T);
+
+ res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp);
+ size = get_mode_size_bits(op_mode);
+ entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
+ set_ia32_am_sc(res, entity);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ set_ia32_ls_mode(res, op_mode);
+
+ arch_set_irn_register(res, in2_reg);
/* add to schedule */
sched_add_before(irn, res);
- /* remove the old sub */
- sched_remove(irn);
-
- DBG_OPT_SUB2NEGADD(irn, res);
+ /* generate the add */
+ res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
/* exchange the add and the sub */
- exchange(irn, res);
- }
-}
+ edges_reroute(irn, res);
-/**
- * Transforms a LEA into an Add if possible
- * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
- */
-static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
- ia32_am_flavour_t am_flav;
- int imm = 0;
- ir_node *res = NULL;
- ir_node *nomem, *noreg, *base, *index, *op1, *op2;
- char *offs;
- ia32_transform_env_t tenv;
- const arch_register_t *out_reg, *base_reg, *index_reg;
-
- /* must be a LEA */
- if (! is_ia32_Lea(irn))
- return;
+ /* add to schedule */
+ sched_add_before(irn, res);
+ } else {
+ ir_node *res_proj = NULL;
+ ir_node *flags_proj = NULL;
+ ir_node *carry;
+ const ir_edge_t *edge;
+
+ if (get_irn_mode(irn) == mode_T) {
+ /* collect the Proj uses */
+ assert(pn_ia32_Sub_res == pn_ia32_Sbb_res);
+ assert(pn_ia32_Sub_flags == pn_ia32_Sbb_flags);
+ foreach_out_edge(irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ long pn = get_Proj_proj(proj);
+ if (pn == pn_ia32_Sub_res) {
+ assert(res_proj == NULL);
+ res_proj = proj;
+ } else {
+ assert(pn == pn_ia32_Sub_flags);
+ assert(flags_proj == NULL);
+ flags_proj = proj;
+ }
+ }
+ }
- am_flav = get_ia32_am_flavour(irn);
+ if (is_ia32_Sbb(irn)) {
+ /* Feed borrow (in CF) as carry (via CMC) into NOT+ADC. */
+ carry = get_irn_n(irn, n_ia32_Sbb_eflags);
+ carry = new_bd_ia32_Cmc(dbgi, block, carry);
+ goto carry;
+ } else if (flags_proj != 0) {
+ /*
+ * ARG, the above technique does NOT set the flags right.
+ * So, we must produce the following code:
+ * t1 = ~b
+ * t2 = a + ~b + Carry
+ * Complement Carry
+ *
+ * a + -b = a + (~b + 1) would set the carry flag wrong IFF both a and b are zero.
+ */
+ ir_node *cmc;
+ ir_node *nnot;
+ ir_node *adc;
+ ir_node *adc_flags;
+
+ carry = new_bd_ia32_Stc(dbgi, block);
+
+carry:
+ nnot = new_bd_ia32_Not(dbgi, block, in2);
+ arch_set_irn_register(nnot, in2_reg);
+ sched_add_before(irn, nnot);
+
+ arch_set_irn_register(carry, &ia32_registers[REG_EFLAGS]);
+ sched_add_before(irn, carry);
+
+ adc = new_bd_ia32_Adc(dbgi, block, noreg, noreg, nomem, nnot, in1, carry);
+ arch_set_irn_register(adc, out_reg);
+ sched_add_before(irn, adc);
+
+ set_irn_mode(adc, mode_T);
+ adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
+ arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
+
+ if (flags_proj != NULL) {
+ cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
+ arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
+ sched_add_before(irn, cmc);
+ exchange(flags_proj, cmc);
+ }
- if (get_ia32_am_sc(irn))
- return;
+ if (res_proj != NULL) {
+ set_Proj_pred(res_proj, adc);
+ set_Proj_proj(res_proj, pn_ia32_Adc_res);
+ }
- /* only some LEAs can be transformed to an Add */
- if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
- return;
+ res = adc;
+ } else {
+ res = new_bd_ia32_Neg(dbgi, block, in2);
+ arch_set_irn_register(res, in2_reg);
- noreg = ia32_new_NoReg_gp(cg);
- nomem = new_rd_NoMem(cg->irg);
- op1 = noreg;
- op2 = noreg;
- base = get_irn_n(irn, 0);
- index = get_irn_n(irn,1);
-
- offs = get_ia32_am_offs(irn);
-
- /* offset has a explicit sign -> we need to skip + */
- if (offs && offs[0] == '+')
- offs++;
-
- out_reg = arch_get_irn_register(cg->arch_env, irn);
- base_reg = arch_get_irn_register(cg->arch_env, base);
- index_reg = arch_get_irn_register(cg->arch_env, index);
-
- tenv.block = get_nodes_block(irn);
- tenv.dbg = get_irn_dbg_info(irn);
- tenv.irg = cg->irg;
- tenv.irn = irn;
- DEBUG_ONLY(tenv.mod = cg->mod;)
- tenv.mode = get_irn_mode(irn);
- tenv.cg = cg;
-
- switch(get_ia32_am_flavour(irn)) {
- case ia32_am_B:
- /* out register must be same as base register */
- if (! REGS_ARE_EQUAL(out_reg, base_reg))
- return;
-
- op1 = base;
- break;
- case ia32_am_OB:
- /* out register must be same as base register */
- if (! REGS_ARE_EQUAL(out_reg, base_reg))
- return;
-
- op1 = base;
- imm = 1;
- break;
- case ia32_am_OI:
- /* out register must be same as index register */
- if (! REGS_ARE_EQUAL(out_reg, index_reg))
- return;
-
- op1 = index;
- imm = 1;
- break;
- case ia32_am_BI:
- /* out register must be same as one in register */
- if (REGS_ARE_EQUAL(out_reg, base_reg)) {
- op1 = base;
- op2 = index;
- }
- else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
- op1 = index;
- op2 = base;
- }
- else {
- /* in registers a different from out -> no Add possible */
- return;
- }
- default:
- break;
- }
+ /* add to schedule */
+ sched_add_before(irn, res);
- res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
- arch_set_irn_register(cg->arch_env, res, out_reg);
- set_ia32_op_type(res, ia32_Normal);
- set_ia32_commutative(res);
- set_ia32_res_mode(res, tenv.mode);
+ /* generate the add */
+ res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, res, in1);
+ arch_set_irn_register(res, out_reg);
+ set_ia32_commutative(res);
+
+ /* exchange the add and the sub */
+ edges_reroute(irn, res);
- if (imm) {
- set_ia32_cnst(res, offs);
- set_ia32_immop_type(res, ia32_ImmConst);
+ /* add to schedule */
+ sched_add_before(irn, res);
+ }
}
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
+ set_irn_mode(res, get_irn_mode(irn));
- /* add Add to schedule */
- sched_add_before(irn, res);
+ SET_IA32_ORIG_NODE(res, irn);
- DBG_OPT_LEA2ADD(irn, res);
+ /* remove the old sub */
+ sched_remove(irn);
+ kill_node(irn);
- res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
+ DBG_OPT_SUB2NEGADD(irn, res);
+}
- /* add result Proj to schedule */
- sched_add_before(irn, res);
+static inline int need_constraint_copy(ir_node *irn)
+{
+ /* TODO this should be determined from the node specification */
+ switch (get_ia32_irn_opcode(irn)) {
+ case iro_ia32_IMul: {
+ /* the 3 operand form of IMul needs no constraint copy */
+ ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
+ return !is_ia32_Immediate(right);
+ }
- /* remove the old LEA */
- sched_remove(irn);
+ case iro_ia32_Lea:
+ case iro_ia32_Conv_I2I:
+ case iro_ia32_Conv_I2I8Bit:
+ case iro_ia32_CMovcc:
+ return 0;
- /* exchange the Add and the LEA */
- exchange(irn, res);
+ default:
+ return 1;
+ }
}
-static INLINE int need_constraint_copy(ir_node *irn) {
- return \
- ! is_ia32_Lea(irn) && \
- ! is_ia32_Conv_I2I(irn) && \
- ! is_ia32_Conv_I2I8Bit(irn) && \
- ! is_ia32_CmpCMov(irn) && \
- ! is_ia32_PsiCondCMov(irn) && \
- ! is_ia32_CmpSet(irn);
+/**
+ * Returns the index of the "same" register.
+ * On the x86, we should have only one.
+ */
+static int get_first_same(const arch_register_req_t* req)
+{
+ const unsigned other = req->other_same;
+ int i;
+
+ for (i = 0; i < 32; ++i) {
+ if (other & (1U << i)) return i;
+ }
+ panic("same position not found");
}
/**
* is not fulfilled.
* Transform Sub into Neg -- Add if IN2 == OUT
*/
-static void ia32_finish_node(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
- const ia32_register_req_t **reqs;
- const arch_register_t *out_reg, *in_reg, *in2_reg;
+static void assure_should_be_same_requirements(ir_node *node)
+{
+ const arch_register_t *out_reg, *in_reg;
int n_res, i;
- ir_node *copy, *in_node, *block, *in2_node;
- ia32_op_type_t op_tp;
-
- if (is_ia32_irn(irn)) {
- /* AM Dest nodes don't produce any values */
- op_tp = get_ia32_op_type(irn);
- if (op_tp == ia32_AddrModeD)
- goto end;
-
- reqs = get_ia32_out_req_all(irn);
- n_res = get_ia32_n_res(irn);
- block = get_nodes_block(irn);
-
- /* check all OUT requirements, if there is a should_be_same */
- if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
- {
- for (i = 0; i < n_res; i++) {
- if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
- /* get in and out register */
- out_reg = get_ia32_out_reg(irn, i);
- in_node = get_irn_n(irn, reqs[i]->same_pos);
- in_reg = arch_get_irn_register(cg->arch_env, in_node);
-
- /* don't copy ignore nodes */
- if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
- continue;
-
- /* check if in and out register are equal */
- if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
- /* in case of a commutative op: just exchange the in's */
- /* beware: the current op could be everything, so test for ia32 */
- /* commutativity first before getting the second in */
- if (is_ia32_commutative(irn)) {
- in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
-
- if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
- set_irn_n(irn, reqs[i]->same_pos, in2_node);
- set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
- }
- else
- goto insert_copy;
- }
- else {
-insert_copy:
- DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
- /* create copy from in register */
- copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
-
- DBG_OPT_2ADDRCPY(copy);
-
- /* destination is the out register */
- arch_set_irn_register(cg->arch_env, copy, out_reg);
-
- /* insert copy before the node into the schedule */
- sched_add_before(irn, copy);
-
- /* set copy as in */
- set_irn_n(irn, reqs[i]->same_pos, copy);
- }
- }
- }
+ ir_node *in_node, *block;
+
+ n_res = arch_irn_get_n_outs(node);
+ block = get_nodes_block(node);
+
+ /* check all OUT requirements, if there is a should_be_same */
+ for (i = 0; i < n_res; i++) {
+ int i2, arity;
+ int same_pos;
+ ir_node *uses_out_reg;
+ const arch_register_req_t *req = arch_get_out_register_req(node, i);
+ const arch_register_class_t *cls;
+ int uses_out_reg_pos;
+
+ if (!arch_register_req_is(req, should_be_same))
+ continue;
+
+ same_pos = get_first_same(req);
+
+ /* get in and out register */
+ out_reg = arch_irn_get_register(node, i);
+ in_node = get_irn_n(node, same_pos);
+ in_reg = arch_get_irn_register(in_node);
+
+ /* requirement already fulfilled? */
+ if (in_reg == out_reg)
+ continue;
+ cls = arch_register_get_class(in_reg);
+ assert(cls == arch_register_get_class(out_reg));
+
+ /* check if any other input operands uses the out register */
+ arity = get_irn_arity(node);
+ uses_out_reg = NULL;
+ uses_out_reg_pos = -1;
+ for (i2 = 0; i2 < arity; ++i2) {
+ ir_node *in = get_irn_n(node, i2);
+ const arch_register_t *other_in_reg;
+
+ if (!mode_is_data(get_irn_mode(in)))
+ continue;
+
+ other_in_reg = arch_get_irn_register(in);
+
+ if (other_in_reg != out_reg)
+ continue;
+
+ if (uses_out_reg != NULL && in != uses_out_reg) {
+ panic("invalid register allocation");
}
+ uses_out_reg = in;
+ if (uses_out_reg_pos >= 0)
+ uses_out_reg_pos = -1; /* multiple inputs... */
+ else
+ uses_out_reg_pos = i2;
}
- /* check xCmp: try to avoid unordered cmp */
- if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
- op_tp == ia32_Normal &&
- ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
- {
- long pnc = get_ia32_pncode(irn);
+ /* no-one else is using the out reg, we can simply copy it
+ * (the register can't be live since the operation will override it
+ * anyway) */
+ if (uses_out_reg == NULL) {
+ ir_node *copy = be_new_Copy(cls, block, in_node);
+ DBG_OPT_2ADDRCPY(copy);
- if (pnc & pn_Cmp_Uo) {
- ir_node *tmp;
- int idx1 = 2, idx2 = 3;
+ /* destination is the out register */
+ arch_set_irn_register(copy, out_reg);
- if (is_ia32_xCmpCMov(irn)) {
- idx1 = 0;
- idx2 = 1;
- }
+ /* insert copy before the node into the schedule */
+ sched_add_before(node, copy);
- tmp = get_irn_n(irn, idx1);
- set_irn_n(irn, idx1, get_irn_n(irn, idx2));
- set_irn_n(irn, idx2, tmp);
+ /* set copy as in */
+ set_irn_n(node, same_pos, copy);
- set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D));
- }
+ DBG((dbg, LEVEL_1,
+ "created copy %+F for should be same argument at input %d of %+F\n",
+ copy, same_pos, node));
+ continue;
}
- /*
- If we have a CondJmp/CmpSet/xCmpSet with immediate,
- we need to check if it's the right operand, otherwise
- we have to change it, as CMP doesn't support immediate
- as left operands.
- */
-#if 0
- if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
- (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
- op_tp == ia32_AddrModeS)
- {
- set_ia32_op_type(irn, ia32_AddrModeD);
- set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
+ /* for commutative nodes we can simply swap the left/right */
+ if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
+ ia32_swap_left_right(node);
+ DBG((dbg, LEVEL_1,
+ "swapped left/right input of %+F to resolve should be same constraint\n",
+ node));
+ continue;
}
-#endif
+
+ panic("Unresolved should_be_same constraint");
}
-end: ;
}
/**
* Following Problem:
* We have a source address mode node with base or index register equal to
- * result register. The constraint handler will insert a copy from the
- * remaining input operand to the result register -> base or index is
- * broken then.
+ * result register and unfulfilled should_be_same requirement. The constraint
+ * handler will insert a copy from the remaining input operand to the result
+ * register -> base or index is broken then.
* Solution: Turn back this address mode into explicit Load + Operation.
*/
-static void fix_am_source(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
- ir_node *base, *index, *noreg;
- const arch_register_t *reg_base, *reg_index;
- const ia32_register_req_t **reqs;
- int n_res, i;
+static void fix_am_source(ir_node *irn)
+{
+ int n_res, i;
/* check only ia32 nodes with source address mode */
- if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
+ if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
+ return;
+ /* only need to fix binary operations */
+ if (get_ia32_am_support(irn) != ia32_am_binary)
return;
- base = get_irn_n(irn, 0);
- index = get_irn_n(irn, 1);
-
- reg_base = arch_get_irn_register(cg->arch_env, base);
- reg_index = arch_get_irn_register(cg->arch_env, index);
- reqs = get_ia32_out_req_all(irn);
-
- noreg = ia32_new_NoReg_gp(cg);
-
- n_res = get_ia32_n_res(irn);
+ n_res = arch_irn_get_n_outs(irn);
for (i = 0; i < n_res; i++) {
- if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
- /* get in and out register */
- const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
-
- /*
- there is a constraint for the remaining operand
- and the result register is equal to base or index register
- */
- if (reqs[i]->same_pos == 2 &&
- (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
- {
- /* turn back address mode */
- ir_node *in_node = get_irn_n(irn, 2);
- const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
- ir_node *block = get_nodes_block(irn);
- ir_mode *ls_mode = get_ia32_ls_mode(irn);
- ir_node *load;
- int pnres;
-
- if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
- load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
- pnres = pn_ia32_Load_res;
- }
- else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
- load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
- pnres = pn_ia32_xLoad_res;
- }
- else {
- assert(0 && "cannot turn back address mode for this register class");
- }
-
- /* copy address mode information to load */
- set_ia32_ls_mode(load, ls_mode);
- set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
- set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_am_support(load, ia32_am_Source);
- set_ia32_am_scale(load, get_ia32_am_scale(irn));
- set_ia32_am_sc(load, get_ia32_am_sc(irn));
- add_ia32_am_offs(load, get_ia32_am_offs(irn));
- set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
-
- if (is_ia32_use_frame(irn))
- set_ia32_use_frame(load);
-
- /* insert the load into schedule */
- sched_add_before(irn, load);
-
- DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
-
- load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
- arch_set_irn_register(cg->arch_env, load, out_reg);
-
- /* insert the load result proj into schedule */
- sched_add_before(irn, load);
-
- /* set the new input operand */
- set_irn_n(irn, 3, load);
-
- /* this is a normal node now */
- set_irn_n(irn, 0, noreg);
- set_irn_n(irn, 1, noreg);
- set_ia32_op_type(irn, ia32_Normal);
-
- break;
- }
- }
+ const arch_register_req_t *req = arch_get_out_register_req(irn, i);
+ const arch_register_t *out_reg;
+ int same_pos;
+ ir_node *same_node;
+ const arch_register_t *same_reg;
+ ir_node *load_res;
+
+ if (!arch_register_req_is(req, should_be_same))
+ continue;
+
+ /* get in and out register */
+ out_reg = arch_irn_get_register(irn, i);
+ same_pos = get_first_same(req);
+ same_node = get_irn_n(irn, same_pos);
+ same_reg = arch_get_irn_register(same_node);
+
+ /* should_be same constraint is fullfilled, nothing to do */
+ if (out_reg == same_reg)
+ continue;
+
+ /* we only need to do something if the out reg is the same as base
+ or index register */
+ if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
+ out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
+ continue;
+
+ load_res = ia32_turn_back_am(irn);
+ arch_set_irn_register(load_res, out_reg);
+
+ DBG((dbg, LEVEL_3,
+ "irg %+F: build back AM source for node %+F, inserted load %+F\n",
+ get_irn_irg(irn), irn, get_Proj_pred(load_res)));
+ break;
}
}
-static void ia32_finish_irg_walker(ir_node *block, void *env) {
+/**
+ * Block walker: finishes a block
+ */
+static void ia32_finish_irg_walker(ir_node *block, void *env)
+{
ir_node *irn, *next;
+ (void) env;
/* first: turn back AM source if necessary */
for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
next = sched_next(irn);
- fix_am_source(irn, env);
+ fix_am_source(irn);
}
for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
- ia32_code_gen_t *cg = env;
-
next = sched_next(irn);
/* check if there is a sub which need to be transformed */
- ia32_transform_sub_to_neg_add(irn, cg);
-
- /* transform a LEA into an Add if possible */
- ia32_transform_lea_to_add(irn, cg);
+ if (is_ia32_Sub(irn) || is_ia32_Sbb(irn) || is_ia32_xSub(irn)) {
+ ia32_transform_sub_to_neg_add(irn);
+ }
}
/* second: insert copies and finish irg */
for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
next = sched_next(irn);
- ia32_finish_node(irn, env);
+ if (is_ia32_irn(irn)) {
+ /* some nodes are just a bit less efficient, but need no fixing if the
+ * should be same requirement is not fulfilled */
+ if (need_constraint_copy(irn))
+ assure_should_be_same_requirements(irn);
+ }
}
}
-static void ia32_push_on_queue_walker(ir_node *block, void *env) {
- waitq *wq = env;
+/**
+ * Block walker: pushes all blocks on a wait queue
+ */
+static void ia32_push_on_queue_walker(ir_node *block, void *env)
+{
+ waitq *wq = (waitq*)env;
waitq_put(wq, block);
}
/**
* Add Copy nodes for not fulfilled should_be_equal constraints
*/
-void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
+void ia32_finish_irg(ir_graph *irg)
+{
waitq *wq = new_waitq();
/* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
while (! waitq_empty(wq)) {
- ir_node *block = waitq_get(wq);
- ia32_finish_irg_walker(block, cg);
+ ir_node *block = (ir_node*)waitq_get(wq);
+ ia32_finish_irg_walker(block, NULL);
}
del_waitq(wq);
}
+
+void ia32_init_finish(void)
+{
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");
+}
projects / libfirm / blobdiff