#include "ia32_finish.h"
#include "ia32_new_nodes.h"
#include "ia32_map_regs.h"
+#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
const arch_register_t *in1_reg, *in2_reg, *out_reg;
/* fix_am will solve this for AddressMode variants */
- if(get_ia32_op_type(irn) != ia32_Normal)
+ if (get_ia32_op_type(irn) != ia32_Normal)
return;
noreg = ia32_new_NoReg_gp(cg);
dbg = get_irn_dbg_info(irn);
/* generate the neg src2 */
- if(is_ia32_xSub(irn)) {
+ if (is_ia32_xSub(irn)) {
int size;
ir_entity *entity;
ir_mode *op_mode = get_ia32_ls_mode(irn);
ir_node *flags_proj = NULL;
const ir_edge_t *edge;
- if(get_irn_mode(irn) == mode_T) {
+ if (get_irn_mode(irn) == mode_T) {
/* collect the Proj uses */
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
* t2 = a + ~b + Carry
* Complement Carry
*
- * a + -b = a + (~b + 1) would sat the carry flag IF a == b ...
+ * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
*/
not = new_rd_ia32_Not(dbg, irg, block, in2);
arch_set_irn_register(cg->arch_env, not, in2_reg);
stc = new_rd_ia32_Stc(dbg, irg, block);
arch_set_irn_register(cg->arch_env, stc,
&ia32_flags_regs[REG_EFLAGS]);
+ sched_add_before(irn, stc);
adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not,
in1, stc);
arch_set_irn_register(cg->arch_env, adc, out_reg);
sched_add_before(irn, adc);
+ set_irn_mode(adc, mode_T);
adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags);
+ arch_set_irn_register(cg->arch_env, adc_flags,
+ &ia32_flags_regs[REG_EFLAGS]);
cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags);
+ arch_set_irn_register(cg->arch_env, cmc,
+ &ia32_flags_regs[REG_EFLAGS]);
sched_add_before(irn, cmc);
exchange(flags_proj, cmc);
- if(res_proj != NULL) {
+ if (res_proj != NULL) {
set_Proj_pred(res_proj, adc);
set_Proj_proj(res_proj, pn_ia32_Adc_res);
}
/* remove the old sub */
sched_remove(irn);
- be_kill_node(irn);
+ kill_node(irn);
DBG_OPT_SUB2NEGADD(irn, res);
}
-static INLINE int need_constraint_copy(ir_node *irn) {
- /* the 3 operand form of IMul needs no constraint copy */
- if(is_ia32_IMul(irn)) {
- ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
- if(is_ia32_Immediate(right))
+static INLINE int need_constraint_copy(ir_node *irn)
+{
+ /* TODO this should be determined from the node specification */
+ switch (get_ia32_irn_opcode(irn)) {
+ case iro_ia32_IMul: {
+ /* the 3 operand form of IMul needs no constraint copy */
+ ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
+ return !is_ia32_Immediate(right);
+ }
+
+ case iro_ia32_Lea:
+ case iro_ia32_Conv_I2I:
+ case iro_ia32_Conv_I2I8Bit:
+ case iro_ia32_CMov:
return 0;
- }
- return ! is_ia32_Lea(irn) &&
- ! is_ia32_Conv_I2I(irn) &&
- ! is_ia32_Conv_I2I8Bit(irn) &&
- ! is_ia32_CMov(irn);
+ default:
+ return 1;
+ }
}
/**
ir_node *perm_proj1;
ir_node *uses_out_reg;
const arch_register_req_t *req = reqs[i];
- const arch_register_class_t *class;
+ const arch_register_class_t *cls;
int uses_out_reg_pos;
if (!arch_register_req_is(req, should_be_same))
/* unknowns can be changed to any register we want on emitting */
if (is_unknown_reg(in_reg))
continue;
- class = arch_register_get_class(in_reg);
- assert(class == arch_register_get_class(out_reg));
+ cls = arch_register_get_class(in_reg);
+ assert(cls == arch_register_get_class(out_reg));
/* check if any other input operands uses the out register */
arity = get_irn_arity(node);
* (the register can't be live since the operation will override it
* anyway) */
if(uses_out_reg == NULL) {
- ir_node *copy = be_new_Copy(class, irg, block, in_node);
+ ir_node *copy = be_new_Copy(cls, irg, block, in_node);
DBG_OPT_2ADDRCPY(copy);
/* destination is the out register */
* after! the operation as we will override the register. */
in[0] = in_node;
in[1] = uses_out_reg;
- perm = be_new_Perm(class, irg, block, 2, in);
+ perm = be_new_Perm(cls, irg, block, 2, in);
perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
* register -> base or index is broken then.
* Solution: Turn back this address mode into explicit Load + Operation.
*/
-static void fix_am_source(ir_node *irn, void *env) {
+static void fix_am_source(ir_node *irn, void *env)
+{
ia32_code_gen_t *cg = env;
const arch_env_t *arch_env = cg->arch_env;
ir_node *base;
if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
return;
/* only need to fix binary operations */
- if (get_ia32_am_arity(irn) != ia32_am_binary)
+ if (get_ia32_am_support(irn) != ia32_am_binary)
return;
- base = get_irn_n(irn, 0);
- index = get_irn_n(irn, 1);
+ base = get_irn_n(irn, n_ia32_base);
+ index = get_irn_n(irn, n_ia32_index);
reg_base = arch_get_irn_register(arch_env, base);
reg_index = arch_get_irn_register(arch_env, index);
/* copy address mode information to load */
set_ia32_op_type(load, ia32_AddrModeS);
ia32_copy_am_attrs(load, irn);
+ if (is_ia32_is_reload(irn))
+ set_ia32_is_reload(load);
/* insert the load into schedule */
sched_add_before(irn, load);
arch_set_irn_register(cg->arch_env, load_res, out_reg);
/* set the new input operand */
- set_irn_n(irn, n_ia32_binary_right, load_res);
- if(get_irn_mode(irn) == mode_T) {
+ if (is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right)))
+ set_irn_n(irn, n_ia32_binary_left, load_res);
+ else
+ set_irn_n(irn, n_ia32_binary_right, load_res);
+ if (get_irn_mode(irn) == mode_T) {
const ir_edge_t *edge, *next;
foreach_out_edge_safe(irn, edge, next) {
ir_node *node = get_edge_src_irn(edge);
int pn = get_Proj_proj(node);
- if(pn == 0) {
+ if (pn == pn_ia32_res) {
exchange(node, irn);
- } else if(pn == pn_ia32_mem) {
+ } else if (pn == pn_ia32_mem) {
set_Proj_pred(node, load);
set_Proj_proj(node, pnmem);
+ } else {
+ panic("Unexpected Proj");
}
}
set_irn_mode(irn, mode_Iu);
projects / libfirm / blobdiff