make transformations before checking 2 addresscode constraints

[libfirm] / ir / be / ia32 / ia32_finish.c

diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c
index 2e3c6c7..0a39293 100644 (file)
--- a/ir/be/ia32/ia32_finish.c
+++ b/ir/be/ia32/ia32_finish.c
@@ -59,6 +59,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
                arch_set_irn_register(cg->arch_env, res, in2_reg);
 
                /* add to schedule */
+               sched_add_before(irn, get_Proj_pred(res));
                sched_add_before(irn, res);
 
                /* generate the add */
@@ -309,17 +310,8 @@ insert_copy:
                        set_ia32_op_type(irn, ia32_AddrModeD);
                        set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
                }
-
-               /* check if there is a sub which need to be transformed */
-               ia32_transform_sub_to_neg_add(irn, cg);
-
-               /* transform a LEA into an Add if possible */
-               ia32_transform_lea_to_add(irn, cg);
        }
-end:
-
-       /* check for peephole optimization */
-       ia32_peephole_optimization(irn, cg);
+end: ;
 }
 
 /**
@@ -398,7 +390,7 @@ static void fix_am_source(ir_node *irn, void *env) {
                                /* insert the load into schedule */
                                sched_add_before(irn, load);
 
-                               ir_printf("irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load);
+                               DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
 
                                load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
                                arch_set_irn_register(cg->arch_env, load, out_reg);
@@ -427,6 +419,22 @@ static void ia32_finish_irg_walker(ir_node *block, void *env) {
                fix_am_source(irn, env);
        }
 
+       for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
+               ia32_code_gen_t *cg = env;
+               next = sched_next(irn);
+
+               if (is_ia32_irn(irn)) {
+                       /* check if there is a sub which need to be transformed */
+                       ia32_transform_sub_to_neg_add(irn, cg);
+
+                       /* transform a LEA into an Add if possible */
+                       ia32_transform_lea_to_add(irn, cg);
+
+                       /* check for peephole optimization */
+                       ia32_peephole_optimization(irn, cg);
+               }
+       }
+
        /* second: insert copies and finish irg */
        for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
                next = sched_next(irn);