#include "../besched_t.h"
#include "../benode_t.h"
+#include "../beabi.h"
+#include "../be_dbgout.h"
#include "ia32_emitter.h"
#include "gen_ia32_emitter.h"
ir_mode *mode = get_irn_mode(n);
tarval *tv = get_ia32_Immop_tarval(n);
- /* beware: in some rare cases mode is mode_b which has no tarval_null() */
- if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
- const char *instr = "xor";
- if (env->isa->opt_arch == arch_pentium_4) {
- /* P4 prefers sub r, r, others xor r, r */
- instr = "sub";
- }
- lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
- }
- else {
- if (get_ia32_op_type(n) == ia32_SymConst) {
- lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
- }
- else {
+ if (get_ia32_op_type(n) == ia32_SymConst) {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
+ } else {
+ assert(mode == get_tarval_mode(tv));
+ /* beware: in some rare cases mode is mode_b which has no tarval_null() */
+ if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
+ const char *instr = "xor";
+ if (env->isa->opt_arch == arch_pentium_4) {
+ /* P4 prefers sub r, r, others xor r, r */
+ instr = "sub";
+ }
+ lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
+ } else {
lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
}
#undef IA32_EMIT
}
+static const char *last_name = NULL;
+static unsigned last_line = -1;
+static unsigned num = -1;
+
+/**
+ * Emit the debug support for node irn.
+ */
+static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
+ dbg_info *db = get_irn_dbg_info(irn);
+ unsigned lineno;
+ const char *fname = be_retrieve_dbg_info(db, &lineno);
+
+ if (fname) {
+ if (last_name != fname) {
+ last_line = -1;
+ be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
+ last_name = fname;
+ }
+ if (last_line != lineno) {
+ char name[64];
+ FILE *F = env->out;
+
+ snprintf(name, sizeof(name), ".LM%u", ++num);
+ last_line = lineno;
+ be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
+ fprintf(F, "%s:\n", name);
+ }
+ }
+}
+
/**
* Emits code for a node.
*/
if (op->ops.generic) {
void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
+ ia32_emit_dbg(irn, emit_env);
(*emit)(irn, env);
}
else {
}
/* emit the contents of the block */
+ ia32_emit_dbg(block, env);
sched_foreach(block, irn) {
ia32_emit_node(irn, env);
}
/**
* Emits code for function start.
*/
-static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
+static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
entity *irg_ent = get_irg_entity(irg);
const char *irg_name = get_entity_ld_name(irg_ent);
+ cpu_support cpu = emit_env->isa->opt_arch;
+ const be_irg_t *birg = emit_env->cg->birg;
fprintf(F, "\n");
ia32_switch_section(F, SECTION_TEXT);
+ be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
ia32_emit_align_func(F, cpu);
if (get_entity_visibility(irg_ent) == visibility_external_visible) {
fprintf(F, ".globl %s\n", irg_name);
/**
* Emits code for function end
*/
-static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
+static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
+ const be_irg_t *birg = emit_env->cg->birg;
ia32_dump_function_size(F, irg_name);
+ be_dbg_method_end(birg->main_env->db_handle);
fprintf(F, "\n");
}
ia32_register_emitters();
- ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
+ ia32_emit_func_prolog(F, irg, &emit_env);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
}
- ia32_emit_func_epilog(F, irg);
+ ia32_emit_func_epilog(F, irg, &emit_env);
}