#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
#include "ia32_map_regs.h"
+#include "bearch_ia32_t.h"
#define BLOCK_PREFIX(x) ".L" x
/* global arch_env for lc_printf functions */
static const arch_env_t *arch_env = NULL;
+/** by default, we generate assembler code for the Linux gas */
+asm_flavour_t asm_flavour = ASM_LINUX_GAS;
+
+/**
+ * Switch to a new section
+ */
+void ia32_switch_section(FILE *F, section_t sec) {
+ static section_t curr_sec = NO_SECTION;
+ static const char *text[ASM_MAX][SECTION_MAX] = {
+ {
+ ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
+ },
+ {
+ ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
+ }
+ };
+
+ if (curr_sec == sec)
+ return;
+
+ curr_sec = sec;
+ switch (sec) {
+
+ case NO_SECTION:
+ break;
+
+ case SECTION_TEXT:
+ case SECTION_DATA:
+ case SECTION_RODATA:
+ case SECTION_COMMON:
+ fprintf(F, "\t%s\n", text[asm_flavour][sec]);
+ }
+}
+
+static void ia32_dump_function_object(FILE *F, const char *name)
+{
+ switch (asm_flavour) {
+ case ASM_LINUX_GAS:
+ fprintf(F, "\t.type\t%s, @function\n", name);
+ break;
+ case ASM_MINGW_GAS:
+ fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
+ break;
+ }
+}
+
+static void ia32_dump_function_size(FILE *F, const char *name)
+{
+ switch (asm_flavour) {
+ case ASM_LINUX_GAS:
+ fprintf(F, "\t.size\t%s, .-%s\n", name, name);
+ break;
+ }
+}
+
/*************************************************************
* _ _ __ _ _
* (_) | | / _| | | | |
reg = arch_get_irn_register(arch_env, op);
assert(reg && "no in register found");
+
+ /* in case of unknown: just return a register */
+ if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
+ reg = &ia32_gp_regs[REG_EAX];
+ else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
+ reg = &ia32_xmm_regs[REG_XMM0];
+ else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
+ reg = &ia32_vfp_regs[REG_VF0];
+ else if (REGS_ARE_EQUAL(reg, &ia32_st_regs[REG_ST_UKNWN]))
+ reg = &ia32_st_regs[REG_ST0];
+
return reg;
}
(!(is_ia32_St(n) || \
is_ia32_Store8Bit(n) || \
is_ia32_CondJmp(n) || \
- is_ia32_fCondJmp(n) || \
+ is_ia32_xCondJmp(n) || \
is_ia32_SwitchJmp(n)))
if (! buf) {
snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
}
else {
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
+ if (PRODUCES_RESULT(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
+ }
+ else {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
+ }
}
break;
case ia32_AddrModeD:
lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
}
break;
- case ia32_am_Dest:
- snprintf(buf, SNPRINTF_BUF_LEN, ia32_emit_am(n, env));
+ case ia32_AddrModeD:
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
break;
default:
assert(0 && "unsupported op type");
finish_CondJmp(F, irn, get_ia32_res_mode(irn));
}
+/**
+ * Emits code for conditional x87 floating point jump with two variables.
+ */
+static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ ia32_attr_t *attr = get_ia32_attr(irn);
+ const char *reg = attr->x87[1]->name;
+ const char *instr = "fcom";
+ int reverse = 0;
+
+ switch (get_ia32_pncode(irn)) {
+ case iro_ia32_fcomrJmp:
+ reverse = 1;
+ case iro_ia32_fcomJmp:
+ default:
+ instr = "fucom";
+ break;
+ case iro_ia32_fcomrpJmp:
+ reverse = 1;
+ case iro_ia32_fcompJmp:
+ instr = "fucomp";
+ break;
+ case iro_ia32_fcomrppJmp:
+ reverse = 1;
+ case iro_ia32_fcomppJmp:
+ instr = "fucompp";
+ reg = "";
+ break;
+ }
+
+ if (reverse)
+ set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s", instr, reg);
+ lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+ IA32_DO_EMIT(irn);
+// lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %3D", irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
+ IA32_DO_EMIT(irn);
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
+ IA32_DO_EMIT(irn);
+
+ finish_CondJmp(F, irn, mode_Is);
+}
+
/*********************************************************
* _ _ _
* (_) | (_)
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
IA32_DO_EMIT(irn);
- fprintf(F, "\t.section\t.rodata\n");
+ ia32_switch_section(F, SECTION_RODATA);
fprintf(F, "\t.align 4\n");
fprintf(F, "%s:\n", tbl.label);
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
IA32_DO_EMIT(irn);
}
-
- fprintf(F, "\n\t.text\n\n");
+ ia32_switch_section(F, SECTION_TEXT);
}
else {
/* one jump is enough */
* Emit rep movsd instruction for memcopy.
*/
static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
- tarval *tv = get_ia32_Immop_tarval(irn);
- int rem = get_tarval_long(tv);
- int size = get_tarval_long(get_ia32_Immop_tarval(get_irn_n(irn, 2)));
+ FILE *F = emit_env->out;
+ tarval *tv = get_ia32_Immop_tarval(irn);
+ int rem = get_tarval_long(tv);
+ ir_node *size_node = get_irn_n(irn, 2);
+ int size;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+ /* beware: size_node could be a be_Copy to fulfill constraints for ecx */
+ size_node = be_is_Copy(size_node) ? be_get_Copy_op(size_node) : size_node;
+ size = get_tarval_long(get_ia32_Immop_tarval(size_node));
+
emit_CopyB_prolog(F, rem, size);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
IA32_DO_EMIT(irn);
}
+/**
+ * Emits code for Constant loading.
+ */
+static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[256], cmnt_buf[256];
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+
+ if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
+ const char *instr = "xor";
+ if (env->isa->opt_arch == arch_pentium_4) {
+ /* P4 prefers sub r, r, others xor r, r */
+ instr = "sub";
+ }
+ lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
+ }
+ else {
+ if (get_ia32_op_type(n) == ia32_SymConst) {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
+ }
+ else {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
+ }
+ }
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
+}
+
/***********************************************************************************
*/
static void ia32_register_emitters(void) {
-#define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
-#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
-#define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
+#define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
+#define IA32_EMIT(a) IA32_EMIT2(a,a)
+#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
+#define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
/* first clear the generic function pointer for all ops */
clear_irp_opcodes_generic_func();
IA32_EMIT(Conv_FP2FP);
IA32_EMIT(Conv_I2I);
IA32_EMIT(Conv_I2I8Bit);
+ IA32_EMIT(Const);
+ IA32_EMIT2(fcomJmp, x87CondJmp);
+ IA32_EMIT2(fcompJmp, x87CondJmp);
+ IA32_EMIT2(fcomppJmp, x87CondJmp);
+ IA32_EMIT2(fcomrJmp, x87CondJmp);
+ IA32_EMIT2(fcomrpJmp, x87CondJmp);
+ IA32_EMIT2(fcomrppJmp, x87CondJmp);
/* benode emitter */
BE_EMIT(Call);
EMIT(Jmp);
EMIT(Proj);
-#undef IA32_EMIT
#undef BE_EMIT
#undef EMIT
+#undef IA32_EMIT2
+#undef IA32_EMIT
}
/**
}
}
+/**
+ * Emits gas alignment directives for Functions dependend on cpu architecture.
+ */
+static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
+ /* gcc doesn't emit alignment for p4 ?*/
+ if (cpu == arch_pentium_4)
+ return;
+
+ fprintf(F, "\t.p2align ");
+
+ switch (cpu) {
+ case arch_i386:
+ /* align 4 bytes, maximum skip 3 bytes */
+ fprintf(F, "2,,3");
+ break;
+ case arch_i486:
+ /* align 16 bytes, maximum skip 15 bytes */
+ fprintf(F, "4,,15");
+ break;
+ case arch_k6:
+ /* align 32 bytes, maximum skip 31 bytes */
+ fprintf(F, "5,,31");
+ break;
+ default:
+ /* align 16 bytes, maximum skip 15 bytes */
+ fprintf(F, "4,,15");
+ }
+
+ fprintf(F, "\n");
+}
+
+/**
+ * Emits gas alignment directives for Labels dependend on cpu architecture.
+ */
+static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
+ /* gcc doesn't emit alignment for p4 ?*/
+ if (cpu == arch_pentium_4)
+ return;
+
+ fprintf(F, "\t.p2align ");
+
+ switch (cpu) {
+ case arch_i386:
+ /* align 4 bytes, maximum skip 3 bytes */
+ fprintf(F, "2,,3");
+ break;
+ case arch_i486:
+ /* align 16 bytes, maximum skip 15 bytes */
+ fprintf(F, "4,,15");
+ break;
+ case arch_k6:
+ /* align 32 bytes, maximum skip 7 bytes */
+ fprintf(F, "5,,7");
+ break;
+ default:
+ /* align 16 bytes, maximum skip 7 bytes */
+ fprintf(F, "4,,7");
+ }
+
+ fprintf(F, "\n");
+}
+
/**
* Walks over the nodes in a block connected by scheduling edges
* and emits code for each node.
*/
static void ia32_gen_block(ir_node *block, void *env) {
+ ia32_emit_env_t *emit_env = env;
const ir_node *irn;
+ int need_label = block != get_irg_start_block(get_irn_irg(block));
if (! is_Block(block))
return;
- fprintf(((ia32_emit_env_t *)env)->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
+ if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
+ /* if the extended block scheduler is used, only leader blocks need
+ labels. */
+ need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
+ }
+
+ if (need_label) {
+ ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
+ fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
+ }
+
sched_foreach(block, irn) {
ia32_emit_node(irn, env);
}
/**
* Emits code for function start.
*/
-static void ia32_emit_func_prolog(FILE *F, ir_graph *irg) {
+static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
entity *irg_ent = get_irg_entity(irg);
- const char *irg_name = get_entity_name(irg_ent);
+ const char *irg_name = get_entity_ld_name(irg_ent);
- fprintf(F, "\t.section\t.text\n");
+ fprintf(F, "\n");
+ ia32_switch_section(F, SECTION_TEXT);
+ ia32_emit_align_func(F, cpu);
if (get_entity_visibility(irg_ent) == visibility_external_visible) {
fprintf(F, ".globl %s\n", irg_name);
}
- fprintf(F, "\t.type\t%s, @function\n", irg_name);
+ ia32_dump_function_object(F, irg_name);
fprintf(F, "%s:\n", irg_name);
}
* Emits code for function end
*/
static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
- const char *irg_name = get_entity_name(get_irg_entity(irg));
+ const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
fprintf(F, "\tret\n");
- fprintf(F, "\t.size\t%s, .-%s\n\n", irg_name, irg_name);
+ ia32_dump_function_size(F, irg_name);
+ fprintf(F, "\n");
}
/**
ia32_register_emitters();
- ia32_emit_func_prolog(F, irg);
+ ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
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