static int do_pic;
static char pic_base_label[128];
static ir_label_t exc_label_id;
+static int mark_spill_reload = 0;
+
+/** Return the next block in Block schedule */
+static ir_node *get_prev_block_sched(const ir_node *block)
+{
+ return get_irn_link(block);
+}
+
+static int is_fallthrough(const ir_node *cfgpred)
+{
+ ir_node *pred;
+
+ if (!is_Proj(cfgpred))
+ return 1;
+ pred = get_Proj_pred(cfgpred);
+ if (is_ia32_SwitchJmp(pred))
+ return 0;
+
+ return 1;
+}
+
+static int block_needs_label(const ir_node *block)
+{
+ int need_label = 1;
+ int n_cfgpreds = get_Block_n_cfgpreds(block);
+
+ if (n_cfgpreds == 0) {
+ need_label = 0;
+ } else if (n_cfgpreds == 1) {
+ ir_node *cfgpred = get_Block_cfgpred(block, 0);
+ ir_node *cfgpred_block = get_nodes_block(cfgpred);
+
+ if (get_prev_block_sched(block) == cfgpred_block
+ && is_fallthrough(cfgpred)) {
+ need_label = 0;
+ }
+ }
+
+ return need_label;
+}
/**
* Returns the register at in position pos.
in register we need. */
op = get_irn_n(irn, pos);
- reg = arch_get_irn_register(arch_env, op);
+ reg = arch_get_irn_register(op);
assert(reg && "no in register found");
- if(reg == &ia32_gp_regs[REG_GP_NOREG])
+ if (reg == &ia32_gp_regs[REG_GP_NOREG])
panic("trying to emit noreg for %+F input %d", irn, pos);
/* in case of unknown register: just return a valid register */
if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
- const arch_register_req_t *req;
-
- /* ask for the requirements */
- req = arch_get_register_req(arch_env, irn, pos);
+ const arch_register_req_t *req = arch_get_register_req(irn, pos);
if (arch_register_req_is(req, limited)) {
/* in case of limited requirements: get the first allowed register */
if (get_irn_mode(irn) != mode_T) {
assert(pos == 0);
- reg = arch_get_irn_register(arch_env, irn);
+ reg = arch_get_irn_register(irn);
} else if (is_ia32_irn(irn)) {
reg = get_ia32_out_reg(irn, pos);
} else {
proj = get_edge_src_irn(edge);
assert(is_Proj(proj) && "non-Proj from mode_T node");
if (get_Proj_proj(proj) == pos) {
- reg = arch_get_irn_register(arch_env, proj);
+ reg = arch_get_irn_register(proj);
break;
}
}
{
const char *reg_name;
- if(mode != NULL) {
+ if (mode != NULL) {
int size = get_mode_size_bits(mode);
- if(size == 8) {
- emit_8bit_register(reg);
- return;
- } else if(size == 16) {
- emit_16bit_register(reg);
- return;
- } else {
- assert(mode_is_float(mode) || size == 32);
+ switch (size) {
+ case 8: emit_8bit_register(reg); return;
+ case 16: emit_16bit_register(reg); return;
}
+ assert(mode_is_float(mode) || size == 32);
}
reg_name = arch_register_get_name(reg);
void ia32_emit_source_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_in_reg(node, pos);
+ const arch_register_t *reg = get_in_reg(node, pos);
emit_register(reg, NULL);
}
-static void emit_ia32_Immediate(const ir_node *node);
+static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
+{
+ ident *id;
+
+ set_entity_backend_marked(entity, 1);
+ id = get_entity_ld_ident(entity);
+ be_emit_ident(id);
+
+ if (get_entity_owner(entity) == get_tls_type()) {
+ if (get_entity_visibility(entity) == visibility_external_allocated) {
+ be_emit_cstring("@INDNTPOFF");
+ } else {
+ be_emit_cstring("@NTPOFF");
+ }
+ }
+
+ if (!no_pic_adjust && do_pic) {
+ /* TODO: only do this when necessary */
+ be_emit_char('-');
+ be_emit_string(pic_base_label);
+ }
+}
+
+static void emit_ia32_Immediate_no_prefix(const ir_node *node)
+{
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
+
+ if (attr->symconst != NULL) {
+ if (attr->sc_sign)
+ be_emit_char('-');
+ ia32_emit_entity(attr->symconst, 0);
+ }
+ if (attr->symconst == NULL || attr->offset != 0) {
+ if (attr->symconst != NULL) {
+ be_emit_irprintf("%+d", attr->offset);
+ } else {
+ be_emit_irprintf("0x%X", attr->offset);
+ }
+ }
+}
+
+static void emit_ia32_Immediate(const ir_node *node)
+{
+ be_emit_char('$');
+ emit_ia32_Immediate_no_prefix(node);
+}
void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
{
const arch_register_t *reg;
ir_node *in = get_irn_n(node, pos);
- if(is_ia32_Immediate(in)) {
+ if (is_ia32_Immediate(in)) {
emit_ia32_Immediate(in);
return;
}
static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
{
- if(mode_is_float(mode)) {
- switch(get_mode_size_bits(mode)) {
- case 32: be_emit_char('s'); return;
- case 64: be_emit_char('l'); return;
- case 80:
- case 96: be_emit_char('t'); return;
- }
- } else {
- assert(mode_is_int(mode) || mode_is_reference(mode));
- switch(get_mode_size_bits(mode)) {
+ assert(mode_is_int(mode) || mode_is_reference(mode));
+ switch (get_mode_size_bits(mode)) {
+ case 8: be_emit_char('b'); return;
+ case 16: be_emit_char('w'); return;
+ case 32: be_emit_char('l'); return;
+ /* gas docu says q is the suffix but gcc, objdump and icc use ll
+ * apparently */
case 64: be_emit_cstring("ll"); return;
- /* gas docu says q is the suffix but gcc, objdump and icc use
- ll apparently */
- case 32: be_emit_char('l'); return;
- case 16: be_emit_char('w'); return;
- case 8: be_emit_char('b'); return;
- }
}
- panic("Can't output mode_suffix for %+F\n", mode);
+ panic("Can't output mode_suffix for %+F", mode);
}
void ia32_emit_mode_suffix(const ir_node *node)
{
ir_mode *mode = get_ia32_ls_mode(node);
- if(mode == NULL)
+ if (mode == NULL)
mode = mode_Iu;
ia32_emit_mode_suffix_mode(mode);
void ia32_emit_x87_mode_suffix(const ir_node *node)
{
+ ir_mode *mode;
+
/* we only need to emit the mode on address mode */
- if(get_ia32_op_type(node) != ia32_Normal) {
- ir_mode *mode = get_ia32_ls_mode(node);
- assert(mode != NULL);
- ia32_emit_mode_suffix_mode(mode);
+ if (get_ia32_op_type(node) == ia32_Normal)
+ return;
+
+ mode = get_ia32_ls_mode(node);
+ assert(mode != NULL);
+
+ if (mode_is_float(mode)) {
+ switch (get_mode_size_bits(mode)) {
+ case 32: be_emit_char('s'); return;
+ case 64: be_emit_char('l'); return;
+ case 80:
+ case 96: be_emit_char('t'); return;
+ }
+ } else {
+ assert(mode_is_int(mode));
+ switch (get_mode_size_bits(mode)) {
+ case 16: be_emit_char('s'); return;
+ case 32: be_emit_char('l'); return;
+ /* gas docu says q is the suffix but gcc, objdump and icc use ll
+ * apparently */
+ case 64: be_emit_cstring("ll"); return;
+ }
}
+ panic("Can't output mode_suffix for %+F", mode);
}
static char get_xmm_mode_suffix(ir_mode *mode)
{
assert(mode_is_float(mode));
switch(get_mode_size_bits(mode)) {
- case 32:
- return 's';
- case 64:
- return 'd';
- default:
- assert(0);
+ case 32: return 's';
+ case 64: return 'd';
+ default: panic("Invalid XMM mode");
}
- return '%';
}
void ia32_emit_xmm_mode_suffix(const ir_node *node)
void ia32_emit_extend_suffix(const ir_mode *mode)
{
- if(get_mode_size_bits(mode) == 32)
+ if (get_mode_size_bits(mode) == 32)
return;
- if(mode_is_signed(mode)) {
- be_emit_char('s');
- } else {
- be_emit_char('z');
- }
+ be_emit_char(mode_is_signed(mode) ? 's' : 'z');
}
void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
{
ir_node *in = get_irn_n(node, pos);
- if(is_ia32_Immediate(in)) {
+ if (is_ia32_Immediate(in)) {
emit_ia32_Immediate(in);
} else {
const ir_mode *mode = get_ia32_ls_mode(node);
}
/**
- * Emits registers and/or address mode of a binary operation.
+ * Returns the target block for a control flow node.
*/
-void ia32_emit_binop(const ir_node *node) {
- const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
- const ir_mode *mode = get_ia32_ls_mode(node);
- const arch_register_t *reg_left;
+static ir_node *get_cfop_target_block(const ir_node *irn)
+{
+ assert(get_irn_mode(irn) == mode_X);
+ return get_irn_link(irn);
+}
- switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- reg_left = get_in_reg(node, n_ia32_binary_left);
- if(is_ia32_Immediate(right_op)) {
- emit_ia32_Immediate(right_op);
- be_emit_cstring(", ");
- emit_register(reg_left, mode);
+/**
+ * Emits a block label for the given block.
+ */
+static void ia32_emit_block_name(const ir_node *block)
+{
+ if (has_Block_label(block)) {
+ be_emit_string(be_gas_block_label_prefix());
+ be_emit_irprintf("%lu", get_Block_label(block));
+ } else {
+ be_emit_cstring(BLOCK_PREFIX);
+ be_emit_irprintf("%ld", get_irn_node_nr(block));
+ }
+}
+
+/**
+ * Emits the target label for a control flow node.
+ */
+static void ia32_emit_cfop_target(const ir_node *node)
+{
+ ir_node *block = get_cfop_target_block(node);
+ ia32_emit_block_name(block);
+}
+
+/*
+ * coding of conditions
+ */
+struct cmp2conditon_t {
+ const char *name;
+ int num;
+};
+
+/*
+ * positive conditions for signed compares
+ */
+static const struct cmp2conditon_t cmp2condition_s[] = {
+ { NULL, pn_Cmp_False }, /* always false */
+ { "e", pn_Cmp_Eq }, /* == */
+ { "l", pn_Cmp_Lt }, /* < */
+ { "le", pn_Cmp_Le }, /* <= */
+ { "g", pn_Cmp_Gt }, /* > */
+ { "ge", pn_Cmp_Ge }, /* >= */
+ { "ne", pn_Cmp_Lg }, /* != */
+ { NULL, pn_Cmp_Leg}, /* always true */
+};
+
+/*
+ * positive conditions for unsigned compares
+ */
+static const struct cmp2conditon_t cmp2condition_u[] = {
+ { NULL, pn_Cmp_False }, /* always false */
+ { "e", pn_Cmp_Eq }, /* == */
+ { "b", pn_Cmp_Lt }, /* < */
+ { "be", pn_Cmp_Le }, /* <= */
+ { "a", pn_Cmp_Gt }, /* > */
+ { "ae", pn_Cmp_Ge }, /* >= */
+ { "ne", pn_Cmp_Lg }, /* != */
+ { NULL, pn_Cmp_Leg }, /* always true */
+};
+
+static void ia32_emit_cmp_suffix(int pnc)
+{
+ const char *str;
+
+ if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
+ pnc = pnc & 7;
+ assert(cmp2condition_u[pnc].num == pnc);
+ str = cmp2condition_u[pnc].name;
+ } else {
+ pnc = pnc & 7;
+ assert(cmp2condition_s[pnc].num == pnc);
+ str = cmp2condition_s[pnc].name;
+ }
+
+ be_emit_string(str);
+}
+
+typedef enum ia32_emit_mod_t {
+ EMIT_RESPECT_LS = 1U << 0,
+ EMIT_ALTERNATE_AM = 1U << 1
+} ia32_emit_mod_t;
+
+/**
+ * fmt parameter output
+ * ---- ---------------------- ---------------------------------------------
+ * %% %
+ * %AM <node> address mode of the node
+ * %AR const arch_register_t* address mode of the node or register
+ * %ASx <node> address mode of the node or source register x
+ * %Dx <node> destination register x
+ * %I <node> immediate of the node
+ * %L <node> control flow target of the node
+ * %M <node> mode suffix of the node
+ * %P int condition code
+ * %R const arch_register_t* register
+ * %Sx <node> source register x
+ * %s const char* string
+ * %u unsigned int unsigned int
+ *
+ * x starts at 0
+ * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
+ * * modifier does not prefix immediates with $, but AM with *
+ */
+static void ia32_emitf(const ir_node *node, const char *fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+
+ for (;;) {
+ const char *start = fmt;
+ ia32_emit_mod_t mod = 0;
+
+ while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
+ ++fmt;
+ if (fmt != start) {
+ be_emit_string_len(start, fmt - start);
+ }
+
+ if (*fmt == '\n') {
+ be_emit_finish_line_gas(node);
+ ++fmt;
+ if (*fmt == '\0')
+ break;
+ continue;
+ }
+
+ if (*fmt == '\0')
break;
- } else {
- const arch_register_t *reg_right
- = get_in_reg(node, n_ia32_binary_right);
- emit_register(reg_right, mode);
- be_emit_cstring(", ");
- emit_register(reg_left, mode);
+
+ ++fmt;
+ if (*fmt == '*') {
+ mod |= EMIT_ALTERNATE_AM;
+ ++fmt;
}
- break;
- case ia32_AddrModeS:
- if(is_ia32_Immediate(right_op)) {
- emit_ia32_Immediate(right_op);
- be_emit_cstring(", ");
- ia32_emit_am(node);
- } else {
- reg_left = get_in_reg(node, n_ia32_binary_left);
- ia32_emit_am(node);
- be_emit_cstring(", ");
- emit_register(reg_left, mode);
+
+ if (*fmt == '#') {
+ mod |= EMIT_RESPECT_LS;
+ ++fmt;
+ }
+
+ switch (*fmt++) {
+ case '%':
+ be_emit_char('%');
+ break;
+
+ case 'A': {
+ switch (*fmt++) {
+ case 'M':
+ if (mod & EMIT_ALTERNATE_AM)
+ be_emit_char('*');
+ ia32_emit_am(node);
+ break;
+
+ case 'R': {
+ const arch_register_t *reg = va_arg(ap, const arch_register_t*);
+ if (mod & EMIT_ALTERNATE_AM)
+ be_emit_char('*');
+ if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ ia32_emit_am(node);
+ } else {
+ emit_register(reg, NULL);
+ }
+ break;
+ }
+
+ case 'S':
+ if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ if (mod & EMIT_ALTERNATE_AM)
+ be_emit_char('*');
+ ia32_emit_am(node);
+ ++fmt;
+ } else {
+ assert(get_ia32_op_type(node) == ia32_Normal);
+ goto emit_S;
+ }
+ break;
+
+ default: goto unknown;
+ }
+ break;
+ }
+
+ case 'D': {
+ unsigned pos;
+ const arch_register_t *reg;
+
+ if (*fmt < '0' || '9' <= *fmt)
+ goto unknown;
+
+ pos = *fmt++ - '0';
+ reg = get_out_reg(node, pos);
+ emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
+ break;
+ }
+
+ case 'I':
+ if (!(mod & EMIT_ALTERNATE_AM))
+ be_emit_char('$');
+ emit_ia32_Immediate_no_prefix(node);
+ break;
+
+ case 'L':
+ ia32_emit_cfop_target(node);
+ break;
+
+ case 'M': {
+ ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
+ break;
+ }
+
+ case 'P': {
+ int pnc = va_arg(ap, int);
+ ia32_emit_cmp_suffix(pnc);
+ break;
+ }
+
+ case 'R': {
+ const arch_register_t *reg = va_arg(ap, const arch_register_t*);
+ emit_register(reg, NULL);
+ break;
+ }
+
+emit_S:
+ case 'S': {
+ unsigned pos;
+ const ir_node *in;
+
+ if (*fmt < '0' || '9' <= *fmt)
+ goto unknown;
+
+ pos = *fmt++ - '0';
+ in = get_irn_n(node, pos);
+ if (is_ia32_Immediate(in)) {
+ if (!(mod & EMIT_ALTERNATE_AM))
+ be_emit_char('$');
+ emit_ia32_Immediate_no_prefix(in);
+ } else {
+ if (mod & EMIT_ALTERNATE_AM)
+ be_emit_char('*');
+ const arch_register_t *reg = get_in_reg(node, pos);
+ emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
+ }
+ break;
+ }
+
+ case 's': {
+ const char *str = va_arg(ap, const char*);
+ be_emit_string(str);
+ break;
+ }
+
+ case 'u': {
+ unsigned num = va_arg(ap, unsigned);
+ be_emit_irprintf("%u", num);
+ break;
+ }
+
+ default:
+unknown:
+ panic("unknown conversion");
}
- break;
- case ia32_AddrModeD:
- panic("DestMode can't be output by %%binop anymore");
- break;
- default:
- assert(0 && "unsupported op type");
}
+
+ va_end(ap);
}
/**
* Emits registers and/or address mode of a binary operation.
*/
-void ia32_emit_x87_binop(const ir_node *node) {
+void ia32_emit_binop(const ir_node *node)
+{
+ if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
+ ia32_emitf(node, "%#S4, %#AS3");
+ } else {
+ ia32_emitf(node, "%#AS4, %#S3");
+ }
+}
+
+/**
+ * Emits registers and/or address mode of a binary operation.
+ */
+void ia32_emit_x87_binop(const ir_node *node)
+{
switch(get_ia32_op_type(node)) {
case ia32_Normal:
{
const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
const arch_register_t *in1 = x87_attr->x87[0];
- const arch_register_t *in2 = x87_attr->x87[1];
+ const arch_register_t *in = x87_attr->x87[1];
const arch_register_t *out = x87_attr->x87[2];
- const arch_register_t *in;
- in = out ? ((out == in2) ? in1 : in2) : in2;
- out = out ? out : in1;
+ if (out == NULL) {
+ out = in1;
+ } else if (out == in) {
+ in = in1;
+ }
be_emit_char('%');
be_emit_string(arch_register_get_name(in));
/**
* Emits registers and/or address mode of a unary operation.
*/
-void ia32_emit_unop(const ir_node *node, int pos) {
- const ir_node *op;
-
- switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- op = get_irn_n(node, pos);
- if (is_ia32_Immediate(op)) {
- emit_ia32_Immediate(op);
- } else {
- ia32_emit_source_register(node, pos);
- }
- break;
- case ia32_AddrModeS:
- case ia32_AddrModeD:
- ia32_emit_am(node);
- break;
- default:
- assert(0 && "unsupported op type");
- }
-}
-
-static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
+void ia32_emit_unop(const ir_node *node, int pos)
{
- ident *id;
-
- set_entity_backend_marked(entity, 1);
- id = get_entity_ld_ident(entity);
- be_emit_ident(id);
-
- if (get_entity_owner(entity) == get_tls_type()) {
- if (get_entity_visibility(entity) == visibility_external_allocated) {
- be_emit_cstring("@INDNTPOFF");
- } else {
- be_emit_cstring("@NTPOFF");
- }
- }
-
- if (!no_pic_adjust && do_pic) {
- /* TODO: only do this when necessary */
- be_emit_char('-');
- be_emit_string(pic_base_label);
- }
+ char fmt[] = "%ASx";
+ fmt[3] = '0' + pos;
+ ia32_emitf(node, fmt);
}
/**
* Emits address mode.
*/
-void ia32_emit_am(const ir_node *node) {
+void ia32_emit_am(const ir_node *node)
+{
ir_entity *ent = get_ia32_am_sc(node);
int offs = get_ia32_am_offs_int(node);
- ir_node *base = get_irn_n(node, 0);
+ ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, 1);
+ ir_node *index = get_irn_n(node, n_ia32_index);
int has_index = !is_ia32_NoReg_GP(index);
/* just to be sure... */
ia32_emit_entity(ent, 0);
}
- if(offs != 0) {
- if(ent != NULL) {
+ /* also handle special case if nothing is set */
+ if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
+ if (ent != NULL) {
be_emit_irprintf("%+d", offs);
} else {
be_emit_irprintf("%d", offs);
scale = get_ia32_am_scale(node);
if (scale > 0) {
- be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
+ be_emit_irprintf(",%d", 1 << scale);
}
}
be_emit_char(')');
- }
-
- /* special case if nothing is set */
- if(ent == NULL && offs == 0 && !has_base && !has_index) {
- be_emit_char('0');
- }
-}
-
-static void emit_ia32_IMul(const ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_IMul_left);
- const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
-
- be_emit_cstring("\timul");
- ia32_emit_mode_suffix(node);
- be_emit_char(' ');
-
- ia32_emit_binop(node);
-
- /* do we need the 3-address form? */
- if(is_ia32_NoReg_GP(left) ||
- get_in_reg(node, n_ia32_IMul_left) != out_reg) {
- be_emit_cstring(", ");
- emit_register(out_reg, get_ia32_ls_mode(node));
- }
- be_emit_finish_line_gas(node);
-}
-
-/*************************************************
- * _ _ _
- * (_) | | |
- * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
- * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
- * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
- * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
- *
- *************************************************/
-
-#undef IA32_DO_EMIT
-#define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
-
-/*
- * coding of conditions
- */
-struct cmp2conditon_t {
- const char *name;
- int num;
-};
+ }
+}
-/*
- * positive conditions for signed compares
- */
-static const struct cmp2conditon_t cmp2condition_s[] = {
- { NULL, pn_Cmp_False }, /* always false */
- { "e", pn_Cmp_Eq }, /* == */
- { "l", pn_Cmp_Lt }, /* < */
- { "le", pn_Cmp_Le }, /* <= */
- { "g", pn_Cmp_Gt }, /* > */
- { "ge", pn_Cmp_Ge }, /* >= */
- { "ne", pn_Cmp_Lg }, /* != */
- { NULL, pn_Cmp_Leg}, /* always true */
-};
+static void emit_ia32_IMul(const ir_node *node)
+{
+ ir_node *left = get_irn_n(node, n_ia32_IMul_left);
+ const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
-/*
- * positive conditions for unsigned compares
- */
-static const struct cmp2conditon_t cmp2condition_u[] = {
- { NULL, pn_Cmp_False }, /* always false */
- { "e", pn_Cmp_Eq }, /* == */
- { "b", pn_Cmp_Lt }, /* < */
- { "be", pn_Cmp_Le }, /* <= */
- { "a", pn_Cmp_Gt }, /* > */
- { "ae", pn_Cmp_Ge }, /* >= */
- { "ne", pn_Cmp_Lg }, /* != */
- { NULL, pn_Cmp_Leg }, /* always true */
-};
+ /* do we need the 3-address form? */
+ if (is_ia32_NoReg_GP(left) ||
+ get_in_reg(node, n_ia32_IMul_left) != out_reg) {
+ ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
+ } else {
+ ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
+ }
+}
/**
* walks up a tree of copies/perms/spills/reloads to find the original value
*/
static ir_node *find_original_value(ir_node *node)
{
- inc_irg_visited(current_ir_graph);
- while(1) {
- mark_irn_visited(node);
- if(be_is_Copy(node)) {
- node = be_get_Copy_op(node);
- } else if(be_is_CopyKeep(node)) {
- node = be_get_CopyKeep_op(node);
- } else if(is_Proj(node)) {
- ir_node *pred = get_Proj_pred(node);
- if(be_is_Perm(pred)) {
- node = get_irn_n(pred, get_Proj_proj(node));
- } else if(be_is_MemPerm(pred)) {
- node = get_irn_n(pred, get_Proj_proj(node) + 1);
- } else if(is_ia32_Load(pred)) {
- node = get_irn_n(pred, n_ia32_Load_mem);
- } else {
- return node;
- }
- } else if(is_ia32_Store(node)) {
- node = get_irn_n(node, n_ia32_Store_val);
- } else if(is_Phi(node)) {
- int i, arity;
- arity = get_irn_arity(node);
- for(i = 0; i < arity; ++i) {
- ir_node *in = get_irn_n(node, i);
- if(irn_visited(in))
- continue;
- node = in;
- break;
- }
- assert(i < arity);
+ if (irn_visited(node))
+ return NULL;
+
+ mark_irn_visited(node);
+ if (be_is_Copy(node)) {
+ return find_original_value(be_get_Copy_op(node));
+ } else if (be_is_CopyKeep(node)) {
+ return find_original_value(be_get_CopyKeep_op(node));
+ } else if (is_Proj(node)) {
+ ir_node *pred = get_Proj_pred(node);
+ if (be_is_Perm(pred)) {
+ return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
+ } else if (be_is_MemPerm(pred)) {
+ return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
+ } else if (is_ia32_Load(pred)) {
+ return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
} else {
return node;
}
+ } else if (is_ia32_Store(node)) {
+ return find_original_value(get_irn_n(node, n_ia32_Store_val));
+ } else if (is_Phi(node)) {
+ int i, arity;
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ ir_node *res = find_original_value(in);
+
+ if (res != NULL)
+ return res;
+ }
+ return NULL;
+ } else {
+ return node;
}
}
const ia32_attr_t *flags_attr;
flags = skip_Proj(flags);
- if(is_ia32_Sahf(flags)) {
+ if (is_ia32_Sahf(flags)) {
ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
- if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
+ if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
|| is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
+ inc_irg_visited(current_ir_graph);
cmp = find_original_value(cmp);
+ assert(cmp != NULL);
assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
|| is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
}
flags_attr = get_ia32_attr_const(cmp);
- if(flags_attr->data.ins_permuted)
+ if (flags_attr->data.ins_permuted)
pnc = get_mirrored_pnc(pnc);
pnc |= ia32_pn_Cmp_float;
- } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
+ } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
|| is_ia32_Fucompi(flags)) {
flags_attr = get_ia32_attr_const(flags);
- if(flags_attr->data.ins_permuted)
+ if (flags_attr->data.ins_permuted)
pnc = get_mirrored_pnc(pnc);
pnc |= ia32_pn_Cmp_float;
} else {
-#if 0
- assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
- || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
-#endif
flags_attr = get_ia32_attr_const(flags);
- if(flags_attr->data.ins_permuted)
+ if (flags_attr->data.ins_permuted)
pnc = get_mirrored_pnc(pnc);
- if(flags_attr->data.cmp_unsigned)
+ if (flags_attr->data.cmp_unsigned)
pnc |= ia32_pn_Cmp_unsigned;
}
return pnc;
}
-static void ia32_emit_cmp_suffix(int pnc)
-{
- const char *str;
-
- if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
- pnc = pnc & 7;
- assert(cmp2condition_u[pnc].num == pnc);
- str = cmp2condition_u[pnc].name;
- } else {
- pnc = pnc & 7;
- assert(cmp2condition_s[pnc].num == pnc);
- str = cmp2condition_s[pnc].name;
- }
-
- be_emit_string(str);
-}
-
void ia32_emit_cmp_suffix_node(const ir_node *node,
int flags_pos)
{
pn_Cmp pnc = get_ia32_condcode(node);
pnc = determine_final_pnc(node, flags_pos, pnc);
- if(attr->data.ins_permuted) {
- if(pnc & ia32_pn_Cmp_float) {
+ if (attr->data.ins_permuted) {
+ if (pnc & ia32_pn_Cmp_float) {
pnc = get_negated_pnc(pnc, mode_F);
} else {
pnc = get_negated_pnc(pnc, mode_Iu);
ia32_emit_cmp_suffix(pnc);
}
-/**
- * Returns the target block for a control flow node.
- */
-static ir_node *get_cfop_target_block(const ir_node *irn) {
- return get_irn_link(irn);
-}
-
-/**
- * Emits a block label for the given block.
- */
-static void ia32_emit_block_name(const ir_node *block)
-{
- if (has_Block_label(block)) {
- be_emit_string(be_gas_block_label_prefix());
- be_emit_irprintf("%lu", get_Block_label(block));
- } else {
- be_emit_cstring(BLOCK_PREFIX);
- be_emit_irprintf("%ld", get_irn_node_nr(block));
- }
-}
-
/**
* Emits an exception label for a given node.
*/
be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
}
-/**
- * Emits the target label for a control flow node.
- */
-static void ia32_emit_cfop_target(const ir_node *node)
-{
- ir_node *block = get_cfop_target_block(node);
-
- ia32_emit_block_name(block);
-}
-
-/** Return the next block in Block schedule */
-static ir_node *next_blk_sched(const ir_node *block)
-{
- return get_irn_link(block);
-}
-
/**
* Returns the Proj with projection number proj and NOT mode_M
*/
-static ir_node *get_proj(const ir_node *node, long proj) {
+static ir_node *get_proj(const ir_node *node, long proj)
+{
const ir_edge_t *edge;
ir_node *src;
return NULL;
}
+static int can_be_fallthrough(const ir_node *node)
+{
+ ir_node *target_block = get_cfop_target_block(node);
+ ir_node *block = get_nodes_block(node);
+ return get_prev_block_sched(target_block) == block;
+}
+
/**
* Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
*/
const ir_node *proj_true;
const ir_node *proj_false;
const ir_node *block;
- const ir_node *next_block;
pn_Cmp pnc = get_ia32_condcode(node);
pnc = determine_final_pnc(node, 0, pnc);
assert(proj_false && "Jcc without false Proj");
block = get_nodes_block(node);
- next_block = next_blk_sched(block);
- if (get_cfop_target_block(proj_true) == next_block) {
+ if (can_be_fallthrough(proj_true)) {
/* exchange both proj's so the second one can be omitted */
const ir_node *t = proj_true;
proj_true = proj_false;
proj_false = t;
- if(pnc & ia32_pn_Cmp_float) {
+ if (pnc & ia32_pn_Cmp_float) {
pnc = get_negated_pnc(pnc, mode_F);
} else {
pnc = get_negated_pnc(pnc, mode_Iu);
* which indicates that the result is unordered */
switch (pnc & 15) {
case pn_Cmp_Uo: {
- be_emit_cstring("\tjp ");
- ia32_emit_cfop_target(proj_true);
- be_emit_finish_line_gas(proj_true);
+ ia32_emitf(proj_true, "\tjp %L\n");
break;
}
case pn_Cmp_Leg:
- be_emit_cstring("\tjnp ");
- ia32_emit_cfop_target(proj_true);
- be_emit_finish_line_gas(proj_true);
+ ia32_emitf(proj_true, "\tjnp %L\n");
break;
case pn_Cmp_Eq:
case pn_Cmp_Le:
/* we need a local label if the false proj is a fallthrough
* as the falseblock might have no label emitted then */
- if (get_cfop_target_block(proj_false) == next_block) {
+ if (can_be_fallthrough(proj_false)) {
need_parity_label = 1;
- be_emit_cstring("\tjp 1f");
+ ia32_emitf(proj_false, "\tjp 1f\n");
} else {
- be_emit_cstring("\tjp ");
- ia32_emit_cfop_target(proj_false);
+ ia32_emitf(proj_false, "\tjp %L\n");
}
- be_emit_finish_line_gas(proj_false);
goto emit_jcc;
case pn_Cmp_Ug:
case pn_Cmp_Uge:
case pn_Cmp_Ne:
- be_emit_cstring("\tjp ");
- ia32_emit_cfop_target(proj_true);
- be_emit_finish_line_gas(proj_true);
+ ia32_emitf(proj_true, "\tjp %L\n");
goto emit_jcc;
default:
}
} else {
emit_jcc:
- be_emit_cstring("\tj");
- ia32_emit_cmp_suffix(pnc);
- be_emit_char(' ');
- ia32_emit_cfop_target(proj_true);
- be_emit_finish_line_gas(proj_true);
+ ia32_emitf(proj_true, "\tj%P %L\n", pnc);
}
- if(need_parity_label) {
- be_emit_cstring("1:");
- be_emit_write_line();
+ if (need_parity_label) {
+ ia32_emitf(NULL, "1:\n");
}
/* the second Proj might be a fallthrough */
- if (get_cfop_target_block(proj_false) != next_block) {
- be_emit_cstring("\tjmp ");
- ia32_emit_cfop_target(proj_false);
- be_emit_finish_line_gas(proj_false);
+ if (can_be_fallthrough(proj_false)) {
+ ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
} else {
- be_emit_cstring("\t/* fallthrough to ");
- ia32_emit_cfop_target(proj_false);
- be_emit_cstring(" */");
- be_emit_finish_line_gas(proj_false);
+ ia32_emitf(proj_false, "\tjmp %L\n");
}
}
{
const ia32_attr_t *attr = get_ia32_attr_const(node);
int ins_permuted = attr->data.ins_permuted;
- const arch_register_t *out = arch_get_irn_register(arch_env, node);
+ const arch_register_t *out = arch_get_irn_register(node);
pn_Cmp pnc = get_ia32_condcode(node);
const arch_register_t *in_true;
const arch_register_t *in_false;
pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
- in_true = arch_get_irn_register(arch_env,
- get_irn_n(node, n_ia32_CMov_val_true));
- in_false = arch_get_irn_register(arch_env,
- get_irn_n(node, n_ia32_CMov_val_false));
+ in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
+ in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
/* should be same constraint fullfilled? */
- if(out == in_false) {
+ if (out == in_false) {
/* yes -> nothing to do */
- } else if(out == in_true) {
+ } else if (out == in_true) {
const arch_register_t *tmp;
assert(get_ia32_op_type(node) == ia32_Normal);
in_false = tmp;
} else {
/* we need a mov */
- be_emit_cstring("\tmovl ");
- emit_register(in_false, NULL);
- be_emit_cstring(", ");
- emit_register(out, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
}
- if(ins_permuted) {
- if(pnc & ia32_pn_Cmp_float) {
+ if (ins_permuted) {
+ if (pnc & ia32_pn_Cmp_float) {
pnc = get_negated_pnc(pnc, mode_F);
} else {
pnc = get_negated_pnc(pnc, mode_Iu);
/* TODO: handling of Nans isn't correct yet */
- be_emit_cstring("\tcmov");
- ia32_emit_cmp_suffix(pnc);
- be_emit_char(' ');
- if(get_ia32_op_type(node) == ia32_AddrModeS) {
- ia32_emit_am(node);
- } else {
- emit_register(in_true, get_ia32_ls_mode(node));
- }
- be_emit_cstring(", ");
- emit_register(out, get_ia32_ls_mode(node));
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tcmov%P %AR, %#R\n", pnc, in_true, out);
}
/*********************************************************
/**
* Compare two variables of type branch_t. Used to sort all switch cases
*/
-static int ia32_cmp_branch_t(const void *a, const void *b) {
+static int ia32_cmp_branch_t(const void *a, const void *b)
+{
branch_t *b1 = (branch_t *)a;
branch_t *b2 = (branch_t *)b;
const ir_edge_t *edge;
/* fill the table structure */
- tbl.label = xmalloc(SNPRINTF_BUF_LEN);
+ tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
tbl.defProj = NULL;
tbl.num_branches = get_irn_n_edges(node) - 1;
- tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
+ tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
tbl.min_value = INT_MAX;
tbl.max_value = INT_MIN;
interval = tbl.max_value - tbl.min_value;
/* emit the table */
- be_emit_cstring("\tcmpl $");
- be_emit_irprintf("%u, ", interval);
- ia32_emit_source_register(node, 0);
- be_emit_finish_line_gas(node);
-
- be_emit_cstring("\tja ");
- ia32_emit_cfop_target(tbl.defProj);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
+ ia32_emitf(tbl.defProj, "\tja %L\n");
if (tbl.num_branches > 1) {
/* create table */
- be_emit_cstring("\tjmp *");
- be_emit_string(tbl.label);
- be_emit_cstring("(,");
- ia32_emit_source_register(node, 0);
- be_emit_cstring(",4)");
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
be_gas_emit_switch_section(GAS_SECTION_RODATA);
- be_emit_cstring("\t.align 4\n");
- be_emit_write_line();
-
- be_emit_string(tbl.label);
- be_emit_cstring(":\n");
- be_emit_write_line();
-
- be_emit_cstring(".long ");
- ia32_emit_cfop_target(tbl.branches[0].target);
- be_emit_finish_line_gas(NULL);
+ ia32_emitf(NULL, "\t.align 4\n");
+ ia32_emitf(NULL, "%s:\n", tbl.label);
last_value = tbl.branches[0].value;
- for (i = 1; i < tbl.num_branches; ++i) {
- while (++last_value < tbl.branches[i].value) {
- be_emit_cstring(".long ");
- ia32_emit_cfop_target(tbl.defProj);
- be_emit_finish_line_gas(NULL);
+ for (i = 0; i != tbl.num_branches; ++i) {
+ while (last_value != tbl.branches[i].value) {
+ ia32_emitf(tbl.defProj, ".long %L\n");
+ ++last_value;
}
- be_emit_cstring(".long ");
- ia32_emit_cfop_target(tbl.branches[i].target);
- be_emit_finish_line_gas(NULL);
+ ia32_emitf(tbl.branches[i].target, ".long %L\n");
+ ++last_value;
}
be_gas_emit_switch_section(GAS_SECTION_TEXT);
} else {
/* one jump is enough */
- be_emit_cstring("\tjmp ");
- ia32_emit_cfop_target(tbl.branches[0].target);
- be_emit_finish_line_gas(node);
+ ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
}
if (tbl.label)
*/
static void emit_Jmp(const ir_node *node)
{
- ir_node *block, *next_block;
+ ir_node *block;
/* for now, the code works for scheduled and non-schedules blocks */
block = get_nodes_block(node);
/* we have a block schedule */
- next_block = next_blk_sched(block);
- if (get_cfop_target_block(node) != next_block) {
- be_emit_cstring("\tjmp ");
- ia32_emit_cfop_target(node);
+ if (can_be_fallthrough(node)) {
+ ia32_emitf(node, "\t/* fallthrough to %L */\n");
} else {
- be_emit_cstring("\t/* fallthrough to ");
- ia32_emit_cfop_target(node);
- be_emit_cstring(" */");
- }
- be_emit_finish_line_gas(node);
-}
-
-static void emit_ia32_Immediate(const ir_node *node)
-{
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
-
- be_emit_char('$');
- if(attr->symconst != NULL) {
- if(attr->sc_sign)
- be_emit_char('-');
- ia32_emit_entity(attr->symconst, 0);
- }
- if(attr->symconst == NULL || attr->offset != 0) {
- if(attr->symconst != NULL) {
- be_emit_irprintf("%+d", attr->offset);
- } else {
- be_emit_irprintf("0x%X", attr->offset);
- }
+ ia32_emitf(node, "\tjmp %L\n");
}
}
/* parse number */
sscanf(s, "%d%n", &num, &p);
- if(num < 0) {
+ if (num < 0) {
ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
node);
return s;
s += p;
}
- if(num < 0 || num >= ARR_LEN(asm_regs)) {
+ if (num < 0 || num >= ARR_LEN(asm_regs)) {
ir_fprintf(stderr, "Error: Custom assembler references invalid "
"input/output (%+F)\n", node);
return s;
assert(asm_reg->valid);
/* get register */
- if(asm_reg->use_input == 0) {
+ if (asm_reg->use_input == 0) {
reg = get_out_reg(node, asm_reg->inout_pos);
} else {
ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
/* might be an immediate value */
- if(is_ia32_Immediate(pred)) {
+ if (is_ia32_Immediate(pred)) {
emit_ia32_Immediate(pred);
return s;
}
reg = get_in_reg(node, asm_reg->inout_pos);
}
- if(reg == NULL) {
+ if (reg == NULL) {
ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
"(%+F)\n", num, node);
return s;
}
- if(asm_reg->memory) {
+ if (asm_reg->memory) {
be_emit_char('(');
}
/* emit it */
- if(modifier != 0) {
+ if (modifier != 0) {
be_emit_char('%');
switch(modifier) {
case 'b':
emit_register(reg, asm_reg->mode);
}
- if(asm_reg->memory) {
+ if (asm_reg->memory) {
be_emit_char(')');
}
ident *asm_text = attr->asm_text;
const char *s = get_id_str(asm_text);
- be_emit_cstring("# Begin ASM \t");
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "#APP\t\n");
if (s[0] != '\t')
be_emit_char('\t');
while(*s != 0) {
- if(*s == '%') {
+ if (*s == '%') {
s = emit_asm_operand(node, s);
- continue;
} else {
- be_emit_char(*s);
+ be_emit_char(*s++);
}
- ++s;
}
- be_emit_char('\n');
- be_emit_write_line();
-
- be_emit_cstring("# End ASM\n");
- be_emit_write_line();
+ ia32_emitf(NULL, "\n#NO_APP\n");
}
/**********************************
/**
* Emit movsb/w instructions to make mov count divideable by 4
*/
-static void emit_CopyB_prolog(unsigned size) {
- be_emit_cstring("\tcld");
- be_emit_finish_line_gas(NULL);
-
- switch (size) {
- case 1:
- be_emit_cstring("\tmovsb");
- be_emit_finish_line_gas(NULL);
- break;
- case 2:
- be_emit_cstring("\tmovsw");
- be_emit_finish_line_gas(NULL);
- break;
- case 3:
- be_emit_cstring("\tmovsb");
- be_emit_finish_line_gas(NULL);
- be_emit_cstring("\tmovsw");
- be_emit_finish_line_gas(NULL);
- break;
- }
+static void emit_CopyB_prolog(unsigned size)
+{
+ if (size & 1)
+ ia32_emitf(NULL, "\tmovsb\n");
+ if (size & 2)
+ ia32_emitf(NULL, "\tmovsw\n");
}
/**
unsigned size = get_ia32_copyb_size(node);
emit_CopyB_prolog(size);
-
- be_emit_cstring("\trep movsd");
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\trep movsd\n");
}
/**
{
unsigned size = get_ia32_copyb_size(node);
- emit_CopyB_prolog(size & 0x3);
+ emit_CopyB_prolog(size);
size >>= 2;
while (size--) {
- be_emit_cstring("\tmovsd");
- be_emit_finish_line_gas(NULL);
+ ia32_emitf(NULL, "\tmovsd\n");
}
}
{
ir_mode *ls_mode = get_ia32_ls_mode(node);
int ls_bits = get_mode_size_bits(ls_mode);
+ const char *conv;
- be_emit_cstring("\tcvt");
-
- if(is_ia32_Conv_I2FP(node)) {
- if(ls_bits == 32) {
- be_emit_cstring("si2ss");
+ if (is_ia32_Conv_I2FP(node)) {
+ if (ls_bits == 32) {
+ conv = "si2ss";
} else {
- be_emit_cstring("si2sd");
+ conv = "si2sd";
}
- } else if(is_ia32_Conv_FP2I(node)) {
- if(ls_bits == 32) {
- be_emit_cstring("ss2si");
+ } else if (is_ia32_Conv_FP2I(node)) {
+ if (ls_bits == 32) {
+ conv = "ss2si";
} else {
- be_emit_cstring("sd2si");
+ conv = "sd2si";
}
} else {
assert(is_ia32_Conv_FP2FP(node));
- if(ls_bits == 32) {
- be_emit_cstring("sd2ss");
+ if (ls_bits == 32) {
+ conv = "sd2ss";
} else {
- be_emit_cstring("ss2sd");
+ conv = "ss2sd";
}
}
- be_emit_char(' ');
- switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- ia32_emit_source_register(node, n_ia32_unary_op);
- break;
- case ia32_AddrModeS:
- ia32_emit_am(node);
- break;
- default:
- assert(0 && "unsupported op type for Conv");
- }
- be_emit_cstring(", ");
- ia32_emit_dest_register(node, 0);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
}
static void emit_ia32_Conv_I2FP(const ir_node *node)
*/
static void emit_ia32_Conv_I2I(const ir_node *node)
{
- const char *sign_suffix;
- ir_mode *smaller_mode = get_ia32_ls_mode(node);
- int smaller_bits = get_mode_size_bits(smaller_mode);
- int signed_mode;
- const arch_register_t *in_reg, *out_reg;
+ ir_mode *smaller_mode = get_ia32_ls_mode(node);
+ int smaller_bits = get_mode_size_bits(smaller_mode);
+ int signed_mode = mode_is_signed(smaller_mode);
assert(!mode_is_float(smaller_mode));
- assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
-
- signed_mode = mode_is_signed(smaller_mode);
- if(smaller_bits == 32) {
- // this should not happen as it's no convert
- assert(0);
- sign_suffix = "";
+ assert(smaller_bits == 8 || smaller_bits == 16);
+
+ if (signed_mode &&
+ smaller_bits == 16 &&
+ &ia32_gp_regs[REG_EAX] == get_out_reg(node, 0) &&
+ &ia32_gp_regs[REG_EAX] == arch_get_irn_register(get_irn_n(node, n_ia32_unary_op))) {
+ /* argument and result are both in EAX and signedness is ok: use the
+ * smaller cwtl opcode */
+ ia32_emitf(node, "\tcwtl\n");
} else {
- sign_suffix = signed_mode ? "s" : "z";
+ const char *sign_suffix = signed_mode ? "s" : "z";
+ ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
}
+}
- out_reg = get_out_reg(node, 0);
-
- switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- in_reg = get_in_reg(node, n_ia32_unary_op);
-
- if (in_reg == &ia32_gp_regs[REG_EAX] &&
- out_reg == &ia32_gp_regs[REG_EAX] &&
- signed_mode &&
- smaller_bits == 16)
- {
- /* argument and result are both in EAX and */
- /* signedness is ok: -> use the smaller cwtl opcode */
- be_emit_cstring("\tcwtl");
- } else {
- be_emit_cstring("\tmov");
- be_emit_string(sign_suffix);
- ia32_emit_mode_suffix_mode(smaller_mode);
- be_emit_cstring("l ");
- emit_register(in_reg, smaller_mode);
- be_emit_cstring(", ");
- emit_register(out_reg, NULL);
- }
- break;
- case ia32_AddrModeS: {
- be_emit_cstring("\tmov");
- be_emit_string(sign_suffix);
- ia32_emit_mode_suffix_mode(smaller_mode);
- be_emit_cstring("l ");
- ia32_emit_am(node);
- be_emit_cstring(", ");
- emit_register(out_reg, NULL);
- break;
- }
- default:
- assert(0 && "unsupported op type for Conv");
- }
- be_emit_finish_line_gas(node);
+/**
+ * Emits a call
+ */
+static void emit_ia32_Call(const ir_node *node)
+{
+ /* Special case: Call must not have its immediates prefixed by $, instead
+ * address mode is prefixed by *. */
+ ia32_emitf(node, "\tcall %*AS3\n");
}
*
*******************************************/
-/**
- * Emits a backend call
- */
-static void emit_be_Call(const ir_node *node)
-{
- ir_entity *ent = be_Call_get_entity(node);
-
- be_emit_cstring("\tcall ");
- if (ent) {
- ia32_emit_entity(ent, 1);
- } else {
- const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
- be_emit_char('*');
- emit_register(reg, NULL);
- }
- be_emit_finish_line_gas(node);
-}
-
/**
* Emits code to increase stack pointer.
*/
static void emit_be_IncSP(const ir_node *node)
{
- int offs = be_get_IncSP_offset(node);
- const arch_register_t *reg = arch_get_irn_register(arch_env, node);
+ int offs = be_get_IncSP_offset(node);
if (offs == 0)
return;
if (offs > 0) {
- be_emit_cstring("\tsubl $");
- be_emit_irprintf("%u, ", offs);
- emit_register(reg, NULL);
+ ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
} else {
- be_emit_cstring("\taddl $");
- be_emit_irprintf("%u, ", -offs);
- emit_register(reg, NULL);
+ ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
}
- be_emit_finish_line_gas(node);
}
/**
*/
static void Copy_emitter(const ir_node *node, const ir_node *op)
{
- const arch_register_t *in = arch_get_irn_register(arch_env, op);
- const arch_register_t *out = arch_get_irn_register(arch_env, node);
- ir_mode *mode;
+ const arch_register_t *in = arch_get_irn_register(op);
+ const arch_register_t *out = arch_get_irn_register(node);
- if(in == out) {
+ if (in == out) {
return;
}
- if(is_unknown_reg(in))
+ if (is_unknown_reg(in))
return;
/* copies of vf nodes aren't real... */
- if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
return;
- mode = get_irn_mode(node);
- if (mode == mode_E) {
- be_emit_cstring("\tmovsd ");
- emit_register(in, NULL);
- be_emit_cstring(", ");
- emit_register(out, NULL);
+ if (get_irn_mode(node) == mode_E) {
+ ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
} else {
- be_emit_cstring("\tmovl ");
- emit_register(in, NULL);
- be_emit_cstring(", ");
- emit_register(out, NULL);
+ ia32_emitf(node, "\tmovl %R, %R\n", in, out);
}
- be_emit_finish_line_gas(node);
}
static void emit_be_Copy(const ir_node *node)
const arch_register_t *in0, *in1;
const arch_register_class_t *cls0, *cls1;
- in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
- in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
+ in0 = arch_get_irn_register(get_irn_n(node, 0));
+ in1 = arch_get_irn_register(get_irn_n(node, 1));
cls0 = arch_register_get_class(in0);
cls1 = arch_register_get_class(in1);
assert(cls0 == cls1 && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
- be_emit_cstring("\txchg ");
- emit_register(in1, NULL);
- be_emit_cstring(", ");
- emit_register(in0, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
- be_emit_cstring("\txorpd ");
- emit_register(in1, NULL);
- be_emit_cstring(", ");
- emit_register(in0, NULL);
- be_emit_finish_line_gas(NULL);
-
- be_emit_cstring("\txorpd ");
- emit_register(in0, NULL);
- be_emit_cstring(", ");
- emit_register(in1, NULL);
- be_emit_finish_line_gas(NULL);
-
- be_emit_cstring("\txorpd ");
- emit_register(in1, NULL);
- be_emit_cstring(", ");
- emit_register(in0, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
+ ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
+ ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
/* is a NOP */
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
/* is a NOP */
} else {
- panic("unexpected register class in be_Perm (%+F)\n", node);
+ panic("unexpected register class in be_Perm (%+F)", node);
}
}
*/
static void emit_ia32_Const(const ir_node *node)
{
- be_emit_cstring("\tmovl ");
- emit_ia32_Immediate(node);
- be_emit_cstring(", ");
- ia32_emit_dest_register(node, 0);
-
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tmovl %I, %D0\n");
}
/**
*/
static void emit_ia32_LdTls(const ir_node *node)
{
- be_emit_cstring("\tmovl %gs:0, ");
- ia32_emit_dest_register(node, 0);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
{
- be_emit_cstring("\tmovl ");
- emit_register(src, NULL);
- be_emit_cstring(", ");
- emit_register(dst, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_neg(const ir_node* node, const arch_register_t *reg)
{
- be_emit_cstring("\tnegl ");
- emit_register(reg, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tnegl %R\n", reg);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
{
- be_emit_cstring("\tsbbl $0, ");
- emit_register(reg, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tsbbl $0, %R\n", reg);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
{
- be_emit_cstring("\tsbbl ");
- emit_register(src, NULL);
- be_emit_cstring(", ");
- emit_register(dst, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
{
- be_emit_cstring("\txchgl ");
- emit_register(src, NULL);
- be_emit_cstring(", ");
- emit_register(dst, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_zero(const ir_node* node, const arch_register_t *reg)
{
- be_emit_cstring("\txorl ");
- emit_register(reg, NULL);
- be_emit_cstring(", ");
- emit_register(reg, NULL);
- be_emit_finish_line_gas(node);
+ ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
}
static void emit_ia32_Minus64Bit(const ir_node *node)
static void emit_ia32_GetEIP(const ir_node *node)
{
- be_emit_cstring("\tcall ");
- be_emit_string(pic_base_label);
- be_emit_finish_line_gas(node);
-
- be_emit_string(pic_base_label);
- be_emit_cstring(":\n");
- be_emit_write_line();
-
- be_emit_cstring("\tpopl ");
- ia32_emit_dest_register(node, 0);
- be_emit_char('\n');
- be_emit_write_line();
+ ia32_emitf(node, "\tcall %s\n", pic_base_label);
+ ia32_emitf(NULL, "%s:\n", pic_base_label);
+ ia32_emitf(node, "\tpopl %D0\n");
}
static void emit_be_Return(const ir_node *node)
{
- unsigned pop;
- be_emit_cstring("\tret");
+ unsigned pop = be_Return_get_pop(node);
- pop = be_Return_get_pop(node);
if (pop > 0 || be_Return_get_emit_pop(node)) {
- be_emit_irprintf(" $%d", pop);
+ ia32_emitf(node, "\tret $%u\n", pop);
+ } else {
+ ia32_emitf(node, "\tret\n");
}
- be_emit_finish_line_gas(node);
}
static void emit_Nothing(const ir_node *node)
* Enters the emitter functions for handled nodes into the generic
* pointer of an opcode.
*/
-static void ia32_register_emitters(void) {
-
+static void ia32_register_emitters(void)
+{
#define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
#define IA32_EMIT(a) IA32_EMIT2(a,a)
#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
ia32_register_spec_emitters();
/* other ia32 emitter functions */
+ IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
IA32_EMIT(Asm);
IA32_EMIT(CMov);
- IA32_EMIT(IMul);
- IA32_EMIT(SwitchJmp);
- IA32_EMIT(CopyB);
- IA32_EMIT(CopyB_i);
- IA32_EMIT(Conv_I2FP);
- IA32_EMIT(Conv_FP2I);
+ IA32_EMIT(Call);
+ IA32_EMIT(Const);
IA32_EMIT(Conv_FP2FP);
+ IA32_EMIT(Conv_FP2I);
+ IA32_EMIT(Conv_I2FP);
IA32_EMIT(Conv_I2I);
- IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
- IA32_EMIT(Const);
+ IA32_EMIT(CopyB);
+ IA32_EMIT(CopyB_i);
+ IA32_EMIT(GetEIP);
+ IA32_EMIT(IMul);
+ IA32_EMIT(Jcc);
IA32_EMIT(LdTls);
IA32_EMIT(Minus64Bit);
- IA32_EMIT(Jcc);
- IA32_EMIT(GetEIP);
+ IA32_EMIT(SwitchJmp);
/* benode emitter */
- BE_EMIT(Call);
- BE_EMIT(IncSP);
BE_EMIT(Copy);
BE_EMIT(CopyKeep);
+ BE_EMIT(IncSP);
BE_EMIT(Perm);
BE_EMIT(Return);
- BE_IGN(RegParams);
BE_IGN(Barrier);
BE_IGN(Keep);
+ BE_IGN(RegParams);
/* firm emitter */
EMIT(Jmp);
- IGN(Proj);
IGN(Phi);
IGN(Start);
typedef void (*emit_func_ptr) (const ir_node *);
+/**
+ * Assign and emit an exception label if the current instruction can fail.
+ */
+static void ia32_assign_exc_label(ir_node *node)
+{
+ /* assign a new ID to the instruction */
+ set_ia32_exc_label_id(node, ++exc_label_id);
+ /* print it */
+ ia32_emit_exc_label(node);
+ be_emit_char(':');
+ be_emit_pad_comment();
+ be_emit_cstring("/* exception to Block ");
+ ia32_emit_cfop_target(node);
+ be_emit_cstring(" */\n");
+ be_emit_write_line();
+}
+
/**
* Emits code for a node.
*/
DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
- if (is_ia32_irn(node) && get_ia32_exc_label(node)) {
- /* emit the exception label of this instruction */
- ia32_assign_exc_label(node);
+ if (is_ia32_irn(node)) {
+ if (get_ia32_exc_label(node)) {
+ /* emit the exception label of this instruction */
+ ia32_assign_exc_label(node);
+ }
+ if (mark_spill_reload) {
+ if (is_ia32_is_spill(node)) {
+ ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
+ }
+ if (is_ia32_is_reload(node)) {
+ ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
+ }
+ if (is_ia32_is_remat(node)) {
+ ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
+ }
+ }
}
if (op->ops.generic) {
emit_func_ptr func = (emit_func_ptr) op->ops.generic;
*/
static void ia32_emit_alignment(unsigned align, unsigned skip)
{
- be_emit_cstring("\t.p2align ");
- be_emit_irprintf("%u,,%u\n", align, skip);
- be_emit_write_line();
+ ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
}
/**
* 16 bytes. However we should only do that if the alignment nops before the
* label aren't executed more often than we have jumps to the label.
*/
-static int should_align_block(ir_node *block, ir_node *prev)
+static int should_align_block(const ir_node *block)
{
static const double DELTA = .0001;
ir_exec_freq *exec_freq = cg->birg->exec_freq;
+ ir_node *prev = get_prev_block_sched(block);
double block_freq;
double prev_freq = 0; /**< execfreq of the fallthrough block */
double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
int i, n_cfgpreds;
- if(exec_freq == NULL)
+ if (exec_freq == NULL)
return 0;
- if(ia32_cg_config.label_alignment_factor <= 0)
+ if (ia32_cg_config.label_alignment_factor <= 0)
return 0;
block_freq = get_block_execfreq(exec_freq, block);
- if(block_freq < DELTA)
+ if (block_freq < DELTA)
return 0;
n_cfgpreds = get_Block_n_cfgpreds(block);
for(i = 0; i < n_cfgpreds; ++i) {
- ir_node *pred = get_Block_cfgpred_block(block, i);
- double pred_freq = get_block_execfreq(exec_freq, pred);
+ const ir_node *pred = get_Block_cfgpred_block(block, i);
+ double pred_freq = get_block_execfreq(exec_freq, pred);
- if(pred == prev) {
+ if (pred == prev) {
prev_freq += pred_freq;
} else {
jmp_freq += pred_freq;
}
}
- if(prev_freq < DELTA && !(jmp_freq < DELTA))
+ if (prev_freq < DELTA && !(jmp_freq < DELTA))
return 1;
jmp_freq /= prev_freq;
return jmp_freq > ia32_cg_config.label_alignment_factor;
}
-/**
- * Return non-zero, if a instruction in a fall-through.
- */
-static int is_fallthrough(ir_node *cfgpred)
-{
- ir_node *pred;
-
- if(!is_Proj(cfgpred))
- return 1;
- pred = get_Proj_pred(cfgpred);
- if(is_ia32_SwitchJmp(pred))
- return 0;
-
- return 1;
-}
-
/**
* Emit the block header for a block.
*
* @param block the block
* @param prev_block the previous block
*/
-static void ia32_emit_block_header(ir_node *block, ir_node *prev_block)
+static void ia32_emit_block_header(ir_node *block)
{
ir_graph *irg = current_ir_graph;
- int n_cfgpreds;
- int need_label = 1;
+ int need_label = block_needs_label(block);
int i, arity;
ir_exec_freq *exec_freq = cg->birg->exec_freq;
if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
return;
- n_cfgpreds = get_Block_n_cfgpreds(block);
-
- if (n_cfgpreds == 0) {
- need_label = 0;
- } else if (n_cfgpreds == 1) {
- ir_node *cfgpred = get_Block_cfgpred(block, 0);
- if (get_nodes_block(cfgpred) == prev_block && is_fallthrough(cfgpred)) {
- need_label = 0;
- }
- }
-
if (ia32_cg_config.label_alignment > 0) {
/* align the current block if:
* a) if should be aligned due to its execution frequency
* b) there is no fall-through here
*/
- if (should_align_block(block, prev_block)) {
+ if (should_align_block(block)) {
ia32_emit_align_label();
} else {
/* if the predecessor block has no fall-through,
we can always align the label. */
int i;
- ir_node *check_node = NULL;
+ int has_fallthrough = 0;
- for (i = n_cfgpreds - 1; i >= 0; --i) {
+ for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
ir_node *cfg_pred = get_Block_cfgpred(block, i);
-
- if (get_nodes_block(skip_Proj(cfg_pred)) == prev_block) {
- check_node = cfg_pred;
+ if (can_be_fallthrough(cfg_pred)) {
+ has_fallthrough = 1;
break;
}
}
- if (check_node == NULL || !is_fallthrough(check_node))
+
+ if (!has_fallthrough)
ia32_emit_align_label();
}
}
* Walks over the nodes in a block connected by scheduling edges
* and emits code for each node.
*/
-static void ia32_gen_block(ir_node *block, ir_node *last_block)
+static void ia32_gen_block(ir_node *block)
{
ir_node *node;
- ia32_emit_block_header(block, last_block);
+ ia32_emit_block_header(block);
/* emit the contents of the block */
be_dbg_set_dbg_info(get_irn_dbg_info(block));
}
}
-/**
- * Assign and emit an exception label if the current instruction can fail.
- */
-void ia32_assign_exc_label(ir_node *node)
-{
- if (get_ia32_exc_label(node)) {
- /* assign a new ID to the instruction */
- set_ia32_exc_label_id(node, ++exc_label_id);
- /* print it */
- ia32_emit_exc_label(node);
- be_emit_char(':');
- be_emit_pad_comment();
- be_emit_cstring("/* exception to Block ");
- ia32_emit_cfop_target(node);
- be_emit_cstring(" */\n");
- be_emit_write_line();
- }
-}
-
/**
* Compare two exception_entries.
*/
-static int cmp_exc_entry(const void *a, const void *b) {
+static int cmp_exc_entry(const void *a, const void *b)
+{
const exc_entry *ea = a;
const exc_entry *eb = b;
*/
void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
{
- ir_node *block;
- ir_node *last_block = NULL;
ir_entity *entity = get_irg_entity(irg);
exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
int i, n;
be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
/* we use links to point to target blocks */
- set_using_irn_link(irg);
+ ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
+ /* initialize next block links */
n = ARR_LEN(cg->blk_sched);
- for (i = 0; i < n;) {
- ir_node *next_bl;
+ for (i = 0; i < n; ++i) {
+ ir_node *block = cg->blk_sched[i];
+ ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
+
+ set_irn_link(block, prev);
+ }
- block = cg->blk_sched[i];
- ++i;
- next_bl = i < n ? cg->blk_sched[i] : NULL;
+ for (i = 0; i < n; ++i) {
+ ir_node *block = cg->blk_sched[i];
- /* set here the link. the emitter expects to find the next block here */
- set_irn_link(block, next_bl);
- ia32_gen_block(block, last_block);
- last_block = block;
+ ia32_gen_block(block);
}
be_gas_emit_function_epilog(entity);
be_emit_char('\n');
be_emit_write_line();
- clear_using_irn_link(irg);
+ ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
/* Sort the exception table using the exception label id's.
Those are ascending with ascending addresses. */
DEL_ARR_F(exc_list);
}
+static const lc_opt_table_entry_t ia32_emitter_options[] = {
+ LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
+ LC_OPT_LAST
+};
+
void ia32_init_emitter(void)
{
+ lc_opt_entry_t *be_grp;
+ lc_opt_entry_t *ia32_grp;
+
+ be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+ ia32_grp = lc_opt_get_grp(be_grp, "ia32");
+
+ lc_opt_add_table(ia32_grp, ia32_emitter_options);
+
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");
}
projects / libfirm / blobdiff