#include "irargs_t.h"
#include "irprog_t.h"
#include "iredges_t.h"
+#include "irtools.h"
#include "execfreq.h"
#include "error.h"
#include "raw_bitset.h"
#include "dbginfo.h"
+#include "lc_opts.h"
-#include "../besched_t.h"
-#include "../benode_t.h"
+#include "../besched.h"
+#include "../benode.h"
#include "../beabi.h"
#include "../be_dbgout.h"
#include "../beemitter.h"
#include "../begnuas.h"
-#include "../beirg_t.h"
+#include "../beirg.h"
#include "../be_dbgout.h"
#include "ia32_emitter.h"
static const ia32_isa_t *isa;
static ia32_code_gen_t *cg;
-static int do_pic;
static char pic_base_label[128];
static ir_label_t exc_label_id;
static int mark_spill_reload = 0;
+static int do_pic;
/** Return the next block in Block schedule */
static ir_node *get_prev_block_sched(const ir_node *block)
return get_irn_link(block);
}
+/** Checks if the current block is a fall-through target. */
static int is_fallthrough(const ir_node *cfgpred)
{
ir_node *pred;
return 1;
}
+/**
+ * returns non-zero if the given block needs a label
+ * because of being a jump-target (and not a fall-through)
+ */
static int block_needs_label(const ir_node *block)
{
int need_label = 1;
int n_cfgpreds = get_Block_n_cfgpreds(block);
+ if (has_Block_entity(block))
+ return 1;
+
if (n_cfgpreds == 0) {
need_label = 0;
} else if (n_cfgpreds == 1) {
* |_| |_|
*************************************************************/
+/**
+ * Emit the name of the 8bit low register
+ */
static void emit_8bit_register(const arch_register_t *reg)
{
const char *reg_name = arch_register_get_name(reg);
be_emit_char('l');
}
+/**
+ * Emit the name of the 8bit high register
+ */
+static void emit_8bit_register_high(const arch_register_t *reg)
+{
+ const char *reg_name = arch_register_get_name(reg);
+
+ be_emit_char('%');
+ be_emit_char(reg_name[1]);
+ be_emit_char('h');
+}
+
static void emit_16bit_register(const arch_register_t *reg)
{
const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
be_emit_string(reg_name);
}
+/**
+ * emit a register, possible shortened by a mode
+ *
+ * @param reg the register
+ * @param mode the mode of the register or NULL for full register
+ */
static void emit_register(const arch_register_t *reg, const ir_mode *mode)
{
const char *reg_name;
static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
{
- ident *id;
-
set_entity_backend_marked(entity, 1);
- id = get_entity_ld_ident(entity);
- be_emit_ident(id);
+ be_gas_emit_entity(entity);
if (get_entity_owner(entity) == get_tls_type()) {
if (get_entity_visibility(entity) == visibility_external_allocated) {
}
}
- if (!no_pic_adjust && do_pic) {
- /* TODO: only do this when necessary */
+ if (do_pic && !no_pic_adjust) {
be_emit_char('-');
be_emit_string(pic_base_label);
}
if (attr->symconst != NULL) {
if (attr->sc_sign)
be_emit_char('-');
- ia32_emit_entity(attr->symconst, 0);
+ ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
}
if (attr->symconst == NULL || attr->offset != 0) {
if (attr->symconst != NULL) {
void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
{
const arch_register_t *reg;
- ir_node *in = get_irn_n(node, pos);
+ const ir_node *in = get_irn_n(node, pos);
if (is_ia32_Immediate(in)) {
emit_ia32_Immediate(in);
return;
emit_8bit_register(reg);
}
+void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
+{
+ const arch_register_t *reg = get_in_reg(node, pos);
+ emit_8bit_register_high(reg);
+}
+
+void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
+{
+ const arch_register_t *reg;
+ const ir_node *in = get_irn_n(node, pos);
+ if (is_ia32_Immediate(in)) {
+ emit_ia32_Immediate(in);
+ return;
+ }
+
+ reg = get_in_reg(node, pos);
+ emit_16bit_register(reg);
+}
+
void ia32_emit_dest_register(const ir_node *node, int pos)
{
const arch_register_t *reg = get_out_reg(node, pos);
emit_register(reg, NULL);
}
+void ia32_emit_dest_register_size(const ir_node *node, int pos)
+{
+ const arch_register_t *reg = get_out_reg(node, pos);
+
+ emit_register(reg, get_ia32_ls_mode(node));
+}
+
void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
{
const arch_register_t *reg = get_out_reg(node, pos);
be_emit_char(get_xmm_mode_suffix(mode));
}
-void ia32_emit_extend_suffix(const ir_mode *mode)
+void ia32_emit_extend_suffix(const ir_node *node)
{
+ ir_mode *mode = get_ia32_ls_mode(node);
if (get_mode_size_bits(mode) == 32)
return;
be_emit_char(mode_is_signed(mode) ? 's' : 'z');
+ ia32_emit_mode_suffix_mode(mode);
}
void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
*/
static void ia32_emit_block_name(const ir_node *block)
{
- if (has_Block_label(block)) {
- be_emit_string(be_gas_block_label_prefix());
- be_emit_irprintf("%lu", get_Block_label(block));
+ if (has_Block_entity(block)) {
+ ir_entity *entity = get_Block_entity(block);
+ be_gas_emit_entity(entity);
} else {
be_emit_cstring(BLOCK_PREFIX);
be_emit_irprintf("%ld", get_irn_node_nr(block));
NULL /* always true */
};
+/**
+ * Emit the suffix for a compare instruction.
+ */
static void ia32_emit_cmp_suffix(int pnc)
{
const char *str;
+ if (pnc == ia32_pn_Cmp_parity) {
+ be_emit_char('p');
+ return;
+ }
if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
str = cmp2condition_u[pnc & 7];
} else {
typedef enum ia32_emit_mod_t {
EMIT_RESPECT_LS = 1U << 0,
- EMIT_ALTERNATE_AM = 1U << 1
+ EMIT_ALTERNATE_AM = 1U << 1,
+ EMIT_LONG = 1U << 2
} ia32_emit_mod_t;
+/**
+ * Emits address mode.
+ */
+void ia32_emit_am(const ir_node *node)
+{
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ int has_base = !is_ia32_NoReg_GP(base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(index);
+
+ /* just to be sure... */
+ assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
+
+ /* emit offset */
+ if (ent != NULL) {
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ if (is_ia32_am_sc_sign(node))
+ be_emit_char('-');
+ ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
+ }
+
+ /* also handle special case if nothing is set */
+ if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
+ if (ent != NULL) {
+ be_emit_irprintf("%+d", offs);
+ } else {
+ be_emit_irprintf("%d", offs);
+ }
+ }
+
+ if (has_base || has_index) {
+ be_emit_char('(');
+
+ /* emit base */
+ if (has_base) {
+ const arch_register_t *reg = get_in_reg(node, n_ia32_base);
+ emit_register(reg, NULL);
+ }
+
+ /* emit index + scale */
+ if (has_index) {
+ const arch_register_t *reg = get_in_reg(node, n_ia32_index);
+ int scale;
+ be_emit_char(',');
+ emit_register(reg, NULL);
+
+ scale = get_ia32_am_scale(node);
+ if (scale > 0) {
+ be_emit_irprintf(",%d", 1 << scale);
+ }
+ }
+ be_emit_char(')');
+ }
+}
+
/**
* fmt parameter output
* ---- ---------------------- ---------------------------------------------
* %Sx <node> source register x
* %s const char* string
* %u unsigned int unsigned int
+ * %d signed int signed int
*
* x starts at 0
* # modifier for %ASx, %D and %S uses ls mode of node to alter register width
* * modifier does not prefix immediates with $, but AM with *
+ * l modifier for %lu and %ld
*/
static void ia32_emitf(const ir_node *node, const char *fmt, ...)
{
++fmt;
}
+ if (*fmt == 'l') {
+ mod |= EMIT_LONG;
+ ++fmt;
+ }
+
switch (*fmt++) {
case '%':
be_emit_char('%');
case 'M':
if (mod & EMIT_ALTERNATE_AM)
be_emit_char('*');
+
ia32_emit_am(node);
break;
break;
}
- case 'u': {
- unsigned num = va_arg(ap, unsigned);
- be_emit_irprintf("%u", num);
+ case 'u':
+ if (mod & EMIT_LONG) {
+ unsigned long num = va_arg(ap, unsigned long);
+ be_emit_irprintf("%lu", num);
+ } else {
+ unsigned num = va_arg(ap, unsigned);
+ be_emit_irprintf("%u", num);
+ }
+ break;
+
+ case 'd':
+ if (mod & EMIT_LONG) {
+ long num = va_arg(ap, long);
+ be_emit_irprintf("%ld", num);
+ } else {
+ int num = va_arg(ap, int);
+ be_emit_irprintf("%d", num);
+ }
break;
- }
default:
unknown:
- panic("unknown conversion");
+ panic("unknown format conversion in ia32_emitf()");
}
}
ia32_emitf(node, fmt);
}
-/**
- * Emits address mode.
- */
-void ia32_emit_am(const ir_node *node)
-{
- ir_entity *ent = get_ia32_am_sc(node);
- int offs = get_ia32_am_offs_int(node);
- ir_node *base = get_irn_n(node, n_ia32_base);
- int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
-
- /* just to be sure... */
- assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
-
- /* emit offset */
- if (ent != NULL) {
- if (is_ia32_am_sc_sign(node))
- be_emit_char('-');
- ia32_emit_entity(ent, 0);
- }
-
- /* also handle special case if nothing is set */
- if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
- if (ent != NULL) {
- be_emit_irprintf("%+d", offs);
- } else {
- be_emit_irprintf("%d", offs);
- }
- }
-
- if (has_base || has_index) {
- be_emit_char('(');
-
- /* emit base */
- if (has_base) {
- const arch_register_t *reg = get_in_reg(node, n_ia32_base);
- emit_register(reg, NULL);
- }
-
- /* emit index + scale */
- if (has_index) {
- const arch_register_t *reg = get_in_reg(node, n_ia32_index);
- int scale;
- be_emit_char(',');
- emit_register(reg, NULL);
-
- scale = get_ia32_am_scale(node);
- if (scale > 0) {
- be_emit_irprintf(",%d", 1 << scale);
- }
- }
- be_emit_char(')');
- }
-}
-
static void emit_ia32_IMul(const ir_node *node)
{
ir_node *left = get_irn_n(node, n_ia32_IMul_left);
/**
* Emits code for a unconditional jump.
*/
-static void emit_Jmp(const ir_node *node)
+static void emit_ia32_Jmp(const ir_node *node)
{
ir_node *block;
}
}
+static inline bool is_unknown_reg(const arch_register_t *reg)
+{
+ if(reg == &ia32_gp_regs[REG_GP_UKNWN]
+ || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
+ || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
+ return true;
+
+ return false;
+}
+
/**
* Emits code for Copy/CopyKeep.
*/
ia32_emitf(node, "\tpopl %D0\n");
}
+static void emit_ia32_ClimbFrame(const ir_node *node)
+{
+ const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
+
+ ia32_emitf(node, "\tmovl %S0, %D0\n");
+ ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
+ ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
+ ia32_emitf(node, "\tmovl (%D0), %D0\n");
+ ia32_emitf(node, "\tdec %S1\n");
+ ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
+}
+
static void emit_be_Return(const ir_node *node)
{
unsigned pop = be_Return_get_pop(node);
IA32_EMIT(LdTls);
IA32_EMIT(Minus64Bit);
IA32_EMIT(SwitchJmp);
+ IA32_EMIT(ClimbFrame);
+ IA32_EMIT(Jmp);
/* benode emitter */
BE_EMIT(Copy);
BE_IGN(Barrier);
BE_IGN(Keep);
- BE_IGN(RegParams);
+ BE_IGN(Start);
/* firm emitter */
- EMIT(Jmp);
IGN(Phi);
- IGN(Start);
#undef BE_EMIT
#undef EMIT
}
}
- if (need_label || has_Block_label(block)) {
+ if (need_label) {
ia32_emit_block_name(block);
be_emit_char(':');
LC_OPT_LAST
};
+/* ==== Experimental binary emitter ==== */
+
+static unsigned char reg_gp_map[N_ia32_gp_REGS];
+static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
+static unsigned char reg_sse_map[N_ia32_xmm_REGS];
+
+static void build_reg_map(void)
+{
+ reg_gp_map[REG_EAX] = 0x0;
+ reg_gp_map[REG_ECX] = 0x1;
+ reg_gp_map[REG_EDX] = 0x2;
+ reg_gp_map[REG_EBX] = 0x3;
+ reg_gp_map[REG_ESP] = 0x4;
+ reg_gp_map[REG_EBP] = 0x5;
+ reg_gp_map[REG_ESI] = 0x6;
+ reg_gp_map[REG_EDI] = 0x7;
+}
+
+/** The mod encoding of the ModR/M */
+enum Mod {
+ MOD_IND = 0x00, /**< [reg1] */
+ MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
+ MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
+ MOD_REG = 0xC0 /**< reg1 */
+};
+
+#define GET_MODE(code) ((code) & 0xC0)
+
+/** Sign extension bit values for binops */
+enum SignExt {
+ UNSIGNED_IMM = 0, /**< unsigned immediate */
+ SIGNEXT_IMM = 2, /**< sign extended immediate */
+};
+
+/** create R/M encoding for ModR/M */
+#define ENC_RM(x) (x)
+/** create REG encoding for ModR/M */
+#define ENC_REG(x) ((x) << 3)
+
+/** create Base encoding for SIB */
+#define ENC_BASE(x) (x)
+/** create Index encoding for SIB */
+#define ENC_INDEX(x) ((x) << 3)
+/** create Scale encoding for SIB */
+#define ENC_SCALE(x) ((x) << 6)
+
+/* Node: The following routines are supposed to append bytes, words, dwords
+ to the output stream.
+ Currently the implementation is stupid in that it still creates output
+ for an "assembler" in the form of .byte, .long
+ We will change this when enough infrastructure is there to create complete
+ machine code in memory/object files */
+
+static void bemit8(const unsigned char byte)
+{
+ be_emit_irprintf("\t.byte 0x%x\n", byte);
+ be_emit_write_line();
+}
+
+static void bemit16(const unsigned u16)
+{
+ be_emit_irprintf("\t.word 0x%x\n", u16);
+ be_emit_write_line();
+}
+
+static void bemit32(const unsigned u32)
+{
+ be_emit_irprintf("\t.long 0x%x\n", u32);
+ be_emit_write_line();
+}
+
+static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
+ bool is_relative)
+{
+ if (entity == NULL) {
+ bemit32(offset);
+ return;
+ }
+
+ /* the final version should remember the position in the bytestream
+ and patch it with the correct address at linktime... */
+ be_emit_cstring("\t.long ");
+ if (entity_sign)
+ be_emit_char('-');
+ set_entity_backend_marked(entity, 1);
+ be_gas_emit_entity(entity);
+
+ if (is_relative) {
+ be_emit_cstring("-.");
+ }
+
+ if (offset != 0) {
+ be_emit_irprintf("%+d", offset);
+ }
+ be_emit_char('\n');
+ be_emit_write_line();
+}
+
+/* end emit routines, all emitters following here should only use the functions
+ above. */
+
+/** Create a ModR/M byte for src1,src2 registers */
+static void bemit_modrr(const arch_register_t *src1,
+ const arch_register_t *src2)
+{
+ unsigned char modrm = MOD_REG;
+ modrm |= ENC_RM(reg_gp_map[src1->index]);
+ modrm |= ENC_REG(reg_gp_map[src2->index]);
+ bemit8(modrm);
+}
+
+/** Create a ModR/M byte for one register and extension */
+static void bemit_modru(const arch_register_t *reg, unsigned ext)
+{
+ unsigned char modrm = MOD_REG;
+ assert(ext <= 7);
+ modrm |= ENC_RM(reg_gp_map[reg->index]);
+ modrm |= ENC_REG(ext);
+ bemit8(modrm);
+}
+
+/**
+ * Calculate the size of an (unsigned) immediate in bytes.
+ *
+ * @param offset an offset
+ */
+static unsigned get_unsigned_imm_size(unsigned offset)
+{
+ if (offset < 256) {
+ return 1;
+ } else if (offset < 65536) {
+ return 2;
+ } else {
+ return 4;
+ }
+}
+
+/**
+ * Calculate the size of an signed immediate in bytes.
+ *
+ * @param offset an offset
+ */
+static unsigned get_signed_imm_size(int offset)
+{
+ if (-128 <= offset && offset < 128) {
+ return 1;
+ } else if (offset >= -32768 && offset < 32767) {
+ return 2;
+ } else {
+ return 4;
+ }
+}
+
+/**
+ * Emit a binop with a immediate operand.
+ *
+ * @param node the node to emit
+ * @param opcode_eax the opcode for the op eax, imm variant
+ * @param opcode the opcode for the reg, imm variant
+ * @param ruval the opcode extension for opcode
+ */
+static void bemit_binop_with_imm(
+ const ir_node *node,
+ unsigned char opcode_ax,
+ unsigned char opcode, unsigned char ruval)
+{
+ const arch_register_t *reg = get_out_reg(node, 0);
+ const ir_node *op = get_irn_n(node, n_ia32_binary_right);
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
+ unsigned size;
+
+ if (attr->symconst != NULL)
+ size = 4;
+ else {
+ /* check for sign extension */
+ size = get_signed_imm_size(attr->offset);
+ }
+
+ switch (size) {
+ case 1:
+ bemit8(opcode | SIGNEXT_IMM);
+ bemit_modru(reg, ruval);
+ bemit8((unsigned char)attr->offset);
+ return;
+ case 2:
+ case 4:
+ /* check for eax variant: this variant is shorter for 32bit immediates only */
+ if (reg->index == REG_EAX) {
+ bemit8(opcode_ax);
+ } else {
+ bemit8(opcode);
+ bemit_modru(reg, ruval);
+ }
+ bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
+ return;
+ }
+ panic("invalid imm size?!?");
+}
+
+/**
+ * Emit an address mode.
+ *
+ * @param reg content of the reg field: either a register index or an opcode extension
+ * @param node the node
+ */
+static void bemit_mod_am(unsigned reg, const ir_node *node)
+{
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ int has_base = !is_ia32_NoReg_GP(base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(index);
+ unsigned modrm = 0;
+ unsigned sib = 0;
+ unsigned emitoffs = 0;
+ bool emitsib = false;
+
+ /* set the mod part depending on displacement */
+ if (ent != NULL) {
+ modrm |= MOD_IND_WORD_OFS;
+ emitoffs = 32;
+ } else if (offs == 0) {
+ modrm |= MOD_IND;
+ emitoffs = 0;
+ } else if (-128 <= offs && offs < 128) {
+ modrm |= MOD_IND_BYTE_OFS;
+ emitoffs = 8;
+ } else {
+ modrm |= MOD_IND_WORD_OFS;
+ emitoffs = 32;
+ }
+
+ /* determine if we need a SIB byte */
+ if (has_index) {
+ int scale;
+ const arch_register_t *reg_index = arch_get_irn_register(index);
+ assert(reg_index->index != REG_ESP);
+ sib |= ENC_INDEX(reg_gp_map[reg_index->index]);
+
+ if (has_base) {
+ const arch_register_t *reg = arch_get_irn_register(base);
+ sib |= ENC_BASE(reg_gp_map[reg->index]);
+ } else {
+ /* use the EBP encoding if NO base register */
+ sib |= 0x05;
+ }
+
+ scale = get_ia32_am_scale(node);
+ assert(scale < 4);
+ sib |= ENC_SCALE(scale);
+ emitsib = true;
+ }
+
+ /* determine modrm byte */
+ if (emitsib) {
+ /* R/M set to ESP means SIB in 32bit mode */
+ modrm |= ENC_RM(0x04);
+ } else if (has_base) {
+ const arch_register_t *reg = arch_get_irn_register(base);
+ if (reg->index == REG_ESP) {
+ /* for the above reason we are forced to emit a sib
+ when base is ESP. Only the base is used */
+ sib = ENC_BASE(0x04);
+ emitsib = true;
+
+ /* we are forced to emit a 8bit offset as EBP base without
+ offset is a special case for SIB without base register */
+ } else if (reg->index == REG_EBP && emitoffs == 0) {
+ assert(GET_MODE(modrm) == MOD_IND);
+ emitoffs = 8;
+ modrm |= MOD_IND_BYTE_OFS;
+ }
+ modrm |= ENC_RM(reg_gp_map[reg->index]);
+ } else {
+ /* only displacement: Use EBP + disp encoding in 32bit mode */
+ if (emitoffs == 0) {
+ emitoffs = 8;
+ modrm = MOD_IND_BYTE_OFS;
+ }
+ modrm |= ENC_RM(0x05);
+ }
+
+ modrm |= ENC_REG(reg);
+
+ bemit8(modrm);
+ if (emitsib)
+ bemit8(sib);
+
+ /* emit displacement */
+ if (emitoffs == 8) {
+ bemit8((unsigned) offs);
+ } else if (emitoffs == 32) {
+ bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
+ }
+}
+
+/**
+ * Emits a binop.
+ */
+static void bemit_binop_2(const ir_node *node, unsigned code)
+{
+ const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
+ ia32_op_type_t am_type = get_ia32_op_type(node);
+ unsigned char d = 0;
+ const arch_register_t *op2;
+
+ switch (am_type) {
+ case ia32_AddrModeS:
+ d = 2;
+ /* FALLTHROUGH */
+ case ia32_AddrModeD:
+ bemit8(code | d);
+ bemit_mod_am(reg_gp_map[out->index], node);
+ return;
+ case ia32_Normal:
+ bemit8(code);
+ op2 = get_in_reg(node, n_ia32_binary_right);
+ bemit_modrr(out, op2);
+ return;
+ }
+ panic("invalid address mode");
+}
+
+/**
+ * Emit a binop.
+ */
+static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
+{
+ ir_node *right = get_irn_n(node, n_ia32_binary_right);
+ if (is_ia32_Immediate(right)) {
+ /* there's a shorter variant with DEST=EAX */
+ const arch_register_t *reg = get_out_reg(node, 0);
+ if (reg->index == REG_EAX)
+
+ bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
+ } else {
+ bemit_binop_2(node, opcodes[0]);
+ }
+}
+
+/**
+ * Emit an unop.
+ */
+static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
+{
+ ia32_op_type_t am_type = get_ia32_op_type(node);
+
+ bemit8(code);
+ if (am_type == ia32_AddrModeD) {
+ bemit8(code);
+ bemit_mod_am(ext, node);
+ } else {
+ const arch_register_t *in = get_in_reg(node, input);
+ assert(am_type == ia32_Normal);
+ bemit_modru(in, ext);
+ }
+}
+
+
+static void bemit_immediate(const ir_node *node, bool relative)
+{
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
+ bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
+}
+
+static void bemit_copy(const ir_node *copy)
+{
+ const ir_node *op = be_get_Copy_op(copy);
+ const arch_register_t *in = arch_get_irn_register(op);
+ const arch_register_t *out = arch_get_irn_register(copy);
+
+ if (in == out || is_unknown_reg(in))
+ return;
+ /* copies of vf nodes aren't real... */
+ if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ return;
+
+ if (get_irn_mode(copy) == mode_E) {
+ panic("NIY");
+ } else {
+ assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
+ bemit8(0x89);
+ bemit_modrr(out, in);
+ }
+}
+
+static void bemit_xor0(const ir_node *node)
+{
+ const arch_register_t *out = get_out_reg(node, 0);
+ bemit8(0x31);
+ bemit_modrr(out, out);
+}
+
+static void bemit_mov_const(const ir_node *node)
+{
+ const arch_register_t *out = get_out_reg(node, 0);
+ bemit8(0xB8 + reg_gp_map[out->index]);
+ bemit_immediate(node, false);
+}
+
+/**
+ * Creates a function for a Binop with 3 possible encodings.
+ */
+#define BINOP(op, op0, op1, op2, op2_ext) \
+static void bemit_ ## op(const ir_node *node) { \
+ static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
+ bemit_binop(node, op ## _codes); \
+}
+
+/* insn def eax,imm imm */
+BINOP(add, 0x01, 0x05, 0x81, 0 )
+BINOP(or, 0x09, 0x0D, 0x81, 1 )
+BINOP(adc, 0x11, 0x15, 0x81, 2 )
+BINOP(sbb, 0x19, 0x1D, 0x81, 3 )
+BINOP(and, 0x21, 0x25, 0x81, 4 )
+BINOP(sub, 0x29, 0x2D, 0x81, 5 )
+BINOP(xor, 0x31, 0x35, 0x81, 6 )
+BINOP(cmp, 0x39, 0x3D, 0x81, 7 )
+
+/**
+ * Creates a function for an Unop with code /ext encoding.
+ */
+#define UNOP(op, code, ext, input) \
+static void bemit_ ## op(const ir_node *node) { \
+ bemit_unop(node, code, ext, input); \
+}
+
+UNOP(not, 0xF7, 2, n_ia32_unary_op)
+UNOP(neg, 0xF7, 3, n_ia32_unary_op)
+UNOP(mul, 0xF7, 4, n_ia32_binary_right)
+UNOP(imul1op, 0xF7, 5, n_ia32_binary_right)
+UNOP(div, 0xF7, 6, n_ia32_unary_op)
+UNOP(idiv, 0xF7, 7, n_ia32_unary_op)
+
+UNOP(ijmp, 0xFF, 4, n_ia32_unary_op)
+
+/**
+ * Emit a Lea.
+ */
+static void bemit_lea(const ir_node *node)
+{
+ const arch_register_t *out = get_out_reg(node, 0);
+ bemit8(0x8D);
+ bemit_mod_am(reg_gp_map[out->index], node);
+}
+
+/**
+ * Emit a single optcode.
+ */
+#define EMIT_SINGLEOP(op, code) \
+static void bemit_ ## op(const ir_node *node) { \
+ (void) node; \
+ bemit8(code); \
+}
+
+//EMIT_SINGLEOP(daa, 0x27)
+//EMIT_SINGLEOP(das, 0x2F)
+//EMIT_SINGLEOP(aaa, 0x37)
+//EMIT_SINGLEOP(aas, 0x3F)
+//EMIT_SINGLEOP(nop, 0x90)
+EMIT_SINGLEOP(cwde, 0x98)
+EMIT_SINGLEOP(cltd, 0x99)
+//EMIT_SINGLEOP(fwait, 0x9B)
+EMIT_SINGLEOP(sahf, 0x9E)
+//EMIT_SINGLEOP(popf, 0x9D)
+EMIT_SINGLEOP(int3, 0xCC)
+//EMIT_SINGLEOP(iret, 0xCF)
+//EMIT_SINGLEOP(xlat, 0xD7)
+//EMIT_SINGLEOP(lock, 0xF0)
+EMIT_SINGLEOP(rep, 0xF3)
+//EMIT_SINGLEOP(halt, 0xF4)
+EMIT_SINGLEOP(cmc, 0xF5)
+EMIT_SINGLEOP(stc, 0xF9)
+//EMIT_SINGLEOP(cli, 0xFA)
+//EMIT_SINGLEOP(sti, 0xFB)
+//EMIT_SINGLEOP(std, 0xFD)
+
+/**
+ * Emits a MOV out, [MEM].
+ */
+static void bemit_load(const ir_node *node)
+{
+ const arch_register_t *out = get_out_reg(node, 0);
+
+ if (out->index == REG_EAX) {
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ int has_base = !is_ia32_NoReg_GP(base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(index);
+
+ if (ent == NULL && !has_base && !has_index) {
+ /* load from constant address to EAX can be encoded
+ as 0xA1 [offset] */
+ bemit8(0xA1);
+ bemit_entity(NULL, 0, offs, false);
+ return;
+ }
+ }
+ bemit8(0x8B);
+ bemit_mod_am(reg_gp_map[out->index], node);
+}
+
+/**
+ * Emits a MOV [mem], in.
+ */
+static void bemit_store(const ir_node *node)
+{
+ const ir_node *value = get_irn_n(node, n_ia32_Store_val);
+
+ if (is_ia32_Immediate(value)) {
+ bemit8(0xC7);
+ bemit_mod_am(0, node);
+ bemit_immediate(value, false);
+ } else {
+ const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
+
+ if (in->index == REG_EAX) {
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ int has_base = !is_ia32_NoReg_GP(base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(index);
+
+ if (ent == NULL && !has_base && !has_index) {
+ /* store to constant address from EAX can be encoded as
+ 0xA3 [offset]*/
+ bemit8(0xA3);
+ bemit_entity(NULL, 0, offs, false);
+ return;
+ }
+ }
+ bemit8(0x89);
+ bemit_mod_am(reg_gp_map[in->index], node);
+ }
+}
+
+/**
+ * Emit a Push.
+ */
+static void bemit_push(const ir_node *node)
+{
+ const ir_node *value = get_irn_n(node, n_ia32_Push_val);
+
+ if (is_ia32_Immediate(value)) {
+ const ia32_immediate_attr_t *attr
+ = get_ia32_immediate_attr_const(value);
+ unsigned size = get_unsigned_imm_size(attr->offset);
+ if (attr->symconst)
+ size = 4;
+ switch (size) {
+ case 1:
+ bemit8(0x6A);
+ bemit8((unsigned char)attr->offset);
+ break;
+ case 2:
+ case 4:
+ bemit8(0x68);
+ bemit_immediate(value, false);
+ break;
+ }
+ } else {
+ bemit8(0xFF);
+ bemit_mod_am(6, node);
+ }
+}
+
+/**
+ * Emit a Pop.
+ */
+static void bemit_pop(const ir_node *node)
+{
+ const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
+ if (get_ia32_op_type(node) == ia32_Normal)
+ bemit8(0x58 + reg_gp_map[reg->index]);
+ else {
+ bemit8(0x8F);
+ bemit_mod_am(0, node);
+ }
+}
+
+static void bemit_call(const ir_node *node)
+{
+ ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
+
+ if (is_ia32_Immediate(proc)) {
+ bemit8(0xE8);
+ bemit_immediate(proc, true);
+ } else {
+ panic("indirect call NIY");
+ }
+}
+
+/**
+ * Emits a return.
+ */
+static void bemit_return(const ir_node *node)
+{
+ unsigned pop = be_Return_get_pop(node);
+ if (pop > 0 || be_Return_get_emit_pop(node)) {
+ bemit8(0xC2);
+ assert(pop <= 0xffff);
+ bemit16(pop);
+ } else {
+ bemit8(0xC3);
+ }
+}
+
+static void bemit_incsp(const ir_node *node)
+{
+ const arch_register_t *reg = get_out_reg(node, 0);
+ int offs = be_get_IncSP_offset(node);
+ unsigned size = get_signed_imm_size(offs);
+ unsigned char w = size == 1 ? 2 : 0;
+
+ bemit8(0x81 | w);
+ if (offs > 0) {
+
+ bemit_modru(reg, 5); /* sub */
+ if (size == 8) {
+ bemit8(offs);
+ } else {
+ bemit32(offs);
+ }
+ } else if (offs < 0) {
+ bemit_modru(reg, 0); /* add */
+ if (size == 8) {
+ bemit8(-offs);
+ } else {
+ bemit32(-offs);
+ }
+ }
+}
+
+/**
+ * The type of a emitter function.
+ */
+typedef void (*emit_func) (const ir_node *);
+
+/**
+ * Set a node emitter. Make it a bit more type safe.
+ */
+static void register_emitter(ir_op *op, emit_func func)
+{
+ op->ops.generic = (op_func) func;
+}
+
+static void ia32_register_binary_emitters(void)
+{
+ /* first clear the generic function pointer for all ops */
+ clear_irp_opcodes_generic_func();
+
+ /* benode emitter */
+ register_emitter(op_be_Copy, bemit_copy);
+ register_emitter(op_be_Return, bemit_return);
+ register_emitter(op_be_IncSP, bemit_incsp);
+ register_emitter(op_ia32_Add, bemit_add);
+ register_emitter(op_ia32_Adc, bemit_adc);
+ register_emitter(op_ia32_And, bemit_and);
+ register_emitter(op_ia32_Or, bemit_or);
+ register_emitter(op_ia32_Cmp, bemit_cmp);
+ register_emitter(op_ia32_Call, bemit_call);
+ register_emitter(op_ia32_Cltd, bemit_cltd);
+ register_emitter(op_ia32_Cmc, bemit_cmc);
+ register_emitter(op_ia32_Stc, bemit_stc);
+ register_emitter(op_ia32_RepPrefix, bemit_rep);
+ register_emitter(op_ia32_Breakpoint, bemit_int3);
+ register_emitter(op_ia32_Sahf, bemit_sahf);
+ register_emitter(op_ia32_Cltd, bemit_cwde);
+ register_emitter(op_ia32_Sub, bemit_sub);
+ register_emitter(op_ia32_Sbb, bemit_sbb);
+ register_emitter(op_ia32_Xor0, bemit_xor0);
+ register_emitter(op_ia32_Xor, bemit_xor);
+ register_emitter(op_ia32_Const, bemit_mov_const);
+ register_emitter(op_ia32_Lea, bemit_lea);
+ register_emitter(op_ia32_Load, bemit_load);
+ register_emitter(op_ia32_Not, bemit_not);
+ register_emitter(op_ia32_Neg, bemit_neg);
+ register_emitter(op_ia32_Push, bemit_push);
+ register_emitter(op_ia32_Pop, bemit_pop);
+ register_emitter(op_ia32_Store, bemit_store);
+ register_emitter(op_ia32_Mul, bemit_mul);
+ register_emitter(op_ia32_IMul1OP, bemit_imul1op);
+ register_emitter(op_ia32_Div, bemit_div);
+ register_emitter(op_ia32_IDiv, bemit_idiv);
+ register_emitter(op_ia32_IJmp, bemit_ijmp);
+
+ /* ignore the following nodes */
+ register_emitter(op_ia32_ProduceVal, emit_Nothing);
+ register_emitter(op_be_Barrier, emit_Nothing);
+ register_emitter(op_be_Keep, emit_Nothing);
+ register_emitter(op_be_Start, emit_Nothing);
+ register_emitter(op_Phi, emit_Nothing);
+ register_emitter(op_Start, emit_Nothing);
+}
+
+static void gen_binary_block(ir_node *block)
+{
+ ir_node *node;
+
+ ia32_emit_block_header(block);
+
+ /* emit the contents of the block */
+ sched_foreach(block, node) {
+ ia32_emit_node(node);
+ }
+}
+
+void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
+{
+ ir_entity *entity = get_irg_entity(irg);
+ int i, n;
+
+ cg = ia32_cg;
+ isa = cg->isa;
+
+ ia32_register_binary_emitters();
+
+ be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
+
+ /* we use links to point to target blocks */
+ ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
+ irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
+
+ /* initialize next block links */
+ n = ARR_LEN(cg->blk_sched);
+ for (i = 0; i < n; ++i) {
+ ir_node *block = cg->blk_sched[i];
+ ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
+
+ set_irn_link(block, prev);
+ }
+
+ for (i = 0; i < n; ++i) {
+ ir_node *block = cg->blk_sched[i];
+ gen_binary_block(block);
+ }
+
+ be_gas_emit_function_epilog(entity);
+ be_dbg_method_end();
+ be_emit_char('\n');
+ be_emit_write_line();
+
+ ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
+}
+
+
+
+
void ia32_init_emitter(void)
{
lc_opt_entry_t *be_grp;
lc_opt_add_table(ia32_grp, ia32_emitter_options);
+ build_reg_map();
+
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");
}
projects / libfirm / blobdiff