case 64:
return 'l';
case 80:
+ case 96:
return 't';
}
} else {
static
int produces_result(const ir_node *node) {
return !(is_ia32_St(node) ||
- is_ia32_Store8Bit(node) ||
is_ia32_CondJmp(node) ||
is_ia32_xCondJmp(node) ||
is_ia32_CmpSet(node) ||
#undef be_emit_cstring
#define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
#define be_emit_ident(env,i) be_emit_ident(env->emit,i)
+#define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
#define be_emit_write_line(env) be_emit_write_line(env->emit)
#define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
#define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
{
- ia32_attr_t *attr = get_ia32_attr(node);
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
assert(pos < 3);
be_emit_char(env, '%');
switch(get_ia32_immop_type(node)) {
case ia32_ImmConst:
tv = get_ia32_Immop_tarval(node);
- be_emit_tarval(env->emit, tv);
+ be_emit_tarval(env, tv);
return;
case ia32_ImmSymConst:
ent = get_ia32_Immop_symconst(node);
- mark_entity_visited(ent);
+ set_entity_backend_marked(ent, 1);
id = get_entity_ld_ident(ent);
be_emit_ident(env, id);
return;
return;
}
-void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
+static
+void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
{
be_emit_char(env, get_mode_suffix(mode));
}
+void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
+{
+ ir_mode *mode = get_ia32_ls_mode(node);
+ if(mode == NULL)
+ mode = mode_Iu;
+
+ ia32_emit_mode_suffix_mode(env, mode);
+}
+
void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
{
ir_mode *mode = get_ia32_ls_mode(node);
if(mode != NULL)
- ia32_emit_mode_suffix(env, mode);
+ ia32_emit_mode_suffix_mode(env, mode);
}
static
}
+static
+void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
/**
* Emits registers and/or address mode of a binary operation.
*/
void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
- switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
- ia32_emit_immediate(env, node);
- be_emit_cstring(env, ", ");
- ia32_emit_source_register(env, node, 2);
- } else {
- const arch_register_t *in1 = get_in_reg(env, node, 2);
- const arch_register_t *in2 = get_in_reg(env, node, 3);
- const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
- const arch_register_t *in;
- const char *in_name;
-
- in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
- out = out ? out : in1;
- in_name = arch_register_get_name(in);
-
- if (is_ia32_emit_cl(node)) {
- assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
- in_name = "cl";
- }
+ int right_pos;
+ const ir_node *right_op;
- be_emit_char(env, '%');
- be_emit_string(env, in_name);
- be_emit_cstring(env, ", %");
- be_emit_string(env, arch_register_get_name(out));
- }
+ switch(get_ia32_op_type(node)) {
+ case ia32_Normal:
+ right_op = get_irn_n(node, 3);
+ if(is_ia32_Immediate(right_op)) {
+ emit_ia32_Immediate(env, right_op);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 2);
break;
- case ia32_AddrModeS:
- ia32_emit_am(env, node);
+ } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
+ ia32_emit_immediate(env, node);
be_emit_cstring(env, ", ");
- if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
- assert(!produces_result(node) && "Source AM with Const must not produce result");
- ia32_emit_immediate(env, node);
- } else if (produces_result(node)) {
- ia32_emit_dest_register(env, node, 0);
- } else {
- ia32_emit_source_register(env, node, 2);
+ ia32_emit_source_register(env, node, 2);
+ } else {
+ const arch_register_t *in1 = get_in_reg(env, node, 2);
+ const arch_register_t *in2 = get_in_reg(env, node, 3);
+ const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
+ const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
+
+ if (is_ia32_emit_cl(node)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
+ in_name = "cl";
}
- break;
- case ia32_AddrModeD:
- if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
- ia32_emit_immediate(env, node);
- be_emit_cstring(env, ", ");
- ia32_emit_am(env, node);
- } else {
- const arch_register_t *in1 = get_in_reg(env, node,
- get_irn_arity(node) == 5 ? 3 : 2);
- ir_mode *mode = get_ia32_ls_mode(node);
- const char *in_name;
- in_name = ia32_get_reg_name_for_mode(env, mode, in1);
+ be_emit_char(env, '%');
+ be_emit_string(env, in_name);
+ be_emit_cstring(env, ", %");
+ be_emit_string(env, arch_register_get_name(out));
+ }
+ break;
+ case ia32_AddrModeS:
+ ia32_emit_am(env, node);
+ be_emit_cstring(env, ", ");
+ if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
+ assert(!produces_result(node) && "Source AM with Const must not produce result");
+ ia32_emit_immediate(env, node);
+ } else if (produces_result(node)) {
+ ia32_emit_dest_register(env, node, 0);
+ } else {
+ ia32_emit_source_register(env, node, 2);
+ }
+ break;
+ case ia32_AddrModeD:
+ right_pos = get_irn_arity(node) == 5 ? 3 : 2;
+ right_op = get_irn_n(node, right_pos);
+ if(is_ia32_Immediate(right_op)) {
+ emit_ia32_Immediate(env, right_op);
+ be_emit_cstring(env, ", ");
+ ia32_emit_am(env, node);
+ break;
+ } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
+ ia32_emit_immediate(env, node);
+ be_emit_cstring(env, ", ");
+ ia32_emit_am(env, node);
+ } else {
+ const arch_register_t *in1 = get_in_reg(env, node, right_pos);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ const char *in_name;
- if (is_ia32_emit_cl(node)) {
- assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
- in_name = "cl";
- }
+ in_name = ia32_get_reg_name_for_mode(env, mode, in1);
- be_emit_char(env, '%');
- be_emit_string(env, in_name);
- be_emit_cstring(env, ", ");
- ia32_emit_am(env, node);
+ if (is_ia32_emit_cl(node)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
+ in_name = "cl";
}
- break;
- default:
- assert(0 && "unsupported op type");
+
+ be_emit_char(env, '%');
+ be_emit_string(env, in_name);
+ be_emit_cstring(env, ", ");
+ ia32_emit_am(env, node);
+ }
+ break;
+ default:
+ assert(0 && "unsupported op type");
}
}
// should not happen...
assert(0);
} else {
- ia32_attr_t *attr = get_ia32_attr(node);
- const arch_register_t *in1 = attr->x87[0];
- const arch_register_t *in2 = attr->x87[1];
- const arch_register_t *out = attr->x87[2];
+ const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
+ const arch_register_t *in1 = x87_attr->x87[0];
+ const arch_register_t *in2 = x87_attr->x87[1];
+ const arch_register_t *out = x87_attr->x87[2];
const arch_register_t *in;
in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
}
}
+void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
+ int pos) {
+ if(get_ia32_op_type(node) == ia32_Normal) {
+ ia32_emit_dest_register(env, node, pos);
+ } else {
+ assert(get_ia32_op_type(node) == ia32_AddrModeD);
+ ia32_emit_am(env, node);
+ }
+}
+
/**
* Emits registers and/or address mode of a unary operation.
*/
-void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
+void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
+ const ir_node *op;
+
switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
- ia32_emit_immediate(env, node);
- } else {
- if (is_ia32_Mul(node) || is_ia32_IMul1OP(node)) {
- ia32_emit_source_register(env, node, 3);
- } else if(is_ia32_IDiv(node) || is_ia32_Div(node)) {
- ia32_emit_source_register(env, node, 4);
- } else if(is_ia32_Push(node)) {
- ia32_emit_source_register(env, node, 2);
- } else if(is_ia32_Pop(node)) {
- ia32_emit_dest_register(env, node, 1);
- } else {
- ia32_emit_dest_register(env, node, 0);
- }
- }
- break;
- case ia32_AddrModeS:
- case ia32_AddrModeD:
- ia32_emit_am(env, node);
- break;
- default:
- assert(0 && "unsupported op type");
+ case ia32_Normal:
+ op = get_irn_n(node, pos);
+ if (is_ia32_Immediate(op)) {
+ emit_ia32_Immediate(env, op);
+ } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
+ ia32_emit_immediate(env, node);
+ } else {
+ ia32_emit_source_register(env, node, pos);
+ }
+ break;
+ case ia32_AddrModeS:
+ case ia32_AddrModeD:
+ ia32_emit_am(env, node);
+ break;
+ default:
+ assert(0 && "unsupported op type");
}
}
* Emits address mode.
*/
void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
- ia32_am_flavour_t am_flav = get_ia32_am_flavour(node);
- ir_entity *ent = get_ia32_am_sc(node);
- int offs = get_ia32_am_offs_int(node);
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
+ ir_node *base = get_irn_n(node, 0);
+ int has_base = !is_ia32_NoReg_GP(base);
+ ir_node *index = get_irn_n(node, 1);
+ int has_index = !is_ia32_NoReg_GP(index);
/* just to be sure... */
assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
if (ent != NULL) {
ident *id;
- mark_entity_visited(ent);
+ set_entity_backend_marked(ent, 1);
id = get_entity_ld_ident(ent);
if (is_ia32_am_sc_sign(node))
be_emit_char(env, '-');
}
}
- if (am_flav & (ia32_B | ia32_I)) {
+ if (has_base || has_index) {
be_emit_char(env, '(');
/* emit base */
- if (am_flav & ia32_B) {
+ if (has_base) {
ia32_emit_source_register(env, node, 0);
}
/* emit index + scale */
- if (am_flav & ia32_I) {
+ if (has_index) {
+ int scale;
be_emit_char(env, ',');
ia32_emit_source_register(env, node, 1);
- if (am_flav & ia32_S) {
+ scale = get_ia32_am_scale(node);
+ if (scale > 0) {
be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
}
}
* returns the condition code
*/
static
-const char *get_cmp_suffix(int cmp_code)
+const char *get_cmp_suffix(pn_Cmp cmp_code)
{
assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
return get_irn_link(irn);
}
+/**
+ * Emits a block label for the given block.
+ */
static
void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
{
}
/**
- * Returns the target label for a control flow node.
+ * Emits the target label for a control flow node.
*/
static
void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
*/
static
void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
- if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
- be_emit_cstring(env, "\ttest ");
- ia32_emit_immediate(env, node);
- be_emit_cstring(env, ", ");
- ia32_emit_source_register(env, node, 0);
- be_emit_finish_line_gas(env, node);
- } else {
- be_emit_cstring(env, "\ttest ");
- ia32_emit_source_register(env, node, 1);
- be_emit_cstring(env, ", ");
- ia32_emit_source_register(env, node, 0);
- be_emit_finish_line_gas(env, node);
- }
+ be_emit_cstring(env, "\ttest ");
+ ia32_emit_binop(env, node);
+ be_emit_finish_line_gas(env, node);
+
finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
}
*/
static
void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
- ia32_attr_t *attr = get_ia32_attr(node);
- const char *reg = attr->x87[1]->name;
- long pnc = get_ia32_pncode(node);
+ const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
+ const char *reg = x87_attr->x87[1]->name;
+ long pnc = get_ia32_pncode(node);
switch (get_ia32_irn_opcode(node)) {
case iro_ia32_fcomrJmp:
pnc = get_inversed_pnc(pnc);
- reg = attr->x87[0]->name;
+ reg = x87_attr->x87[0]->name;
case iro_ia32_fcomJmp:
default:
be_emit_cstring(env, "\tfucom ");
break;
case iro_ia32_fcomrpJmp:
pnc = get_inversed_pnc(pnc);
- reg = attr->x87[0]->name;
+ reg = x87_attr->x87[0]->name;
case iro_ia32_fcompJmp:
be_emit_cstring(env, "\tfucomp ");
break;
}
static
-void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
+void emit_register_or_immediate(ia32_emit_env_t *env, const ir_node *node,
+ int pos)
+{
+ ir_node *op = get_irn_n(node, pos);
+ if(is_ia32_Immediate(op)) {
+ emit_ia32_Immediate(env, op);
+ } else {
+ ia32_emit_source_register(env, node, pos);
+ }
+}
+
+static
+int is_ia32_Immediate_0(const ir_node *node)
+{
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
+
+ return attr->offset == 0 && attr->symconst == NULL;
+}
+
+static
+void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
+{
long pnc = get_ia32_pncode(node);
- int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
- int idx_left = 2 - is_PsiCondCMov;
- int idx_right = 3 - is_PsiCondCMov;
const arch_register_t *in1, *in2, *out;
out = arch_get_irn_register(env->arch_env, node);
- in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
- in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
+ in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
+ in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
/* we have to emit the cmp first, because the destination register */
/* could be one of the compare registers */
if (is_ia32_CmpCMov(node)) {
- be_emit_cstring(env, "\tcmp ");
- ia32_emit_source_register(env, node, 1);
- be_emit_cstring(env, ", ");
- ia32_emit_source_register(env, node, 0);
+ long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
+ ir_node *cmp_right = get_irn_n(node, 1);
+
+ if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
+ && is_ia32_Immediate(cmp_right)
+ && is_ia32_Immediate_0(cmp_right)) {
+ be_emit_cstring(env, "\ttest ");
+ ia32_emit_source_register(env, node, 0);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ } else {
+ be_emit_cstring(env, "\tcmp ");
+ emit_register_or_immediate(env, node, 1);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ }
} else if (is_ia32_xCmpCMov(node)) {
be_emit_cstring(env, "\tucomis");
- ia32_emit_mode_suffix(env, get_irn_mode(node));
+ ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
be_emit_char(env, ' ');
ia32_emit_source_register(env, node, 1);
be_emit_cstring(env, ", ");
ia32_emit_source_register(env, node, 0);
- } else if (is_PsiCondCMov) {
- /* omit compare because flags are already set by And/Or */
- be_emit_cstring(env, "\ttest ");
- ia32_emit_source_register(env, node, 0);
- be_emit_cstring(env, ", ");
- ia32_emit_source_register(env, node, 0);
} else {
assert(0 && "unsupported CMov");
}
} else if (REGS_ARE_EQUAL(out, in1)) {
ir_node *n = (ir_node*) node;
/* true in == out -> need complement compare and exchange true and default in */
- ir_node *t = get_irn_n(n, idx_left);
- set_irn_n(n, idx_left, get_irn_n(n, idx_right));
- set_irn_n(n, idx_right, t);
+ ir_node *t = get_irn_n(n, 2);
+ set_irn_n(n, 2, get_irn_n(n, 3));
+ set_irn_n(n, 3, t);
pnc = get_negated_pnc(pnc, get_irn_mode(node));
} else {
/* out is different from in: need copy default -> out */
- if (is_PsiCondCMov) {
- be_emit_cstring(env, "\tmovl ");
- ia32_emit_dest_register(env, node, 2);
- be_emit_cstring(env, ", ");
- ia32_emit_dest_register(env, node, 0);
- } else {
- be_emit_cstring(env, "\tmovl ");
- ia32_emit_source_register(env, node, 3);
- be_emit_cstring(env, ", ");
- ia32_emit_dest_register(env, node, 0);
- }
- be_emit_finish_line_gas(env, node);
- }
-
- if (is_PsiCondCMov) {
- be_emit_cstring(env, "\tcmov");
- ia32_emit_cmp_suffix(env, pnc);
- be_emit_cstring(env, "l ");
- ia32_emit_source_register(env, node, 1);
- be_emit_cstring(env, ", ");
- ia32_emit_dest_register(env, node, 0);
- } else {
- be_emit_cstring(env, "\tcmov");
- ia32_emit_cmp_suffix(env, pnc);
- be_emit_cstring(env, "l ");
- ia32_emit_source_register(env, node, 2);
+ be_emit_cstring(env, "\tmovl ");
+ ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_false);
be_emit_cstring(env, ", ");
ia32_emit_dest_register(env, node, 0);
+ be_emit_finish_line_gas(env, node);
}
- be_emit_finish_line_gas(env, node);
-}
-static
-void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
- CMov_emitter(env, node);
+ be_emit_cstring(env, "\tcmov");
+ ia32_emit_cmp_suffix(env, pnc);
+ be_emit_cstring(env, "l ");
+ ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_true);
+ be_emit_cstring(env, ", ");
+ ia32_emit_dest_register(env, node, 0);
+ be_emit_finish_line_gas(env, node);
}
static
-void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
+void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
+{
CMov_emitter(env, node);
}
static
-void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
+void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
+{
CMov_emitter(env, node);
}
static
-void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
- int pnc = get_ia32_pncode(node);
+void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
+{
+ long pnc = get_ia32_pncode(node);
const char *reg8bit;
const arch_register_t *out;
reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
if (is_ia32_CmpSet(node)) {
- be_emit_cstring(env, "\tcmp ");
- ia32_emit_binop(env, node);
+ long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
+ ir_node *cmp_right = get_irn_n(node, n_ia32_CmpSet_cmp_right);
+
+ if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
+ && is_ia32_Immediate(cmp_right)
+ && is_ia32_Immediate_0(cmp_right)) {
+ be_emit_cstring(env, "\ttest ");
+ ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
+ } else {
+ be_emit_cstring(env, "\tcmp ");
+ ia32_emit_binop(env, node);
+ }
} else if (is_ia32_xCmpSet(node)) {
be_emit_cstring(env, "\tucomis");
- ia32_emit_mode_suffix(env, get_irn_mode(get_irn_n(node, 2)));
+ ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
be_emit_char(env, ' ');
ia32_emit_binop(env, node);
- } else if (is_ia32_PsiCondSet(node)) {
- be_emit_cstring(env, "\tcmp $0, ");
- ia32_emit_source_register(env, node, 0);
} else {
assert(0 && "unsupported Set");
}
static
void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
- Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
-}
-
-static
-void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
- Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
+ Set_emitter(env, node);
}
static
void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
- Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
+ Set_emitter(env, node);
}
static
/* jump table for switch generation */
typedef struct _jmp_tbl_t {
ir_node *defProj; /**< default target */
- int min_value; /**< smallest switch case */
- int max_value; /**< largest switch case */
- int num_branches; /**< number of jumps */
+ long min_value; /**< smallest switch case */
+ long max_value; /**< largest switch case */
+ long num_branches; /**< number of jumps */
char *label; /**< label of the jump table */
branch_t *branches; /**< jump array */
} jmp_tbl_t;
be_emit_finish_line_gas(env, node);
}
+static
+void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
+{
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
+
+ be_emit_char(env, '$');
+ if(attr->symconst != NULL) {
+ ident *id = get_entity_ld_ident(attr->symconst);
+
+ if(attr->attr.data.am_sc_sign)
+ be_emit_char(env, '-');
+ be_emit_ident(env, id);
+ }
+ if(attr->symconst == NULL || attr->offset != 0) {
+ if(attr->symconst != NULL)
+ be_emit_char(env, '+');
+ be_emit_irprintf(env->emit, "%d", attr->offset);
+ }
+}
+
+static
+const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
+ const char *s)
+{
+ const arch_register_t *reg;
+ const char *reg_name;
+ char c;
+ char modifier = 0;
+ int num = -1;
+ const ia32_attr_t *attr;
+ int n_outs;
+ int p;
+
+ assert(*s == '%');
+ c = *(++s);
+
+ /* parse modifiers */
+ switch(c) {
+ case 0:
+ ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
+ be_emit_char(env, '%');
+ return s + 1;
+ case '%':
+ be_emit_char(env, '%');
+ return s + 1;
+ case 'w':
+ case 'b':
+ case 'h':
+ modifier = c;
+ ++s;
+ break;
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ break;
+ default:
+ ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
+ "'%c' for asm op\n", node, c);
+ ++s;
+ break;
+ }
+
+ /* parse number */
+ sscanf(s, "%d%n", &num, &p);
+ if(num < 0) {
+ ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
+ node);
+ return s;
+ } else {
+ s += p;
+ }
+
+ /* get register */
+ attr = get_ia32_attr_const(node);
+ n_outs = ARR_LEN(attr->slots);
+ if(num < n_outs) {
+ reg = get_out_reg(env, node, num);
+ } else {
+ ir_node *pred;
+ int in = num - n_outs;
+ if(in >= get_irn_arity(node)) {
+ ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
+ "op (%+F)\n", num, node);
+ return s;
+ }
+ pred = get_irn_n(node, in);
+ /* might be an immediate value */
+ if(is_ia32_Immediate(pred)) {
+ emit_ia32_Immediate(env, pred);
+ return s;
+ }
+ reg = get_in_reg(env, node, in);
+ }
+ if(reg == NULL) {
+ ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
+ "(%+F)\n", num, node);
+ return s;
+ }
+
+ /* emit it */
+ be_emit_char(env, '%');
+ switch(modifier) {
+ case 0:
+ reg_name = arch_register_get_name(reg);
+ break;
+ case 'b':
+ reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
+ break;
+ case 'h':
+ reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
+ break;
+ case 'w':
+ reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
+ break;
+ default:
+ panic("Invalid asm op modifier");
+ }
+ be_emit_string(env, reg_name);
+
+ return s;
+}
+
+/**
+ * Emits code for an ASM pseudo op.
+ */
+static
+void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
+{
+ const void *gen_attr = get_irn_generic_attr_const(node);
+ const ia32_asm_attr_t *attr
+ = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
+ ident *asm_text = attr->asm_text;
+ const char *s = get_id_str(asm_text);
+
+ be_emit_cstring(env, "# Begin ASM \t");
+ be_emit_finish_line_gas(env, node);
+
+ if (s[0] != '\t')
+ be_emit_char(env, '\t');
+
+ while(*s != 0) {
+ if(*s == '%') {
+ s = emit_asm_operand(env, node, s);
+ continue;
+ } else {
+ be_emit_char(env, *s);
+ }
+ ++s;
+ }
+
+ be_emit_char(env, '\n');
+ be_emit_write_line(env);
+
+ be_emit_cstring(env, "# End ASM\n");
+ be_emit_write_line(env);
+}
+
/**********************************
* _____ ____
* / ____| | _ \
if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
REGS_ARE_EQUAL(out_reg, in_reg) &&
- signed_mode)
+ signed_mode &&
+ smaller_bits == 16)
{
/* argument and result are both in EAX and */
- /* signedness is ok: -> use converts */
- if (smaller_bits == 8) {
- be_emit_cstring(env, "\tcbtw");
- } else if (smaller_bits == 16) {
- be_emit_cstring(env, "\tcwtl");
- } else {
- assert(0);
- }
- } else if (REGS_ARE_EQUAL(out_reg, in_reg) && !signed_mode) {
- /* argument and result are in the same register */
- /* and signedness is ok: -> use and with mask */
- int mask = (1 << smaller_bits) - 1;
- be_emit_cstring(env, "\tandl $0x");
- be_emit_irprintf(env->emit, "%x, ", mask);
- ia32_emit_dest_register(env, node, 0);
+ /* signedness is ok: -> use the smaller cwtl opcode */
+ be_emit_cstring(env, "\tcwtl");
} else {
const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
be_emit_cstring(env, "\tmov");
be_emit_string(env, sign_suffix);
- ia32_emit_mode_suffix(env, smaller_mode);
+ ia32_emit_mode_suffix_mode(env, smaller_mode);
be_emit_cstring(env, "l %");
be_emit_string(env, sreg);
be_emit_cstring(env, ", ");
case ia32_AddrModeS: {
be_emit_cstring(env, "\tmov");
be_emit_string(env, sign_suffix);
- ia32_emit_mode_suffix(env, smaller_mode);
+ ia32_emit_mode_suffix_mode(env, smaller_mode);
be_emit_cstring(env, "l %");
ia32_emit_am(env, node);
be_emit_cstring(env, ", ");
be_emit_cstring(env, "\tcall ");
if (ent) {
- mark_entity_visited(ent);
+ set_entity_backend_marked(ent, 1);
be_emit_string(env, get_entity_ld_name(ent));
} else {
be_emit_char(env, '*');
}
static
-void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
+void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
+{
be_emit_cstring(env, "\tret");
be_emit_finish_line_gas(env, node);
}
static
-void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
+void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
+{
+ (void) env;
+ (void) node;
}
ia32_register_spec_emitters();
/* other ia32 emitter functions */
+ IA32_EMIT(Asm);
IA32_EMIT(CondJmp);
IA32_EMIT(TestJmp);
IA32_EMIT(CJmp);
IA32_EMIT(CJmpAM);
IA32_EMIT(CmpCMov);
- IA32_EMIT(PsiCondCMov);
IA32_EMIT(CmpSet);
- IA32_EMIT(PsiCondSet);
IA32_EMIT(SwitchJmp);
IA32_EMIT(CopyB);
IA32_EMIT(CopyB_i);
ir_node *pred_block = get_nodes_block(pred);
/* we don't need labels for fallthrough blocks, however switch-jmps
- * are no fallthoughs */
+ * are no fallthroughs */
if(pred_block == prev &&
!(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
need_label = 0;
ir_node *predblock = get_Block_cfgpred_block(block, i);
be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
}
-
- if (exec_freq != NULL) {
- be_emit_irprintf(env->emit, " freq: %f",
- get_block_execfreq(exec_freq, block));
- }
- be_emit_cstring(env, " */\n");
} else {
be_emit_cstring(env, "\t/* ");
ia32_emit_block_name(env, block);
- be_emit_cstring(env, ": */\n");
+ be_emit_cstring(env, ": ");
+ }
+ if (exec_freq != NULL) {
+ be_emit_irprintf(env->emit, " freq: %f",
+ get_block_execfreq(exec_freq, block));
}
+ be_emit_cstring(env, " */\n");
be_emit_write_line(env);
}
* Sets labels for control flow nodes (jump target)
*/
static
-void ia32_gen_labels(ir_node *block, void *data) {
+void ia32_gen_labels(ir_node *block, void *data)
+{
ir_node *pred;
int n = get_Block_n_cfgpreds(block);
+ (void) data;
for (n--; n >= 0; n--) {
pred = get_Block_cfgpred(block, n);
}
}
+/**
+ * Emit an exception label if the current instruction can fail.
+ */
+void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
+ if (get_ia32_exc_label(node)) {
+ be_emit_irprintf(env->emit, ".EXL%u\n", 0);
+ be_emit_write_line(env);
+ }
+}
+
/**
* Main driver. Emits the code for one routine.
*/
projects / libfirm / blobdiff