/*
- * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
- *
* This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
*/
/**
* @file
* @brief This file implements the ia32 node emitter.
* @author Christian Wuerdig, Matthias Braun
- * @version $Id$
*
* Summary table for x86 floatingpoint compares:
+ * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
+ *
* pnc_Eq => !P && E
* pnc_Lt => !P && B
* pnc_Le => !P && BE
* pnc_Gt => A
* pnc_Ge => AE
- * pnc_Lg => P || NE
+ * pnc_Lg => NE
* pnc_Leg => NP (ordered)
* pnc_Uo => P
* pnc_Ue => E
* pnc_Ule => BE
* pnc_Ug => P || A
* pnc_Uge => P || AE
- * pnc_Ne => NE
+ * pnc_Ne => P || NE
*/
#include "config.h"
#include "raw_bitset.h"
#include "dbginfo.h"
#include "lc_opts.h"
+#include "ircons.h"
-#include "../besched.h"
-#include "../benode.h"
-#include "../beabi.h"
-#include "../be_dbgout.h"
-#include "../beemitter.h"
-#include "../begnuas.h"
-#include "../beirg.h"
-#include "../be_dbgout.h"
+#include "besched.h"
+#include "benode.h"
+#include "beabi.h"
+#include "bedwarf.h"
+#include "beemitter.h"
+#include "begnuas.h"
+#include "beutil.h"
#include "ia32_emitter.h"
+#include "ia32_common_transform.h"
#include "gen_ia32_emitter.h"
#include "gen_ia32_regalloc_if.h"
#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
-#include "ia32_map_regs.h"
#include "ia32_architecture.h"
#include "bearch_ia32_t.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-#define SNPRINTF_BUF_LEN 128
-
static const ia32_isa_t *isa;
-static ia32_code_gen_t *cg;
static char pic_base_label[128];
static ir_label_t exc_label_id;
static int mark_spill_reload = 0;
static int do_pic;
+static bool sp_relative;
+static int frame_type_size;
+static int callframe_offset;
+
/** Return the next block in Block schedule */
static ir_node *get_prev_block_sched(const ir_node *block)
{
- return get_irn_link(block);
+ return (ir_node*)get_irn_link(block);
}
/** Checks if the current block is a fall-through target. */
int need_label = 1;
int n_cfgpreds = get_Block_n_cfgpreds(block);
- if (has_Block_entity(block))
+ if (get_Block_entity(block) != NULL)
return 1;
if (n_cfgpreds == 0) {
return need_label;
}
-/**
- * Returns the register at in position pos.
- */
-static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
-{
- ir_node *op;
- const arch_register_t *reg = NULL;
-
- assert(get_irn_arity(irn) > pos && "Invalid IN position");
-
- /* The out register of the operator at position pos is the
- in register we need. */
- op = get_irn_n(irn, pos);
-
- reg = arch_get_irn_register(op);
-
- assert(reg && "no in register found");
-
- if (reg == &ia32_gp_regs[REG_GP_NOREG])
- panic("trying to emit noreg for %+F input %d", irn, pos);
-
- /* in case of unknown register: just return a valid register */
- if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
- const arch_register_req_t *req = arch_get_register_req(irn, pos);
-
- if (arch_register_req_is(req, limited)) {
- /* in case of limited requirements: get the first allowed register */
- unsigned idx = rbitset_next(req->limited, 0, 1);
- reg = arch_register_for_index(req->cls, idx);
- } else {
- /* otherwise get first register in class */
- reg = arch_register_for_index(req->cls, 0);
- }
- }
-
- return reg;
-}
-
-/**
- * Returns the register at out position pos.
- */
-static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
-{
- ir_node *proj;
- const arch_register_t *reg = NULL;
-
- /* 1st case: irn is not of mode_T, so it has only */
- /* one OUT register -> good */
- /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
- /* Proj with the corresponding projnum for the register */
-
- if (get_irn_mode(irn) != mode_T) {
- assert(pos == 0);
- reg = arch_get_irn_register(irn);
- } else if (is_ia32_irn(irn)) {
- reg = arch_irn_get_register(irn, pos);
- } else {
- const ir_edge_t *edge;
-
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "non-Proj from mode_T node");
- if (get_Proj_proj(proj) == pos) {
- reg = arch_get_irn_register(proj);
- break;
- }
- }
- }
-
- assert(reg && "no out register found");
- return reg;
-}
-
/**
* Add a number to a prefix. This number will not be used a second time.
*/
static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
{
static unsigned long id = 0;
- snprintf(buf, buflen, "%s%lu", prefix, ++id);
+ snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
return buf;
}
-/*************************************************************
- * _ _ __ _ _
- * (_) | | / _| | | | |
- * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
- * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
- * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
- * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
- * | | | |
- * |_| |_|
- *************************************************************/
-
/**
* Emit the name of the 8bit low register
*/
static void emit_8bit_register(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
+ assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
+ || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
- be_emit_char(reg_name[1]);
+ be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('l');
}
*/
static void emit_8bit_register_high(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
+ assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
+ || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
- be_emit_char(reg_name[1]);
+ be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('h');
}
static void emit_16bit_register(const arch_register_t *reg)
{
- const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
-
be_emit_char('%');
- be_emit_string(reg_name);
+ be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
}
/**
*/
static void emit_register(const arch_register_t *reg, const ir_mode *mode)
{
- const char *reg_name;
-
if (mode != NULL) {
int size = get_mode_size_bits(mode);
switch (size) {
assert(mode_is_float(mode) || size == 32);
}
- reg_name = arch_register_get_name(reg);
-
be_emit_char('%');
- be_emit_string(reg_name);
-}
-
-void ia32_emit_source_register(const ir_node *node, int pos)
-{
- const arch_register_t *reg = get_in_reg(node, pos);
-
- emit_register(reg, NULL);
+ be_emit_string(reg->name);
}
static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
be_gas_emit_entity(entity);
if (get_entity_owner(entity) == get_tls_type()) {
- if (get_entity_visibility(entity) == ir_visibility_external) {
+ if (!entity_has_definition(entity)) {
be_emit_cstring("@INDNTPOFF");
} else {
be_emit_cstring("@NTPOFF");
emit_ia32_Immediate_no_prefix(node);
}
-void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
-{
- const arch_register_t *reg;
- const ir_node *in = get_irn_n(node, pos);
- if (is_ia32_Immediate(in)) {
- emit_ia32_Immediate(in);
- return;
- }
-
- reg = get_in_reg(node, pos);
- emit_8bit_register(reg);
-}
-
-void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
-{
- const arch_register_t *reg = get_in_reg(node, pos);
- emit_8bit_register_high(reg);
-}
-
-void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
-{
- const arch_register_t *reg;
- const ir_node *in = get_irn_n(node, pos);
- if (is_ia32_Immediate(in)) {
- emit_ia32_Immediate(in);
- return;
- }
-
- reg = get_in_reg(node, pos);
- emit_16bit_register(reg);
-}
-
-void ia32_emit_dest_register(const ir_node *node, int pos)
-{
- const arch_register_t *reg = get_out_reg(node, pos);
-
- emit_register(reg, NULL);
-}
-
-void ia32_emit_dest_register_size(const ir_node *node, int pos)
-{
- const arch_register_t *reg = get_out_reg(node, pos);
-
- emit_register(reg, get_ia32_ls_mode(node));
-}
-
-void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
-{
- const arch_register_t *reg = get_out_reg(node, pos);
-
- emit_register(reg, mode_Bu);
-}
-
-void ia32_emit_x87_register(const ir_node *node, int pos)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
-
- assert(pos < 3);
- be_emit_char('%');
- be_emit_string(attr->x87[pos]->name);
-}
-
static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
{
assert(mode_is_int(mode) || mode_is_reference(mode));
panic("Can't output mode_suffix for %+F", mode);
}
-void ia32_emit_mode_suffix(const ir_node *node)
-{
- ir_mode *mode = get_ia32_ls_mode(node);
- if (mode == NULL)
- mode = mode_Iu;
-
- ia32_emit_mode_suffix_mode(mode);
-}
-
-void ia32_emit_x87_mode_suffix(const ir_node *node)
+static void ia32_emit_x87_mode_suffix(ir_node const *const node)
{
ir_mode *mode;
case 128: be_emit_char('t'); return;
}
} else {
- assert(mode_is_int(mode));
+ assert(mode_is_int(mode) || mode_is_reference(mode));
switch (get_mode_size_bits(mode)) {
case 16: be_emit_char('s'); return;
case 32: be_emit_char('l'); return;
static char get_xmm_mode_suffix(ir_mode *mode)
{
assert(mode_is_float(mode));
- switch(get_mode_size_bits(mode)) {
+ switch (get_mode_size_bits(mode)) {
case 32: return 's';
case 64: return 'd';
default: panic("Invalid XMM mode");
}
}
-void ia32_emit_xmm_mode_suffix(const ir_node *node)
+static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
{
ir_mode *mode = get_ia32_ls_mode(node);
assert(mode != NULL);
- be_emit_char('s');
be_emit_char(get_xmm_mode_suffix(mode));
}
-void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
-{
- ir_mode *mode = get_ia32_ls_mode(node);
- assert(mode != NULL);
- be_emit_char(get_xmm_mode_suffix(mode));
-}
-
-void ia32_emit_extend_suffix(const ir_node *node)
-{
- ir_mode *mode = get_ia32_ls_mode(node);
- if (get_mode_size_bits(mode) == 32)
- return;
- be_emit_char(mode_is_signed(mode) ? 's' : 'z');
- ia32_emit_mode_suffix_mode(mode);
-}
-
-void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
-{
- ir_node *in = get_irn_n(node, pos);
- if (is_ia32_Immediate(in)) {
- emit_ia32_Immediate(in);
- } else {
- const ir_mode *mode = get_ia32_ls_mode(node);
- const arch_register_t *reg = get_in_reg(node, pos);
- emit_register(reg, mode);
- }
-}
-
/**
* Returns the target block for a control flow node.
*/
static ir_node *get_cfop_target_block(const ir_node *irn)
{
assert(get_irn_mode(irn) == mode_X);
- return get_irn_link(irn);
+ return (ir_node*)get_irn_link(irn);
}
/**
be_gas_emit_block_name(block);
}
-/*
- * positive conditions for signed compares
- */
-static const char *const cmp2condition_s[] = {
- NULL, /* always false */
- "e", /* == */
- "l", /* < */
- "le", /* <= */
- "g", /* > */
- "ge", /* >= */
- "ne", /* != */
- NULL /* always true */
-};
-
-/*
- * positive conditions for unsigned compares
- */
-static const char *const cmp2condition_u[] = {
- NULL, /* always false */
- "e", /* == */
- "b", /* < */
- "be", /* <= */
- "a", /* > */
- "ae", /* >= */
- "ne", /* != */
- NULL /* always true */
-};
-
/**
* Emit the suffix for a compare instruction.
*/
-static void ia32_emit_cmp_suffix(int pnc)
-{
- const char *str;
-
- if (pnc == ia32_pn_Cmp_parity) {
- be_emit_char('p');
- return;
- }
-
- if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
- str = cmp2condition_u[pnc & 7];
- } else {
- str = cmp2condition_s[pnc & 7];
+static void ia32_emit_condition_code(ia32_condition_code_t cc)
+{
+ switch (cc) {
+ case ia32_cc_overflow: be_emit_cstring("o"); return;
+ case ia32_cc_not_overflow: be_emit_cstring("no"); return;
+ case ia32_cc_float_below:
+ case ia32_cc_float_unordered_below:
+ case ia32_cc_below: be_emit_cstring("b"); return;
+ case ia32_cc_float_above_equal:
+ case ia32_cc_float_unordered_above_equal:
+ case ia32_cc_above_equal: be_emit_cstring("ae"); return;
+ case ia32_cc_float_equal:
+ case ia32_cc_equal: be_emit_cstring("e"); return;
+ case ia32_cc_float_not_equal:
+ case ia32_cc_not_equal: be_emit_cstring("ne"); return;
+ case ia32_cc_float_below_equal:
+ case ia32_cc_float_unordered_below_equal:
+ case ia32_cc_below_equal: be_emit_cstring("be"); return;
+ case ia32_cc_float_above:
+ case ia32_cc_float_unordered_above:
+ case ia32_cc_above: be_emit_cstring("a"); return;
+ case ia32_cc_sign: be_emit_cstring("s"); return;
+ case ia32_cc_not_sign: be_emit_cstring("ns"); return;
+ case ia32_cc_parity: be_emit_cstring("p"); return;
+ case ia32_cc_not_parity: be_emit_cstring("np"); return;
+ case ia32_cc_less: be_emit_cstring("l"); return;
+ case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
+ case ia32_cc_less_equal: be_emit_cstring("le"); return;
+ case ia32_cc_greater: be_emit_cstring("g"); return;
+ case ia32_cc_float_parity_cases:
+ case ia32_cc_additional_float_cases:
+ break;
}
-
- be_emit_string(str);
+ panic("Invalid ia32 condition code");
}
typedef enum ia32_emit_mod_t {
+ EMIT_NONE = 0,
EMIT_RESPECT_LS = 1U << 0,
EMIT_ALTERNATE_AM = 1U << 1,
EMIT_LONG = 1U << 2,
EMIT_HIGH_REG = 1U << 3,
- EMIT_LOW_REG = 1U << 4
+ EMIT_LOW_REG = 1U << 4,
+ EMIT_16BIT_REG = 1U << 5
} ia32_emit_mod_t;
+ENUM_BITSET(ia32_emit_mod_t)
/**
* Emits address mode.
*/
-void ia32_emit_am(const ir_node *node)
+static void ia32_emit_am(ir_node const *const node)
{
ir_entity *ent = get_ia32_am_sc(node);
int offs = get_ia32_am_offs_int(node);
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
/* just to be sure... */
assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
+ if (get_ia32_am_tls_segment(node))
+ be_emit_cstring("%gs:");
+
/* emit offset */
if (ent != NULL) {
const ia32_attr_t *attr = get_ia32_attr_const(node);
/* emit base */
if (has_base) {
- const arch_register_t *reg = get_in_reg(node, n_ia32_base);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
emit_register(reg, NULL);
}
/* emit index + scale */
if (has_index) {
- const arch_register_t *reg = get_in_reg(node, n_ia32_index);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
int scale;
be_emit_char(',');
emit_register(reg, NULL);
}
}
-/**
- * fmt parameter output
- * ---- ---------------------- ---------------------------------------------
- * %% %
- * %AM <node> address mode of the node
- * %AR const arch_register_t* address mode of the node or register
- * %ASx <node> address mode of the node or source register x
- * %Dx <node> destination register x
- * %I <node> immediate of the node
- * %L <node> control flow target of the node
- * %M <node> mode suffix of the node
- * %P int condition code
- * %R const arch_register_t* register
- * %Sx <node> source register x
- * %s const char* string
- * %u unsigned int unsigned int
- * %d signed int signed int
- *
- * x starts at 0
- * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
- * * modifier does not prefix immediates with $, but AM with *
- * l modifier for %lu and %ld
- * > modifier to output high 8bit register (ah, bh)
- * < modifier to output low 8bit register (al, bl)
- */
-static void ia32_emitf(const ir_node *node, const char *fmt, ...)
+static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
+
+void ia32_emitf(ir_node const *const node, char const *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
+ be_emit_char('\t');
for (;;) {
const char *start = fmt;
- ia32_emit_mod_t mod = 0;
+ ia32_emit_mod_t mod = EMIT_NONE;
while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
++fmt;
}
if (*fmt == '\n') {
- be_emit_finish_line_gas(node);
+ be_emit_char('\n');
+ be_emit_write_line();
+ be_emit_char('\t');
++fmt;
if (*fmt == '\0')
break;
break;
++fmt;
- while (1) {
- switch(*fmt) {
+ for (;;) {
+ switch (*fmt) {
case '*': mod |= EMIT_ALTERNATE_AM; break;
case '#': mod |= EMIT_RESPECT_LS; break;
case 'l': mod |= EMIT_LONG; break;
case '>': mod |= EMIT_HIGH_REG; break;
case '<': mod |= EMIT_LOW_REG; break;
+ case '^': mod |= EMIT_16BIT_REG; break;
default:
goto end_of_mods;
}
end_of_mods:
switch (*fmt++) {
+ arch_register_t const *reg;
+ ir_node const *imm;
+
case '%':
be_emit_char('%');
break;
case 'A': {
switch (*fmt++) {
+ case 'F':
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
+ be_emit_irprintf(fmt, attr->reg->name);
+ break;
+ } else {
+ goto emit_AM;
+ }
+
emit_AM:
case 'M':
if (mod & EMIT_ALTERNATE_AM)
ia32_emit_am(node);
break;
- case 'R': {
- const arch_register_t *reg = va_arg(ap, const arch_register_t*);
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- goto emit_AM;
+ case 'R':
+ reg = va_arg(ap, const arch_register_t*);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ goto emit_R;
} else {
- if (mod & EMIT_ALTERNATE_AM)
- be_emit_char('*');
- emit_register(reg, NULL);
+ goto emit_AM;
}
- break;
- }
case 'S':
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ goto emit_S;
+ } else {
++fmt;
goto emit_AM;
- } else {
- assert(get_ia32_op_type(node) == ia32_Normal);
- goto emit_S;
}
- break;
default: goto unknown;
}
break;
}
- case 'D': {
- unsigned pos;
- const arch_register_t *reg;
+ case 'B':
+ imm = get_irn_n(node, n_ia32_binary_right);
+ if (is_ia32_Immediate(imm)) {
+ emit_ia32_Immediate(imm);
+ be_emit_cstring(", ");
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ goto destination_operand;
+ } else {
+ ia32_emit_am(node);
+ }
+ } else {
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ reg = arch_get_irn_register_in(node, n_ia32_binary_right);
+ emit_register(reg, get_ia32_ls_mode(node));
+ } else {
+ ia32_emit_am(node);
+ }
+ be_emit_cstring(", ");
+destination_operand:
+ reg = arch_get_irn_register_in(node, n_ia32_binary_left);
+ emit_register(reg, get_ia32_ls_mode(node));
+ }
+ break;
- if (*fmt < '0' || '9' <= *fmt)
+ case 'D':
+ if (*fmt < '0' || '9' < *fmt)
goto unknown;
-
- pos = *fmt++ - '0';
- reg = get_out_reg(node, pos);
- emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
+ reg = arch_get_irn_register_out(node, *fmt++ - '0');
+ goto emit_R;
+
+ case 'F':
+ if (*fmt == 'M') {
+ ia32_emit_x87_mode_suffix(node);
+ } else if (*fmt == 'P') {
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ if (attr->pop)
+ be_emit_char('p');
+ } else if (*fmt == 'R') {
+ /* NOTE: Work around a gas quirk for non-commutative operations if the
+ * destination register is not %st0. In this case r/non-r is swapped.
+ * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
+ * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
+ * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
+ * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
+ * In fact this corresponds to the encoding of the instruction:
+ * - The r suffix selects whether %st0 is on the left (no r) or on the
+ * right (r) side of the executed operation.
+ * - The placement of %st0 selects whether the result is written to
+ * %st0 (right) or the other register (left).
+ * This means that it is sufficient to test whether the operands are
+ * permuted. In particular it is not necessary to consider wether the
+ * result is to be placed into the explicit register operand. */
+ if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
+ be_emit_char('r');
+ } else if (*fmt == 'X') {
+ ia32_emit_xmm_mode_suffix(node);
+ } else if (*fmt == '0') {
+ be_emit_char('%');
+ be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
+ } else {
+ goto unknown;
+ }
+ ++fmt;
break;
- }
case 'I':
+ imm = node;
+emit_I:
if (!(mod & EMIT_ALTERNATE_AM))
be_emit_char('$');
- emit_ia32_Immediate_no_prefix(node);
+ emit_ia32_Immediate_no_prefix(imm);
break;
case 'L':
break;
case 'M': {
- ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
+ ir_mode *mode = get_ia32_ls_mode(node);
+ if (!mode)
+ mode = mode_Iu;
+ if (mod & EMIT_RESPECT_LS) {
+ if (get_mode_size_bits(mode) == 32)
+ break;
+ be_emit_char(mode_is_signed(mode) ? 's' : 'z');
+ }
+ ia32_emit_mode_suffix_mode(mode);
break;
}
case 'P': {
- int pnc = va_arg(ap, int);
- ia32_emit_cmp_suffix(pnc);
+ ia32_condition_code_t cc;
+ if (*fmt == 'X') {
+ ++fmt;
+ cc = (ia32_condition_code_t)va_arg(ap, int);
+ } else if ('0' <= *fmt && *fmt <= '9') {
+ cc = get_ia32_condcode(node);
+ cc = determine_final_cc(node, *fmt - '0', cc);
+ ++fmt;
+ } else {
+ goto unknown;
+ }
+ ia32_emit_condition_code(cc);
break;
}
- case 'R': {
- const arch_register_t *reg = va_arg(ap, const arch_register_t*);
+ case 'R':
+ reg = va_arg(ap, const arch_register_t*);
+emit_R:
+ if (mod & EMIT_ALTERNATE_AM)
+ be_emit_char('*');
if (mod & EMIT_HIGH_REG) {
emit_8bit_register_high(reg);
} else if (mod & EMIT_LOW_REG) {
emit_8bit_register(reg);
+ } else if (mod & EMIT_16BIT_REG) {
+ emit_16bit_register(reg);
} else {
emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
}
break;
- }
emit_S:
case 'S': {
- unsigned pos;
- const ir_node *in;
+ unsigned pos;
- if (*fmt < '0' || '9' <= *fmt)
+ if (*fmt < '0' || '9' < *fmt)
goto unknown;
pos = *fmt++ - '0';
- in = get_irn_n(node, pos);
- if (is_ia32_Immediate(in)) {
- if (!(mod & EMIT_ALTERNATE_AM))
- be_emit_char('$');
- emit_ia32_Immediate_no_prefix(in);
+ imm = get_irn_n(node, pos);
+ if (is_ia32_Immediate(imm)) {
+ goto emit_I;
} else {
- const arch_register_t *reg;
-
- if (mod & EMIT_ALTERNATE_AM)
- be_emit_char('*');
- reg = get_in_reg(node, pos);
- emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
+ reg = arch_get_irn_register_in(node, pos);
+ goto emit_R;
}
- break;
}
case 's': {
default:
unknown:
- panic("unknown format conversion in ia32_emitf()");
+ panic("unknown format conversion");
}
}
+ be_emit_finish_line_gas(node);
va_end(ap);
}
-/**
- * Emits registers and/or address mode of a binary operation.
- */
-void ia32_emit_binop(const ir_node *node)
-{
- if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
- ia32_emitf(node, "%#S4, %#AS3");
- } else {
- ia32_emitf(node, "%#AS4, %#S3");
- }
-}
-
-/**
- * Emits registers and/or address mode of a binary operation.
- */
-void ia32_emit_x87_binop(const ir_node *node)
-{
- switch(get_ia32_op_type(node)) {
- case ia32_Normal:
- {
- const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
- const arch_register_t *in1 = x87_attr->x87[0];
- const arch_register_t *in = x87_attr->x87[1];
- const arch_register_t *out = x87_attr->x87[2];
-
- if (out == NULL) {
- out = in1;
- } else if (out == in) {
- in = in1;
- }
-
- be_emit_char('%');
- be_emit_string(arch_register_get_name(in));
- be_emit_cstring(", %");
- be_emit_string(arch_register_get_name(out));
- }
- break;
- case ia32_AddrModeS:
- ia32_emit_am(node);
- break;
- case ia32_AddrModeD:
- default:
- assert(0 && "unsupported op type");
- }
-}
-
-/**
- * Emits registers and/or address mode of a unary operation.
- */
-void ia32_emit_unop(const ir_node *node, int pos)
-{
- char fmt[] = "%ASx";
- fmt[3] = '0' + pos;
- ia32_emitf(node, fmt);
-}
-
static void emit_ia32_IMul(const ir_node *node)
{
ir_node *left = get_irn_n(node, n_ia32_IMul_left);
- const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
+ const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
/* do we need the 3-address form? */
if (is_ia32_NoReg_GP(left) ||
- get_in_reg(node, n_ia32_IMul_left) != out_reg) {
- ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
+ arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
+ ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
} else {
- ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
+ ia32_emitf(node, "imul%M %#AS4, %#S3");
}
}
return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
} else if (is_ia32_Load(pred)) {
return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
+ } else if (is_ia32_Store(pred)) {
+ return find_original_value(get_irn_n(pred, n_ia32_Store_val));
} else {
return node;
}
- } else if (is_ia32_Store(node)) {
- return find_original_value(get_irn_n(node, n_ia32_Store_val));
} else if (is_Phi(node)) {
int i, arity;
arity = get_irn_arity(node);
}
}
-static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
+static ia32_condition_code_t determine_final_cc(const ir_node *node,
+ int flags_pos, ia32_condition_code_t cc)
{
ir_node *flags = get_irn_n(node, flags_pos);
const ia32_attr_t *flags_attr;
if (is_ia32_Sahf(flags)) {
ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
- if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
- || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
+ if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
inc_irg_visited(current_ir_graph);
cmp = find_original_value(cmp);
assert(cmp != NULL);
- assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
- || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
+ assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
}
flags_attr = get_ia32_attr_const(cmp);
- if (flags_attr->data.ins_permuted)
- pnc = get_mirrored_pnc(pnc);
- pnc |= ia32_pn_Cmp_float;
- } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
- || is_ia32_Fucompi(flags)) {
- flags_attr = get_ia32_attr_const(flags);
-
- if (flags_attr->data.ins_permuted)
- pnc = get_mirrored_pnc(pnc);
- pnc |= ia32_pn_Cmp_float;
} else {
flags_attr = get_ia32_attr_const(flags);
-
- if (flags_attr->data.ins_permuted)
- pnc = get_mirrored_pnc(pnc);
- if (flags_attr->data.cmp_unsigned)
- pnc |= ia32_pn_Cmp_unsigned;
}
- return pnc;
-}
-
-static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
-{
- ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
- return get_negated_pnc(pnc, mode);
-}
-
-void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
-{
- pn_Cmp pnc = get_ia32_condcode(node);
- pnc = determine_final_pnc(node, flags_pos, pnc);
-
- ia32_emit_cmp_suffix(pnc);
+ if (flags_attr->data.ins_permuted)
+ cc = ia32_invert_condition_code(cc);
+ return cc;
}
/**
be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
}
-/**
- * Returns the Proj with projection number proj and NOT mode_M
- */
-static ir_node *get_proj(const ir_node *node, long proj)
-{
- const ir_edge_t *edge;
- ir_node *src;
-
- assert(get_irn_mode(node) == mode_T && "expected mode_T node");
-
- foreach_out_edge(node, edge) {
- src = get_edge_src_irn(edge);
-
- assert(is_Proj(src) && "Proj expected");
- if (get_irn_mode(src) == mode_M)
- continue;
-
- if (get_Proj_proj(src) == proj)
- return src;
- }
- return NULL;
-}
-
static int can_be_fallthrough(const ir_node *node)
{
ir_node *target_block = get_cfop_target_block(node);
*/
static void emit_ia32_Jcc(const ir_node *node)
{
- int need_parity_label = 0;
- const ir_node *proj_true;
- const ir_node *proj_false;
- const ir_node *block;
- pn_Cmp pnc = get_ia32_condcode(node);
+ int need_parity_label = 0;
+ ia32_condition_code_t cc = get_ia32_condcode(node);
- pnc = determine_final_pnc(node, 0, pnc);
+ cc = determine_final_cc(node, 0, cc);
/* get both Projs */
- proj_true = get_proj(node, pn_ia32_Jcc_true);
+ ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
assert(proj_true && "Jcc without true Proj");
- proj_false = get_proj(node, pn_ia32_Jcc_false);
+ ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
assert(proj_false && "Jcc without false Proj");
- block = get_nodes_block(node);
-
if (can_be_fallthrough(proj_true)) {
/* exchange both proj's so the second one can be omitted */
const ir_node *t = proj_true;
proj_true = proj_false;
proj_false = t;
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
}
- if (pnc & ia32_pn_Cmp_float) {
+ if (cc & ia32_cc_float_parity_cases) {
/* Some floating point comparisons require a test of the parity flag,
* which indicates that the result is unordered */
- switch (pnc & 0x0f) {
- case pn_Cmp_Uo: {
- ia32_emitf(proj_true, "\tjp %L\n");
- break;
- }
-
- case pn_Cmp_Leg:
- ia32_emitf(proj_true, "\tjnp %L\n");
- break;
-
- case pn_Cmp_Eq:
- case pn_Cmp_Lt:
- case pn_Cmp_Le:
+ if (cc & ia32_cc_negated) {
+ ia32_emitf(proj_true, "jp %L");
+ } else {
/* we need a local label if the false proj is a fallthrough
* as the falseblock might have no label emitted then */
if (can_be_fallthrough(proj_false)) {
need_parity_label = 1;
- ia32_emitf(proj_false, "\tjp 1f\n");
+ ia32_emitf(proj_false, "jp 1f");
} else {
- ia32_emitf(proj_false, "\tjp %L\n");
+ ia32_emitf(proj_false, "jp %L");
}
- goto emit_jcc;
-
- case pn_Cmp_Ug:
- case pn_Cmp_Uge:
- case pn_Cmp_Ne:
- ia32_emitf(proj_true, "\tjp %L\n");
- goto emit_jcc;
-
- default:
- goto emit_jcc;
}
- } else {
-emit_jcc:
- ia32_emitf(proj_true, "\tj%P %L\n", pnc);
}
-
+ ia32_emitf(proj_true, "j%PX %L", (int)cc);
if (need_parity_label) {
- ia32_emitf(NULL, "1:\n");
+ be_emit_cstring("1:\n");
+ be_emit_write_line();
}
/* the second Proj might be a fallthrough */
if (can_be_fallthrough(proj_false)) {
- ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
+ if (be_options.verbose_asm)
+ ia32_emitf(proj_false, "/* fallthrough to %L */");
} else {
- ia32_emitf(proj_false, "\tjmp %L\n");
+ ia32_emitf(proj_false, "jmp %L");
}
}
*/
static void emit_ia32_Setcc(const ir_node *node)
{
- const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
-
- pn_Cmp pnc = get_ia32_condcode(node);
- pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
- if (pnc & ia32_pn_Cmp_float) {
- switch (pnc & 0x0f) {
- case pn_Cmp_Uo:
- ia32_emitf(node, "\tsetp %#R\n", dreg);
- return;
-
- case pn_Cmp_Leg:
- ia32_emitf(node, "\tsetnp %#R\n", dreg);
- return;
-
- case pn_Cmp_Eq:
- case pn_Cmp_Lt:
- case pn_Cmp_Le:
- ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
- ia32_emitf(node, "\tsetnp %>R\n", dreg);
- ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
- return;
-
- case pn_Cmp_Ug:
- case pn_Cmp_Uge:
- case pn_Cmp_Ne:
- ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
- ia32_emitf(node, "\tsetp %>R\n", dreg);
- ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
- return;
+ const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
- default:
- break;
+ ia32_condition_code_t cc = get_ia32_condcode(node);
+ cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
+ if (cc & ia32_cc_float_parity_cases) {
+ if (cc & ia32_cc_negated) {
+ ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
+ ia32_emitf(node, "setp %>R", dreg);
+ ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
+ } else {
+ ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
+ ia32_emitf(node, "setnp %>R", dreg);
+ ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
}
+ } else {
+ ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
}
- ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
}
static void emit_ia32_CMovcc(const ir_node *node)
{
- const ia32_attr_t *attr = get_ia32_attr_const(node);
- const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
- pn_Cmp pnc = get_ia32_condcode(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
+ ia32_condition_code_t cc = get_ia32_condcode(node);
const arch_register_t *in_true;
const arch_register_t *in_false;
- pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
+ cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
/* although you can't set ins_permuted in the constructor it might still
* be set by memory operand folding
* Permuting inputs of a cmov means the condition is negated!
*/
if (attr->data.ins_permuted)
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
assert(get_ia32_op_type(node) == ia32_Normal);
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
tmp = in_true;
in_true = in_false;
in_false = tmp;
} else {
/* we need a mov */
- ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
+ ia32_emitf(node, "movl %R, %R", in_false, out);
}
- /* TODO: handling of Nans isn't correct yet */
- if (pnc & ia32_pn_Cmp_float) {
- switch (pnc & 0x0f) {
- case pn_Cmp_Uo:
- case pn_Cmp_Leg:
- case pn_Cmp_Eq:
- case pn_Cmp_Lt:
- case pn_Cmp_Le:
- case pn_Cmp_Ug:
- case pn_Cmp_Uge:
- case pn_Cmp_Ne:
- panic("CMov with floatingpoint compare/parity not supported yet");
- }
+ if (cc & ia32_cc_float_parity_cases) {
+ panic("CMov with floatingpoint compare/parity not supported yet");
}
- ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
-}
-
-/*********************************************************
- * _ _ _
- * (_) | (_)
- * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
- * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
- * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
- * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
- * _/ | | |
- * |__/ |_|
- *********************************************************/
-
-/* jump table entry (target and corresponding number) */
-typedef struct _branch_t {
- ir_node *target;
- int value;
-} branch_t;
-
-/* jump table for switch generation */
-typedef struct _jmp_tbl_t {
- ir_node *defProj; /**< default target */
- long min_value; /**< smallest switch case */
- long max_value; /**< largest switch case */
- long num_branches; /**< number of jumps */
- char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
- branch_t *branches; /**< jump array */
-} jmp_tbl_t;
-
-/**
- * Compare two variables of type branch_t. Used to sort all switch cases
- */
-static int ia32_cmp_branch_t(const void *a, const void *b)
-{
- branch_t *b1 = (branch_t *)a;
- branch_t *b2 = (branch_t *)b;
-
- if (b1->value <= b2->value)
- return -1;
- else
- return 1;
-}
-
-static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
-{
- int i;
- long pnc;
- long default_pn;
- ir_node *proj;
- const ir_edge_t *edge;
-
- /* fill the table structure */
- get_unique_label(tbl->label, SNPRINTF_BUF_LEN, ".TBL_");
- tbl->defProj = NULL;
- tbl->num_branches = get_irn_n_edges(node) - 1;
- tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
- tbl->min_value = LONG_MAX;
- tbl->max_value = LONG_MIN;
-
- default_pn = get_ia32_condcode(node);
- i = 0;
- /* go over all proj's and collect them */
- foreach_out_edge(node, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
-
- pnc = get_Proj_proj(proj);
-
- /* check for default proj */
- if (pnc == default_pn) {
- assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
- tbl->defProj = proj;
- } else {
- tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
- tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
-
- /* create branch entry */
- tbl->branches[i].target = proj;
- tbl->branches[i].value = pnc;
- ++i;
- }
-
- }
- assert(i == tbl->num_branches);
-
- /* sort the branches by their number */
- qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
+ ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
}
/**
- * Emits code for a SwitchJmp (creates a jump table if
- * possible otherwise a cmp-jmp cascade). Port from
- * cggg ia32 backend
+ * Emits code for a SwitchJmp
*/
static void emit_ia32_SwitchJmp(const ir_node *node)
{
- unsigned long interval;
- int last_value, i;
- jmp_tbl_t tbl;
-
- /* fill the table structure */
- generate_jump_table(&tbl, node);
-
- /* two-complement's magic make this work without overflow */
- interval = tbl.max_value - tbl.min_value;
+ ir_entity *jump_table = get_ia32_am_sc(node);
+ const ir_switch_table *table = get_ia32_switch_table(node);
- /* emit the table */
- ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
- ia32_emitf(tbl.defProj, "\tja %L\n");
-
- if (tbl.num_branches > 1) {
- /* create table */
- ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
-
- be_gas_emit_switch_section(GAS_SECTION_RODATA);
- ia32_emitf(NULL, "\t.align 4\n");
- ia32_emitf(NULL, "%s:\n", tbl.label);
-
- last_value = tbl.branches[0].value;
- for (i = 0; i != tbl.num_branches; ++i) {
- while (last_value != tbl.branches[i].value) {
- ia32_emitf(tbl.defProj, ".long %L\n");
- ++last_value;
- }
- ia32_emitf(tbl.branches[i].target, ".long %L\n");
- ++last_value;
- }
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- } else {
- /* one jump is enough */
- ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
- }
-
- free(tbl.branches);
+ ia32_emitf(node, "jmp %*AM");
+ be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
}
/**
*/
static void emit_ia32_Jmp(const ir_node *node)
{
- ir_node *block;
-
- /* for now, the code works for scheduled and non-schedules blocks */
- block = get_nodes_block(node);
-
/* we have a block schedule */
if (can_be_fallthrough(node)) {
- ia32_emitf(node, "\t/* fallthrough to %L */\n");
+ if (be_options.verbose_asm)
+ ia32_emitf(node, "/* fallthrough to %L */");
} else {
- ia32_emitf(node, "\tjmp %L\n");
+ ia32_emitf(node, "jmp %L");
}
}
const arch_register_t *reg;
const ia32_asm_reg_t *asm_regs = attr->register_map;
const ia32_asm_reg_t *asm_reg;
- const char *reg_name;
char c;
char modifier = 0;
- int num = -1;
+ int num;
int p;
assert(*s == '%');
c = *(++s);
/* parse modifiers */
- switch(c) {
+ switch (c) {
case 0:
ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
be_emit_char('%');
- return s + 1;
+ return s;
+
case '%':
be_emit_char('%');
return s + 1;
}
/* parse number */
- sscanf(s, "%d%n", &num, &p);
- if (num < 0) {
+ if (sscanf(s, "%d%n", &num, &p) != 1) {
ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
node);
return s;
s += p;
}
- if (num < 0 || ARR_LEN(asm_regs) <= num) {
+ if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
ir_fprintf(stderr,
"Error: Custom assembler references invalid input/output (%+F)\n",
node);
/* get register */
if (asm_reg->use_input == 0) {
- reg = get_out_reg(node, asm_reg->inout_pos);
+ reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
} else {
ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
emit_ia32_Immediate(pred);
return s;
}
- reg = get_in_reg(node, asm_reg->inout_pos);
+ reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
}
if (reg == NULL) {
ir_fprintf(stderr,
return s;
}
+ /* Emit the register. */
if (asm_reg->memory) {
be_emit_char('(');
- }
-
- /* emit it */
- if (modifier != 0) {
- be_emit_char('%');
- switch(modifier) {
- case 'b':
- reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
- break;
- case 'h':
- reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
- break;
- case 'w':
- reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
- break;
- default:
- panic("Invalid asm op modifier");
- }
- be_emit_string(reg_name);
- } else {
- emit_register(reg, asm_reg->mode);
- }
-
- if (asm_reg->memory) {
+ emit_register(reg, NULL);
be_emit_char(')');
+ } else {
+ switch (modifier) {
+ case '\0': emit_register(reg, asm_reg->mode); break;
+ case 'b': emit_8bit_register(reg); break;
+ case 'h': emit_8bit_register_high(reg); break;
+ case 'w': emit_16bit_register(reg); break;
+ default: panic("Invalid asm op modifier");
+ }
}
return s;
ident *asm_text = attr->asm_text;
const char *s = get_id_str(asm_text);
- ia32_emitf(node, "#APP\t\n");
+ be_emit_cstring("#APP\n");
+ be_emit_write_line();
if (s[0] != '\t')
be_emit_char('\t');
- while(*s != 0) {
+ while (*s != 0) {
if (*s == '%') {
s = emit_asm_operand(node, s);
} else {
}
}
- ia32_emitf(NULL, "\n#NO_APP\n");
+ be_emit_cstring("\n#NO_APP\n");
+ be_emit_write_line();
}
-/**********************************
- * _____ ____
- * / ____| | _ \
- * | | ___ _ __ _ _| |_) |
- * | | / _ \| '_ \| | | | _ <
- * | |___| (_) | |_) | |_| | |_) |
- * \_____\___/| .__/ \__, |____/
- * | | __/ |
- * |_| |___/
- **********************************/
/**
* Emit movsb/w instructions to make mov count divideable by 4
static void emit_CopyB_prolog(unsigned size)
{
if (size & 1)
- ia32_emitf(NULL, "\tmovsb\n");
+ ia32_emitf(NULL, "movsb");
if (size & 2)
- ia32_emitf(NULL, "\tmovsw\n");
+ ia32_emitf(NULL, "movsw");
}
/**
unsigned size = get_ia32_copyb_size(node);
emit_CopyB_prolog(size);
- ia32_emitf(node, "\trep movsd\n");
+ ia32_emitf(node, "rep movsd");
}
/**
size >>= 2;
while (size--) {
- ia32_emitf(NULL, "\tmovsd\n");
+ ia32_emitf(NULL, "movsd");
}
}
-
-/***************************
- * _____
- * / ____|
- * | | ___ _ ____ __
- * | | / _ \| '_ \ \ / /
- * | |___| (_) | | | \ V /
- * \_____\___/|_| |_|\_/
- *
- ***************************/
-
/**
* Emit code for conversions (I, FP), (FP, I) and (FP, FP).
*/
int ls_bits = get_mode_size_bits(ls_mode);
const char *conv = ls_bits == 32 ? conv_f : conv_d;
- ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
+ ia32_emitf(node, "cvt%s %AS3, %D0", conv);
}
static void emit_ia32_Conv_I2FP(const ir_node *node)
emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
}
-/**
- * Emits code for an Int conversion.
- */
-static void emit_ia32_Conv_I2I(const ir_node *node)
-{
- ir_mode *smaller_mode = get_ia32_ls_mode(node);
- int signed_mode = mode_is_signed(smaller_mode);
- const char *sign_suffix;
-
- assert(!mode_is_float(smaller_mode));
-
- sign_suffix = signed_mode ? "s" : "z";
- ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
-}
-
-/**
- * Emits a call
- */
-static void emit_ia32_Call(const ir_node *node)
-{
- /* Special case: Call must not have its immediates prefixed by $, instead
- * address mode is prefixed by *. */
- ia32_emitf(node, "\tcall %*AS3\n");
-}
-
-
-/*******************************************
- * _ _
- * | | | |
- * | |__ ___ _ __ ___ __| | ___ ___
- * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
- * | |_) | __/ | | | (_) | (_| | __/\__ \
- * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
- *
- *******************************************/
-
/**
* Emits code to increase stack pointer.
*/
return;
if (offs > 0) {
- ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
+ ia32_emitf(node, "subl $%u, %D0", offs);
} else {
- ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
+ ia32_emitf(node, "addl $%u, %D0", -offs);
}
}
-static inline bool is_unknown_reg(const arch_register_t *reg)
-{
- if(reg == &ia32_gp_regs[REG_GP_UKNWN]
- || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
- || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
- return true;
-
- return false;
-}
-
/**
* Emits code for Copy/CopyKeep.
*/
if (in == out) {
return;
}
- if (is_unknown_reg(in))
- return;
- /* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
- if (get_irn_mode(node) == mode_E) {
- ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
- } else {
- ia32_emitf(node, "\tmovl %R, %R\n", in, out);
- }
+ ia32_emitf(node, "movl %R, %R", in, out);
}
static void emit_be_Copy(const ir_node *node)
static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
- const arch_register_class_t *cls0, *cls1;
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
- cls0 = arch_register_get_class(in0);
- cls1 = arch_register_get_class(in1);
-
- assert(cls0 == cls1 && "Register class mismatch at Perm");
+ arch_register_class_t const *const cls0 = in0->reg_class;
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
- ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
+ ia32_emitf(node, "xchg %R, %R", in1, in0);
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
- ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
- ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
- ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
+ ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
+ ia32_emitf(node, "xorpd %R, %R", in1, in0);
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
}
}
-/**
- * Emits code for Constant loading.
- */
-static void emit_ia32_Const(const ir_node *node)
-{
- ia32_emitf(node, "\tmovl %I, %D0\n");
-}
-
-/**
- * Emits code to load the TLS base
- */
-static void emit_ia32_LdTls(const ir_node *node)
-{
- ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
-}
-
/* helper function for emit_ia32_Minus64Bit */
static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
{
- ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
+ ia32_emitf(node, "movl %R, %R", src, dst);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_neg(const ir_node* node, const arch_register_t *reg)
{
- ia32_emitf(node, "\tnegl %R\n", reg);
+ ia32_emitf(node, "negl %R", reg);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
{
- ia32_emitf(node, "\tsbbl $0, %R\n", reg);
+ ia32_emitf(node, "sbbl $0, %R", reg);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
{
- ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
+ ia32_emitf(node, "sbbl %R, %R", src, dst);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
{
- ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
+ ia32_emitf(node, "xchgl %R, %R", src, dst);
}
/* helper function for emit_ia32_Minus64Bit */
static void emit_zero(const ir_node* node, const arch_register_t *reg)
{
- ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
+ ia32_emitf(node, "xorl %R, %R", reg, reg);
}
static void emit_ia32_Minus64Bit(const ir_node *node)
{
- const arch_register_t *in_lo = get_in_reg(node, 0);
- const arch_register_t *in_hi = get_in_reg(node, 1);
- const arch_register_t *out_lo = get_out_reg(node, 0);
- const arch_register_t *out_hi = get_out_reg(node, 1);
+ const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
+ const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
+ const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
+ const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
if (out_lo == in_lo) {
if (out_hi != in_hi) {
static void emit_ia32_GetEIP(const ir_node *node)
{
- ia32_emitf(node, "\tcall %s\n", pic_base_label);
- ia32_emitf(NULL, "%s:\n", pic_base_label);
- ia32_emitf(node, "\tpopl %D0\n");
+ ia32_emitf(node, "call %s", pic_base_label);
+ be_emit_irprintf("%s:\n", pic_base_label);
+ be_emit_write_line();
+ ia32_emitf(node, "popl %D0");
}
static void emit_ia32_ClimbFrame(const ir_node *node)
{
const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
- ia32_emitf(node, "\tmovl %S0, %D0\n");
- ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
+ ia32_emitf(node, "movl %S0, %D0");
+ ia32_emitf(node, "movl $%u, %S1", attr->count);
be_gas_emit_block_name(node);
be_emit_cstring(":\n");
be_emit_write_line();
- ia32_emitf(node, "\tmovl (%D0), %D0\n");
- ia32_emitf(node, "\tdec %S1\n");
+ ia32_emitf(node, "movl (%D0), %D0");
+ ia32_emitf(node, "dec %S1");
be_emit_cstring("\tjnz ");
be_gas_emit_block_name(node);
be_emit_finish_line_gas(node);
unsigned pop = be_Return_get_pop(node);
if (pop > 0 || be_Return_get_emit_pop(node)) {
- ia32_emitf(node, "\tret $%u\n", pop);
+ ia32_emitf(node, "ret $%u", pop);
} else {
- ia32_emitf(node, "\tret\n");
+ ia32_emitf(node, "ret");
}
}
-static void emit_Nothing(const ir_node *node)
-{
- (void) node;
-}
-
-
-/***********************************************************************************
- * _ __ _
- * (_) / _| | |
- * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
- * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
- * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
- * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
- *
- ***********************************************************************************/
/**
* Enters the emitter functions for handled nodes into the generic
*/
static void ia32_register_emitters(void)
{
-#define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
-#define IA32_EMIT(a) IA32_EMIT2(a,a)
-#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
-#define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
-#define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
-#define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
+#define IA32_EMIT(a) be_set_emitter(op_ia32_##a, emit_ia32_##a)
+#define EMIT(a) be_set_emitter(op_##a, emit_##a)
+#define IGN(a) be_set_emitter(op_##a, be_emit_nothing)
+#define BE_EMIT(a) be_set_emitter(op_be_##a, emit_be_##a)
+#define BE_IGN(a) be_set_emitter(op_be_##a, be_emit_nothing)
/* first clear the generic function pointer for all ops */
- clear_irp_opcodes_generic_func();
+ ir_clear_opcodes_generic_func();
/* register all emitter functions defined in spec */
ia32_register_spec_emitters();
/* other ia32 emitter functions */
- IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
IA32_EMIT(Asm);
IA32_EMIT(CMovcc);
- IA32_EMIT(Call);
- IA32_EMIT(Const);
IA32_EMIT(Conv_FP2FP);
IA32_EMIT(Conv_FP2I);
IA32_EMIT(Conv_I2FP);
- IA32_EMIT(Conv_I2I);
IA32_EMIT(CopyB);
IA32_EMIT(CopyB_i);
IA32_EMIT(GetEIP);
IA32_EMIT(IMul);
IA32_EMIT(Jcc);
IA32_EMIT(Setcc);
- IA32_EMIT(LdTls);
IA32_EMIT(Minus64Bit);
IA32_EMIT(SwitchJmp);
IA32_EMIT(ClimbFrame);
BE_EMIT(Perm);
BE_EMIT(Return);
- BE_IGN(Barrier);
BE_IGN(Keep);
BE_IGN(Start);
#undef BE_EMIT
#undef EMIT
#undef IGN
-#undef IA32_EMIT2
#undef IA32_EMIT
}
-typedef void (*emit_func_ptr) (const ir_node *);
-
/**
* Assign and emit an exception label if the current instruction can fail.
*/
*/
static void ia32_emit_node(ir_node *node)
{
- ir_op *op = get_irn_op(node);
-
DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
if (is_ia32_irn(node)) {
}
if (mark_spill_reload) {
if (is_ia32_is_spill(node)) {
- ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
+ ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
}
if (is_ia32_is_reload(node)) {
- ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
+ ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
}
if (is_ia32_is_remat(node)) {
- ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
+ ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
}
}
}
- if (op->ops.generic) {
- emit_func_ptr func = (emit_func_ptr) op->ops.generic;
- be_dbg_set_dbg_info(get_irn_dbg_info(node));
+ be_emit_node(node);
- (*func) (node);
- } else {
- emit_Nothing(node);
- ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
- abort();
+ if (sp_relative) {
+ int sp_change = arch_get_sp_bias(node);
+ if (sp_change != 0) {
+ assert(sp_change != SP_BIAS_RESET);
+ callframe_offset += sp_change;
+ be_dwarf_callframe_offset(callframe_offset);
+ }
}
}
*/
static void ia32_emit_alignment(unsigned align, unsigned skip)
{
- ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
+ ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
}
/**
static int should_align_block(const ir_node *block)
{
static const double DELTA = .0001;
- ir_exec_freq *exec_freq = cg->birg->exec_freq;
- ir_node *prev = get_prev_block_sched(block);
- double block_freq;
- double prev_freq = 0; /**< execfreq of the fallthrough block */
- double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
- int i, n_cfgpreds;
-
- if (exec_freq == NULL)
- return 0;
+ ir_node *prev = get_prev_block_sched(block);
+ double prev_freq = 0; /**< execfreq of the fallthrough block */
+ double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
+ double block_freq;
+ int i, n_cfgpreds;
+
if (ia32_cg_config.label_alignment_factor <= 0)
return 0;
- block_freq = get_block_execfreq(exec_freq, block);
+ block_freq = get_block_execfreq(block);
if (block_freq < DELTA)
return 0;
n_cfgpreds = get_Block_n_cfgpreds(block);
- for(i = 0; i < n_cfgpreds; ++i) {
+ for (i = 0; i < n_cfgpreds; ++i) {
const ir_node *pred = get_Block_cfgpred_block(block, i);
- double pred_freq = get_block_execfreq(exec_freq, pred);
+ double pred_freq = get_block_execfreq(pred);
if (pred == prev) {
prev_freq += pred_freq;
*/
static void ia32_emit_block_header(ir_node *block)
{
- ir_graph *irg = current_ir_graph;
- int need_label = block_needs_label(block);
- int i, arity;
- ir_exec_freq *exec_freq = cg->birg->exec_freq;
-
+ ir_graph *const irg = get_Block_irg(block);
if (block == get_irg_end_block(irg))
return;
}
}
- if (need_label) {
- be_gas_emit_block_name(block);
- be_emit_char(':');
-
- be_emit_pad_comment();
- be_emit_cstring(" /* ");
- } else {
- be_emit_cstring("\t/* ");
- be_gas_emit_block_name(block);
- be_emit_cstring(": ");
- }
-
- be_emit_cstring("preds:");
-
- /* emit list of pred blocks in comment */
- arity = get_irn_arity(block);
- if (arity <= 0) {
- be_emit_cstring(" none");
- } else {
- for (i = 0; i < arity; ++i) {
- ir_node *predblock = get_Block_cfgpred_block(block, i);
- be_emit_irprintf(" %d", get_irn_node_nr(predblock));
- }
- }
- if (exec_freq != NULL) {
- be_emit_irprintf(", freq: %f",
- get_block_execfreq(exec_freq, block));
- }
- be_emit_cstring(" */\n");
- be_emit_write_line();
+ int const need_label = block_needs_label(block);
+ be_gas_begin_block(block, need_label);
}
/**
*/
static void ia32_gen_block(ir_node *block)
{
- ir_node *node;
-
ia32_emit_block_header(block);
+ if (sp_relative) {
+ ir_graph *irg = get_irn_irg(block);
+ callframe_offset = 4; /* 4 bytes for the return address */
+ /* ESP guessing, TODO perform a real ESP simulation */
+ if (block != get_irg_start_block(irg)) {
+ callframe_offset += frame_type_size;
+ }
+ be_dwarf_callframe_offset(callframe_offset);
+ }
+
/* emit the contents of the block */
- be_dbg_set_dbg_info(get_irn_dbg_info(block));
+ be_dwarf_location(get_irn_dbg_info(block));
sched_foreach(block, node) {
ia32_emit_node(node);
}
*/
static void ia32_gen_labels(ir_node *block, void *data)
{
- exc_entry **exc_list = data;
+ exc_entry **exc_list = (exc_entry**)data;
ir_node *pred;
int n;
*/
static int cmp_exc_entry(const void *a, const void *b)
{
- const exc_entry *ea = a;
- const exc_entry *eb = b;
+ const exc_entry *ea = (const exc_entry*)a;
+ const exc_entry *eb = (const exc_entry*)b;
if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
return -1;
return +1;
}
+static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
+{
+ ir_entity *entity = get_irg_entity(irg);
+ ir_type *type = get_entity_type(entity);
+ size_t n_params = get_method_n_params(type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_type *arg_type = layout->arg_type;
+ size_t n_members = get_compound_n_members(arg_type);
+ parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
+ size_t i;
+
+ for (i = 0; i < n_members; ++i) {
+ ir_entity *member = get_compound_member(arg_type, i);
+ size_t param;
+ if (!is_parameter_entity(member))
+ continue;
+ param = get_entity_parameter_number(member);
+ if (param == IR_VA_START_PARAMETER_NUMBER)
+ continue;
+ assert(infos[param].entity == NULL && infos[param].reg == NULL);
+ infos[param].reg = NULL;
+ infos[param].entity = member;
+ }
+
+ return infos;
+}
+
/**
* Main driver. Emits the code for one routine.
*/
-void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
+void ia32_gen_routine(ir_graph *irg)
{
- ir_entity *entity = get_irg_entity(irg);
- exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
+ ir_entity *entity = get_irg_entity(irg);
+ exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ ir_node **blk_sched = irg_data->blk_sched;
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ parameter_dbg_info_t *infos;
int i, n;
- cg = ia32_cg;
- isa = cg->isa;
- do_pic = cg->birg->main_env->options->pic;
+ isa = (ia32_isa_t*) arch_env;
+ do_pic = be_options.pic;
be_gas_elf_type_char = '@';
ia32_register_emitters();
- get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
+ get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
- be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
- be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
+ infos = construct_parameter_infos(irg);
+ be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
+ infos);
+ xfree(infos);
+
+ sp_relative = layout->sp_relative;
+ if (layout->sp_relative) {
+ ir_type *frame_type = get_irg_frame_type(irg);
+ frame_type_size = get_type_size_bytes(frame_type);
+ be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
+ } else {
+ /* well not entirely correct here, we should emit this after the
+ * "movl esp, ebp" */
+ be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
+ /* TODO: do not hardcode the following */
+ be_dwarf_callframe_offset(8);
+ be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
+ }
/* we use links to point to target blocks */
ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
/* initialize next block links */
- n = ARR_LEN(cg->blk_sched);
+ n = ARR_LEN(blk_sched);
for (i = 0; i < n; ++i) {
- ir_node *block = cg->blk_sched[i];
- ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
+ ir_node *block = blk_sched[i];
+ ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
set_irn_link(block, prev);
}
for (i = 0; i < n; ++i) {
- ir_node *block = cg->blk_sched[i];
+ ir_node *block = blk_sched[i];
ia32_gen_block(block);
}
be_gas_emit_function_epilog(entity);
- be_dbg_method_end();
- be_emit_char('\n');
- be_emit_write_line();
ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
Those are ascending with ascending addresses. */
qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
{
- int i;
+ size_t e;
- for (i = 0; i < ARR_LEN(exc_list); ++i) {
+ for (e = 0; e < ARR_LEN(exc_list); ++e) {
be_emit_cstring("\t.long ");
- ia32_emit_exc_label(exc_list[i].exc_instr);
+ ia32_emit_exc_label(exc_list[e].exc_instr);
be_emit_char('\n');
be_emit_cstring("\t.long ");
- be_gas_emit_block_name(exc_list[i].block);
+ be_gas_emit_block_name(exc_list[e].block);
be_emit_char('\n');
}
}
static unsigned char reg_gp_map[N_ia32_gp_REGS];
//static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
//static unsigned char reg_sse_map[N_ia32_xmm_REGS];
-static unsigned char pnc_map_signed[8];
-static unsigned char pnc_map_unsigned[8];
static void build_reg_map(void)
{
- reg_gp_map[REG_EAX] = 0x0;
- reg_gp_map[REG_ECX] = 0x1;
- reg_gp_map[REG_EDX] = 0x2;
- reg_gp_map[REG_EBX] = 0x3;
- reg_gp_map[REG_ESP] = 0x4;
- reg_gp_map[REG_EBP] = 0x5;
- reg_gp_map[REG_ESI] = 0x6;
- reg_gp_map[REG_EDI] = 0x7;
-
- pnc_map_signed[pn_Cmp_Eq] = 0x04;
- pnc_map_signed[pn_Cmp_Lt] = 0x0C;
- pnc_map_signed[pn_Cmp_Le] = 0x0E;
- pnc_map_signed[pn_Cmp_Gt] = 0x0F;
- pnc_map_signed[pn_Cmp_Ge] = 0x0D;
- pnc_map_signed[pn_Cmp_Lg] = 0x05;
-
- pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
- pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
- pnc_map_unsigned[pn_Cmp_Le] = 0x06;
- pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
- pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
- pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
+ reg_gp_map[REG_GP_EAX] = 0x0;
+ reg_gp_map[REG_GP_ECX] = 0x1;
+ reg_gp_map[REG_GP_EDX] = 0x2;
+ reg_gp_map[REG_GP_EBX] = 0x3;
+ reg_gp_map[REG_GP_ESP] = 0x4;
+ reg_gp_map[REG_GP_EBP] = 0x5;
+ reg_gp_map[REG_GP_ESI] = 0x6;
+ reg_gp_map[REG_GP_EDI] = 0x7;
}
/** Returns the encoding for a pnc field. */
-static unsigned char pnc2cc(int pnc)
+static unsigned char pnc2cc(ia32_condition_code_t cc)
{
- unsigned char cc;
- if (pnc == ia32_pn_Cmp_parity) {
- cc = 0x0A;
- } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
- cc = pnc_map_unsigned[pnc & 0x07];
- } else {
- cc = pnc_map_signed[pnc & 0x07];
- }
- assert(cc != 0);
- return cc;
+ return cc & 0xf;
}
-/** Sign extension bit values for binops */
-enum SignExt {
- UNSIGNED_IMM = 0, /**< unsigned immediate */
- SIGNEXT_IMM = 2, /**< sign extended immediate */
+enum OpSize {
+ OP_8 = 0x00, /* 8bit operation. */
+ OP_16_32 = 0x01, /* 16/32bit operation. */
+ OP_MEM_SRC = 0x02, /* The memory operand is in the soruce position. */
+ OP_IMM8 = 0x02, /* 8bit immediate, which gets sign extended for 16/32bit operation. */
+ OP_16_32_IMM8 = 0x03, /* 16/32bit operation with sign extended 8bit immediate. */
+ OP_EAX = 0x04, /* Short form of instruction with al/ax/eax as operand. */
};
/** The mod encoding of the ModR/M */
be_gas_emit_entity(entity);
if (get_entity_owner(entity) == get_tls_type()) {
- if (get_entity_visibility(entity) == ir_visibility_external) {
+ if (!entity_has_definition(entity)) {
be_emit_cstring("@INDNTPOFF");
} else {
be_emit_cstring("@NTPOFF");
int offs = get_ia32_am_offs_int(node);
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
unsigned modrm = 0;
unsigned sib = 0;
unsigned emitoffs = 0;
/* Determine if we need a SIB byte. */
if (has_index) {
- const arch_register_t *reg_index = arch_get_irn_register(index);
+ const arch_register_t *reg_index = arch_get_irn_register(idx);
int scale = get_ia32_am_scale(node);
assert(scale < 4);
/* R/M set to ESP means SIB in 32bit mode. */
}
}
-/**
- * Emit a binop with a immediate operand.
- *
- * @param node the node to emit
- * @param opcode_eax the opcode for the op eax, imm variant
- * @param opcode the opcode for the reg, imm variant
- * @param ruval the opcode extension for opcode
- */
-static void bemit_binop_with_imm(
- const ir_node *node,
- unsigned char opcode_ax,
- unsigned char opcode, unsigned char ruval)
-{
- /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
- const ir_node *op = get_irn_n(node, n_ia32_binary_right);
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
- unsigned size;
-
- /* Some instructions (test) have no short form with 32bit value + 8bit
- * immediate. */
- if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
- size = 4;
- } else {
- /* check for sign extension */
- size = get_signed_imm_size(attr->offset);
- }
-
- switch (size) {
- case 1:
- bemit8(opcode | SIGNEXT_IMM);
- /* cmp has this special mode */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit_mod_am(ruval, node);
- } else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
- bemit_modru(reg, ruval);
- }
- bemit8((unsigned char)attr->offset);
- return;
- case 2:
- case 4:
- /* check for eax variant: this variant is shorter for 32bit immediates only */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit8(opcode);
- bemit_mod_am(ruval, node);
- } else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
- if (reg->index == REG_EAX) {
- bemit8(opcode_ax);
- } else {
- bemit8(opcode);
- bemit_modru(reg, ruval);
- }
- }
- bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
- return;
- }
- panic("invalid imm size?!?");
-}
-
-/**
- * Emits a binop.
- */
-static void bemit_binop_2(const ir_node *node, unsigned code)
-{
- const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
- bemit8(code);
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
- bemit_modrr(op2, out);
- } else {
- bemit_mod_am(reg_gp_map[out->index], node);
- }
-}
-
-/**
- * Emit a binop.
- */
-static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
-{
- ir_node *right = get_irn_n(node, n_ia32_binary_right);
- if (is_ia32_Immediate(right)) {
- bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
- } else {
- bemit_binop_2(node, opcodes[0]);
- }
-}
-
/**
* Emit an unop.
*/
{
bemit8(code);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = get_in_reg(node, input);
+ const arch_register_t *in = arch_get_irn_register_in(node, input);
bemit_modru(in, ext);
} else {
bemit_mod_am(ext, node);
static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit_unop(node, code, reg_gp_map[out->index], input);
}
bemit_mod_am(ext, node);
}
+static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
+{
+ bemit8(0x0F);
+ bemit_unop_reg(node, code, input);
+}
+
static void bemit_immediate(const ir_node *node, bool relative)
{
const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
static void bemit_copy(const ir_node *copy)
{
- const arch_register_t *in = get_in_reg(copy, 0);
- const arch_register_t *out = get_out_reg(copy, 0);
+ const arch_register_t *in = arch_get_irn_register_in(copy, 0);
+ const arch_register_t *out = arch_get_irn_register_out(copy, 0);
- if (in == out || is_unknown_reg(in))
+ if (in == out)
return;
- /* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
- if (get_irn_mode(copy) == mode_E) {
- panic("NIY");
- } else {
- assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
- bemit8(0x8B);
- bemit_modrr(in, out);
- }
+ assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
+ bemit8(0x8B);
+ bemit_modrr(in, out);
}
static void bemit_perm(const ir_node *node)
{
const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
- const arch_register_class_t *cls0 = arch_register_get_class(in0);
+ const arch_register_class_t *cls0 = in0->reg_class;
- assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
- if (in0->index == REG_EAX) {
+ if (in0->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[in1->index]);
- } else if (in1->index == REG_EAX) {
+ } else if (in1->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[in0->index]);
} else {
bemit8(0x87);
}
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
panic("unimplemented"); // TODO implement
- //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
- //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
- //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
+ //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
+ //ia32_emitf(node, "xorpd %R, %R", in1, in0);
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
static void bemit_xor0(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0x31);
bemit_modrr(out, out);
}
static void bemit_mov_const(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0xB8 + reg_gp_map[out->index]);
bemit_immediate(node, false);
}
-/**
- * Creates a function for a Binop with 3 possible encodings.
- */
-#define BINOP(op, op0, op1, op2, op2_ext) \
-static void bemit_ ## op(const ir_node *node) { \
- static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
- bemit_binop(node, op ## _codes); \
-}
-
-/* insn def eax,imm imm */
-BINOP(add, 0x03, 0x05, 0x81, 0)
-BINOP(or, 0x0B, 0x0D, 0x81, 1)
-BINOP(adc, 0x13, 0x15, 0x81, 2)
-BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
-BINOP(and, 0x23, 0x25, 0x81, 4)
-BINOP(sub, 0x2B, 0x2D, 0x81, 5)
-BINOP(xor, 0x33, 0x35, 0x81, 6)
-BINOP(test, 0x85, 0xA9, 0xF7, 0)
-
-#define BINOPMEM(op, ext) \
-static void bemit_##op(const ir_node *node) \
-{ \
- ir_node *val; \
- unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
- if (size == 16) \
- bemit8(0x66); \
- val = get_irn_n(node, n_ia32_unary_op); \
- if (is_ia32_Immediate(val)) { \
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
- int offset = attr->offset; \
- if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
- bemit8(0x83); \
- bemit_mod_am(ext, node); \
- bemit8(offset); \
- } else { \
- bemit8(0x81); \
- bemit_mod_am(ext, node); \
- if (size == 16) { \
- bemit16(offset); \
- } else { \
- bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
- } \
- } \
- } else { \
- bemit8(ext << 3 | 1); \
- bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
- } \
-} \
- \
-static void bemit_##op##8bit(const ir_node *node) \
-{ \
- ir_node *val = get_irn_n(node, n_ia32_unary_op); \
- if (is_ia32_Immediate(val)) { \
- bemit8(0x80); \
- bemit_mod_am(ext, node); \
- bemit8(get_ia32_immediate_attr_const(val)->offset); \
- } else { \
- bemit8(ext << 3); \
- bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
- } \
-}
+/**
+ * Emit a binop.
+ */
+static void bemit_binop(ir_node const *const node, unsigned const code)
+{
+ ir_mode *const ls_mode = get_ia32_ls_mode(node);
+ unsigned size = ls_mode ? get_mode_size_bits(ls_mode) : 32;
+ if (size == 16)
+ bemit8(0x66);
+
+ unsigned op = size == 8 ? OP_8 : OP_16_32;
+ ir_node *const right = get_irn_n(node, n_ia32_binary_right);
+ if (is_ia32_Immediate(right)) {
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
+ /* Try to use the short form with 8bit sign extended immediate. */
+ if (op != OP_8 && !attr->symconst && get_signed_imm_size(attr->offset) == 1) {
+ op = OP_16_32_IMM8;
+ size = 8;
+ }
+
+ /* Emit the main opcode. */
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_binary_left);
+ /* Try to use the shorter al/ax/eax form. */
+ if (dst->index == REG_GP_EAX && op != OP_16_32_IMM8) {
+ bemit8(code << 3 | OP_EAX | op);
+ } else {
+ bemit8(0x80 | op);
+ bemit_modru(dst, code);
+ }
+ } else {
+ bemit8(0x80 | op);
+ bemit_mod_am(code, node);
+ }
+
+ /* Emit the immediate. */
+ switch (size) {
+ case 8: bemit8(attr->offset); break;
+ case 16: bemit16(attr->offset); break;
+ case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
+ }
+ } else {
+ bemit8(code << 3 | OP_MEM_SRC | op);
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_binary_left);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ arch_register_t const *const src = arch_get_irn_register(right);
+ bemit_modrr(src, dst);
+ } else {
+ bemit_mod_am(reg_gp_map[dst->index], node);
+ }
+ }
+}
+
+/**
+ * Create a function for a binop.
+ */
+#define BINOP(op, code) \
+ static void bemit_##op(ir_node const *const node) \
+ { \
+ bemit_binop(node, code); \
+ }
+
+/* insn opcode */
+BINOP(add, 0)
+BINOP(or, 1)
+BINOP(adc, 2)
+BINOP(sbb, 3)
+BINOP(and, 4)
+BINOP(sub, 5)
+BINOP(xor, 6)
+BINOP(cmp, 7)
+
+static void bemit_binop_mem(ir_node const *const node, unsigned const code)
+{
+ unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
+ if (size == 16)
+ bemit8(0x66);
+
+ unsigned op = size == 8 ? OP_8 : OP_16_32;
+ ir_node *const val = get_irn_n(node, n_ia32_unary_op);
+ if (is_ia32_Immediate(val)) {
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(val);
+ /* Try to use the short form with 8bit sign extended immediate. */
+ if (op != OP_8 && !attr->symconst && get_signed_imm_size(attr->offset) == 1) {
+ op = OP_16_32_IMM8;
+ size = 8;
+ }
+
+ /* Emit the main opcode. */
+ bemit8(0x80 | op);
+ bemit_mod_am(code, node);
+
+ /* Emit the immediate. */
+ switch (size) {
+ case 8: bemit8(attr->offset); break;
+ case 16: bemit16(attr->offset); break;
+ case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
+ }
+ } else {
+ bemit8(code << 3 | op);
+ bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node);
+ }
+}
+
+#define BINOPMEM(op, code) \
+ static void bemit_##op(ir_node const *const node) \
+ { \
+ bemit_binop_mem(node, code); \
+ }
BINOPMEM(addmem, 0)
BINOPMEM(ormem, 1)
#define SHIFT(op, ext) \
static void bemit_##op(const ir_node *node) \
{ \
- const arch_register_t *out = get_out_reg(node, 0); \
+ const arch_register_t *out = arch_get_irn_register_out(node, 0); \
ir_node *count = get_irn_n(node, 1); \
if (is_ia32_Immediate(count)) { \
int offset = get_ia32_immediate_attr_const(count)->offset; \
static void bemit_shld(const ir_node *node)
{
- const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
- const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
bemit8(0x0F);
if (is_ia32_Immediate(count)) {
static void bemit_shrd(const ir_node *node)
{
- const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
- const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
bemit8(0x0F);
if (is_ia32_Immediate(count)) {
}
}
+static void bemit_sbb0(ir_node const *const node)
+{
+ arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
+ unsigned char const reg = reg_gp_map[out->index];
+ bemit8(0x1B);
+ bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
+}
+
/**
* binary emitter for setcc.
*/
static void bemit_setcc(const ir_node *node)
{
- const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
+ const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
- pn_Cmp pnc = get_ia32_condcode(node);
- pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
- if (pnc & ia32_pn_Cmp_float) {
- switch (pnc & 0x0f) {
- case pn_Cmp_Uo:
- /* setp <dreg */
+ ia32_condition_code_t cc = get_ia32_condcode(node);
+ cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
+ if (cc & ia32_cc_float_parity_cases) {
+ if (cc & ia32_cc_negated) {
+ /* set%PNC <dreg */
bemit8(0x0F);
- bemit8(0x9A);
+ bemit8(0x90 | pnc2cc(cc));
bemit_modrm8(REG_LOW, dreg);
- return;
- case pn_Cmp_Leg:
- /* setnp <dreg*/
+ /* setp >dreg */
bemit8(0x0F);
- bemit8(0x9B);
- bemit_modrm8(REG_LOW, dreg);
- return;
+ bemit8(0x9A);
+ bemit_modrm8(REG_HIGH, dreg);
- case pn_Cmp_Eq:
- case pn_Cmp_Lt:
- case pn_Cmp_Le:
+ /* orb %>dreg, %<dreg */
+ bemit8(0x08);
+ bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
+ } else {
/* set%PNC <dreg */
bemit8(0x0F);
- bemit8(0x90 | pnc2cc(pnc));
+ bemit8(0x90 | pnc2cc(cc));
bemit_modrm8(REG_LOW, dreg);
/* setnp >dreg */
/* andb %>dreg, %<dreg */
bemit8(0x20);
bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
- return;
+ }
+ } else {
+ /* set%PNC <dreg */
+ bemit8(0x0F);
+ bemit8(0x90 | pnc2cc(cc));
+ bemit_modrm8(REG_LOW, dreg);
+ }
+}
- case pn_Cmp_Ug:
- case pn_Cmp_Uge:
- case pn_Cmp_Ne:
- /* set%PNC <dreg */
- bemit8(0x0F);
- bemit8(0x90 | pnc2cc(pnc));
- bemit_modrm8(REG_LOW, dreg);
+static void bemit_bsf(ir_node const *const node)
+{
+ bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
+}
- /* setp >dreg */
- bemit8(0x0F);
- bemit8(0x9A);
- bemit_modrm8(REG_HIGH, dreg);
+static void bemit_bsr(ir_node const *const node)
+{
+ bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
+}
- /* orb %>dreg, %<dreg */
- bemit8(0x08);
- bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
- return;
+static void bemit_bswap(ir_node const *const node)
+{
+ bemit8(0x0F);
+ bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
+}
- default:
- break;
- }
- }
- /* set%PNC <dreg */
+static void bemit_bt(ir_node const *const node)
+{
bemit8(0x0F);
- bemit8(0x90 | pnc2cc(pnc));
- bemit_modrm8(REG_LOW, dreg);
+ arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
+ ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
+ if (is_ia32_Immediate(right)) {
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
+ int const offset = attr->offset;
+ assert(!attr->symconst);
+ assert(get_signed_imm_size(offset) == 1);
+ bemit8(0xBA);
+ bemit_modru(lreg, 4);
+ bemit8(offset);
+ } else {
+ bemit8(0xA3);
+ bemit_modrr(lreg, arch_get_irn_register(right));
+ }
}
static void bemit_cmovcc(const ir_node *node)
{
const ia32_attr_t *attr = get_ia32_attr_const(node);
int ins_permuted = attr->data.ins_permuted;
- const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
- pn_Cmp pnc = get_ia32_condcode(node);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
+ ia32_condition_code_t cc = get_ia32_condcode(node);
const arch_register_t *in_true;
const arch_register_t *in_false;
- pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
+ cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
}
if (ins_permuted)
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
- /* TODO: handling of Nans isn't correct yet */
+ if (cc & ia32_cc_float_parity_cases)
+ panic("cmov can't handle parity float cases");
bemit8(0x0F);
- bemit8(0x40 | pnc2cc(pnc));
+ bemit8(0x40 | pnc2cc(cc));
if (get_ia32_op_type(node) == ia32_Normal) {
bemit_modrr(in_true, out);
} else {
}
}
-static void bemit_cmp(const ir_node *node)
+static void bemit_test(ir_node const *const node)
{
- unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
- ir_node *right;
-
- if (ls_size == 16)
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ if (size == 16)
bemit8(0x66);
- right = get_irn_n(node, n_ia32_binary_right);
- if (is_ia32_Immediate(right)) {
- /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
- const ir_node *op = get_irn_n(node, n_ia32_binary_right);
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
- unsigned size;
-
- if (attr->symconst != NULL) {
- size = 4;
- } else {
- /* check for sign extension */
- size = get_signed_imm_size(attr->offset);
- }
-
- switch (size) {
- case 1:
- bemit8(0x81 | SIGNEXT_IMM);
- /* cmp has this special mode */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit_mod_am(7, node);
- } else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
- bemit_modru(reg, 7);
- }
- bemit8((unsigned char)attr->offset);
- return;
- case 2:
- case 4:
- /* check for eax variant: this variant is shorter for 32bit immediates only */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit8(0x81);
- bemit_mod_am(7, node);
- } else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
- if (reg->index == REG_EAX) {
- bemit8(0x3D);
- } else {
- bemit8(0x81);
- bemit_modru(reg, 7);
- }
- }
- if (ls_size == 16) {
- bemit16(attr->offset);
- } else {
- bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
- }
- return;
- }
- panic("invalid imm size?!?");
- } else {
- const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
- bemit8(0x3B);
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
- bemit_modrr(op2, out);
- } else {
- bemit_mod_am(reg_gp_map[out->index], node);
- }
- }
-}
-
-static void bemit_cmp8bit(const ir_node *node)
-{
- ir_node *right = get_irn_n(node, n_ia32_binary_right);
+ unsigned const op = size == 8 ? OP_8 : OP_16_32;
+ ir_node *const right = get_irn_n(node, n_ia32_Test_right);
if (is_ia32_Immediate(right)) {
+ /* Emit the main opcode. */
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
- if (out->index == REG_EAX) {
- bemit8(0x3C);
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_Test_left);
+ /* Try to use the shorter al/ax/eax form. */
+ if (dst->index == REG_GP_EAX) {
+ bemit8(0xA8 | op);
} else {
- bemit8(0x80);
- bemit_modru(out, 7);
+ bemit8(0xF6 | op);
+ bemit_modru(dst, 0);
}
} else {
- bemit8(0x80);
- bemit_mod_am(7, node);
- }
- bemit8(get_ia32_immediate_attr_const(right)->offset);
- } else {
- const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
- bemit8(0x3A);
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
- bemit_modrr(out, in);
- } else {
- bemit_mod_am(reg_gp_map[out->index], node);
+ bemit8(0xF6 | op);
+ bemit_mod_am(0, node);
}
- }
-}
-static void bemit_test8bit(const ir_node *node)
-{
- ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
- if (is_ia32_Immediate(right)) {
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
- if (out->index == REG_EAX) {
- bemit8(0xA8);
- } else {
- bemit8(0xF6);
- bemit_modru(out, 0);
- }
- } else {
- bemit8(0xF6);
- bemit_mod_am(0, node);
+ /* Emit the immediate. */
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
+ switch (size) {
+ case 8: bemit8(attr->offset); break;
+ case 16: bemit16(attr->offset); break;
+ case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
}
- bemit8(get_ia32_immediate_attr_const(right)->offset);
} else {
- const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
- bemit8(0x84);
+ bemit8(0x84 | op);
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_Test_left);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
- bemit_modrr(out, in);
+ arch_register_t const *const src = arch_get_irn_register(right);
+ bemit_modrr(src, dst);
} else {
- bemit_mod_am(reg_gp_map[out->index], node);
+ bemit_mod_am(reg_gp_map[dst->index], node);
}
}
}
bemit32(imm);
}
} else {
- bemit8(0x0F);
- bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
+ bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
}
}
static void bemit_dec(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
bemit8(0x48 + reg_gp_map[out->index]);
}
static void bemit_inc(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
bemit8(0x40 + reg_gp_map[out->index]);
}
static void bemit_ldtls(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0x65); // gs:
- if (out->index == REG_EAX) {
+ if (out->index == REG_GP_EAX) {
bemit8(0xA1); // movl 0, %eax
} else {
bemit8(0x8B); // movl 0, %reg
*/
static void bemit_lea(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0x8D);
bemit_mod_am(reg_gp_map[out->index], node);
}
/* helper function for bemit_minus64bit */
static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
{
- if (src->index == REG_EAX) {
+ if (src->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
- } else if (dst->index == REG_EAX) {
+ } else if (dst->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
} else {
bemit8(0x87); // xchgl %src, %dst
static void bemit_minus64bit(const ir_node *node)
{
- const arch_register_t *in_lo = get_in_reg(node, 0);
- const arch_register_t *in_hi = get_in_reg(node, 1);
- const arch_register_t *out_lo = get_out_reg(node, 0);
- const arch_register_t *out_hi = get_out_reg(node, 1);
+ const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
+ const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
+ const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
+ const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
if (out_lo == in_lo) {
if (out_hi != in_hi) {
*/
static void bemit_load(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
- if (out->index == REG_EAX) {
+ if (out->index == REG_GP_EAX) {
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
if (!has_base && !has_index) {
ir_entity *ent = get_ia32_am_sc(node);
int offs = get_ia32_am_offs_int(node);
bemit_immediate(value, false);
}
} else {
- const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
- if (in->index == REG_EAX) {
+ if (in->index == REG_GP_EAX) {
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
if (!has_base && !has_index) {
ir_entity *ent = get_ia32_am_sc(node);
int offs = get_ia32_am_offs_int(node);
static void bemit_conv_i2i(const ir_node *node)
{
- ir_mode *smaller_mode = get_ia32_ls_mode(node);
- unsigned opcode;
-
- bemit8(0x0F);
/* 8 16 bit source
* movzx B6 B7
- * movsx BE BF
- */
- opcode = 0xB6;
+ * movsx BE BF */
+ ir_mode *const smaller_mode = get_ia32_ls_mode(node);
+ unsigned opcode = 0xB6;
if (mode_is_signed(smaller_mode)) opcode |= 0x08;
if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
- bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
+ bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
+}
+
+static void bemit_popcnt(ir_node const *const node)
+{
+ bemit8(0xF3);
+ bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
}
/**
bemit8(0xFF);
bemit_mod_am(6, node);
} else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
bemit8(0x50 + reg_gp_map[reg->index]);
}
}
*/
static void bemit_pop(const ir_node *node)
{
- const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
+ const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
bemit8(0x58 + reg_gp_map[reg->index]);
}
bemit_jmp(get_cfop_target_block(node));
}
-static void bemit_jcc(int pnc, const ir_node *dest_block)
+static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
{
unsigned char cc = pnc2cc(pnc);
bemit8(0x0F);
static void bemit_ia32_jcc(const ir_node *node)
{
- int pnc = get_ia32_condcode(node);
- const ir_node *proj_true;
- const ir_node *proj_false;
- const ir_node *dest_true;
- const ir_node *dest_false;
- const ir_node *block;
+ ia32_condition_code_t cc = get_ia32_condcode(node);
+ const ir_node *dest_true;
+ const ir_node *dest_false;
- pnc = determine_final_pnc(node, 0, pnc);
+ cc = determine_final_cc(node, 0, cc);
/* get both Projs */
- proj_true = get_proj(node, pn_ia32_Jcc_true);
+ ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
assert(proj_true && "Jcc without true Proj");
- proj_false = get_proj(node, pn_ia32_Jcc_false);
+ ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
assert(proj_false && "Jcc without false Proj");
- block = get_nodes_block(node);
-
if (can_be_fallthrough(proj_true)) {
/* exchange both proj's so the second one can be omitted */
const ir_node *t = proj_true;
proj_true = proj_false;
proj_false = t;
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
}
dest_true = get_cfop_target_block(proj_true);
dest_false = get_cfop_target_block(proj_false);
- if (pnc & ia32_pn_Cmp_float) {
+ if (cc & ia32_cc_float_parity_cases) {
/* Some floating point comparisons require a test of the parity flag,
* which indicates that the result is unordered */
- switch (pnc & 15) {
- case pn_Cmp_Uo: {
- bemit_jp(false, dest_true);
- break;
+ if (cc & ia32_cc_negated) {
+ bemit_jp(false, dest_true);
+ } else {
+ /* we need a local label if the false proj is a fallthrough
+ * as the falseblock might have no label emitted then */
+ if (can_be_fallthrough(proj_false)) {
+ bemit8(0x7A);
+ bemit8(0x06); // jp + 6
+ } else {
+ bemit_jp(false, dest_false);
}
-
- case pn_Cmp_Leg:
- bemit_jp(true, dest_true);
- break;
-
- case pn_Cmp_Eq:
- case pn_Cmp_Lt:
- case pn_Cmp_Le:
- /* we need a local label if the false proj is a fallthrough
- * as the falseblock might have no label emitted then */
- if (can_be_fallthrough(proj_false)) {
- bemit8(0x7A);
- bemit8(0x06); // jp + 6
- } else {
- bemit_jp(false, dest_false);
- }
- goto emit_jcc;
-
- case pn_Cmp_Ug:
- case pn_Cmp_Uge:
- case pn_Cmp_Ne:
- bemit_jp(false, dest_true);
- goto emit_jcc;
-
- default:
- goto emit_jcc;
}
- } else {
-emit_jcc:
- bemit_jcc(pnc, dest_true);
}
+ bemit_jcc(cc, dest_true);
/* the second Proj might be a fallthrough */
if (can_be_fallthrough(proj_false)) {
static void bemit_switchjmp(const ir_node *node)
{
- unsigned long interval;
- int last_value;
- int i;
- jmp_tbl_t tbl;
- const arch_register_t *in;
-
- /* fill the table structure */
- generate_jump_table(&tbl, node);
-
- /* two-complement's magic make this work without overflow */
- interval = tbl.max_value - tbl.min_value;
-
- in = get_in_reg(node, 0);
- /* emit the table */
- if (get_signed_imm_size(interval) == 1) {
- bemit8(0x83); // cmpl $imm8, %in
- bemit_modru(in, 7);
- bemit8(interval);
- } else {
- bemit8(0x81); // cmpl $imm32, %in
- bemit_modru(in, 7);
- bemit32(interval);
- }
- bemit8(0x0F); // ja tbl.defProj
- bemit8(0x87);
- ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
-
- if (tbl.num_branches > 1) {
- /* create table */
- bemit8(0xFF); // jmp *tbl.label(,%in,4)
- bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
- bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
- be_emit_irprintf("\t.long %s\n", tbl.label);
-
- be_gas_emit_switch_section(GAS_SECTION_RODATA);
- be_emit_cstring(".align 4\n");
- be_emit_irprintf("%s:\n", tbl.label);
-
- last_value = tbl.branches[0].value;
- for (i = 0; i != tbl.num_branches; ++i) {
- while (last_value != tbl.branches[i].value) {
- ia32_emitf(tbl.defProj, ".long %L\n");
- ++last_value;
- }
- ia32_emitf(tbl.branches[i].target, ".long %L\n");
- ++last_value;
- }
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- } else {
- /* one jump is enough */
- panic("switch only has one case");
- //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
- }
+ ir_entity *jump_table = get_ia32_am_sc(node);
+ const ir_switch_table *table = get_ia32_switch_table(node);
- be_emit_write_line();
+ bemit8(0xFF); // jmp *tbl.label(,%in,4)
+ bemit_mod_am(0x05, node);
- free(tbl.branches);
+ be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
}
/**
bemit_sub(node);
/* mov %esp, %out */
bemit8(0x8B);
- out = get_out_reg(node, 1);
+ out = arch_get_irn_register_out(node, 1);
bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
}
size = get_signed_imm_size(offs);
bemit8(size == 1 ? 0x83 : 0x81);
- reg = get_out_reg(node, 0);
+ reg = arch_get_irn_register_out(node, 0);
bemit_modru(reg, ext);
if (size == 1) {
}
}
-static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
+static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
{
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
if (get_ia32_op_type(node) == ia32_Normal) {
- const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
- const arch_register_t *in1 = x87_attr->x87[0];
- const arch_register_t *in = x87_attr->x87[1];
- const arch_register_t *out = x87_attr->x87[2];
-
- if (out == NULL) {
- out = in1;
- } else if (out == in) {
- in = in1;
- }
+ assert(!attr->pop || attr->res_in_reg);
- if (out->index == 0) {
- bemit8(0xD8);
- bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
- } else {
- bemit8(0xDC);
- bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
- }
+ unsigned char op0 = 0xD8;
+ if (attr->res_in_reg) op0 |= 0x04;
+ if (attr->pop) op0 |= 0x02;
+ bemit8(op0);
+
+ bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
} else {
- if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
- bemit8(0xD8);
- } else {
- bemit8(0xDC);
- }
- bemit_mod_am(code, node);
+ assert(!attr->reg);
+ assert(!attr->pop);
+
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ bemit8(size == 32 ? 0xD8 : 0xDC);
+ bemit_mod_am(op, node);
}
}
-static void bemit_fbinopp(const ir_node *node, unsigned const code)
+static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
{
- const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
- const arch_register_t *out = x87_attr->x87[2];
- bemit8(0xDE);
- bemit8(code + out->index);
+ bemit8(op0);
+ bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
}
static void bemit_fabs(const ir_node *node)
bemit_fbinop(node, 0, 0);
}
-static void bemit_faddp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xC0);
-}
-
static void bemit_fchs(const ir_node *node)
{
(void)node;
bemit_fbinop(node, 6, 7);
}
-static void bemit_fdivp(const ir_node *node)
+static void bemit_ffreep(ir_node const *const node)
{
- bemit_fbinopp(node, 0xF8);
-}
-
-static void bemit_fdivr(const ir_node *node)
-{
- bemit_fbinop(node, 7, 6);
-}
-
-static void bemit_fdivrp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xF0);
+ bemit_fop_reg(node, 0xDF, 0xC0);
}
static void bemit_fild(const ir_node *node)
static void bemit_fist(const ir_node *node)
{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 16:
- bemit8(0xDF); // fists
- break;
-
- case 32:
- bemit8(0xDB); // fistl
- break;
-
- default:
- panic("invalid mode size");
+ unsigned op;
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ switch (size) {
+ case 16: bemit8(0xDF); op = 2; break; // fist[p]s
+ case 32: bemit8(0xDB); op = 2; break; // fist[p]l
+ case 64: bemit8(0xDF); op = 6; break; // fistpll
+ default: panic("invalid mode size");
}
- bemit_mod_am(2, node);
+ if (get_ia32_x87_attr_const(node)->pop)
+ ++op;
+ // There is only a pop variant for 64 bit integer store.
+ assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
+ bemit_mod_am(op, node);
}
-static void bemit_fistp(const ir_node *node)
+static void bemit_fisttp(ir_node const *const node)
{
switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 16:
- bemit8(0xDF); // fistps
- bemit_mod_am(3, node);
- return;
-
- case 32:
- bemit8(0xDB); // fistpl
- bemit_mod_am(3, node);
- return;
-
- case 64:
- bemit8(0xDF); // fistpll
- bemit_mod_am(7, node);
- return;
-
- default:
- panic("invalid mode size");
+ case 16: bemit8(0xDF); break; // fisttps
+ case 32: bemit8(0xDB); break; // fisttpl
+ case 64: bemit8(0xDD); break; // fisttpll
+ default: panic("Invalid mode size");
}
+ bemit_mod_am(1, node);
}
static void bemit_fld(const ir_node *node)
bemit_fbinop(node, 1, 1);
}
-static void bemit_fmulp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xC8);
-}
-
static void bemit_fpop(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD);
- bemit8(0xD8 + attr->x87[0]->index);
+ bemit_fop_reg(node, 0xDD, 0xD8);
}
static void bemit_fpush(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xD9);
- bemit8(0xC0 + attr->x87[0]->index);
+ bemit_fop_reg(node, 0xD9, 0xC0);
}
static void bemit_fpushcopy(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xD9);
- bemit8(0xC0 + attr->x87[0]->index);
+ bemit_fop_reg(node, 0xD9, 0xC0);
}
static void bemit_fst(const ir_node *node)
{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 32:
- bemit8(0xD9); // fsts
- break;
-
- case 64:
- bemit8(0xDD); // fstl
- break;
-
- default:
- panic("invalid mode size");
- }
- bemit_mod_am(2, node);
-}
-
-static void bemit_fstp(const ir_node *node)
-{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 32:
- bemit8(0xD9); // fstps
- bemit_mod_am(3, node);
- return;
-
- case 64:
- bemit8(0xDD); // fstpl
- bemit_mod_am(3, node);
- return;
-
- case 80:
- case 96:
- bemit8(0xDB); // fstpt
- bemit_mod_am(7, node);
- return;
-
- default:
- panic("invalid mode size");
+ unsigned op;
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ switch (size) {
+ case 32: bemit8(0xD9); op = 2; break; // fst[p]s
+ case 64: bemit8(0xDD); op = 2; break; // fst[p]l
+ case 80:
+ case 96: bemit8(0xDB); op = 6; break; // fstpt
+ default: panic("invalid mode size");
}
+ if (get_ia32_x87_attr_const(node)->pop)
+ ++op;
+ // There is only a pop variant for long double store.
+ assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
+ bemit_mod_am(op, node);
}
static void bemit_fsub(const ir_node *node)
bemit_fbinop(node, 4, 5);
}
-static void bemit_fsubp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xE8);
-}
-
-static void bemit_fsubr(const ir_node *node)
-{
- bemit_fbinop(node, 5, 4);
-}
-
-static void bemit_fsubrp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xE0);
-}
-
static void bemit_fnstcw(const ir_node *node)
{
bemit8(0xD9); // fnstcw
static void bemit_fucomi(const ir_node *node)
{
const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDB); // fucomi
- bemit8(0xE8 + attr->x87[1]->index);
-}
-
-static void bemit_fucomip(const ir_node *node)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDF); // fucomip
- bemit8(0xE8 + attr->x87[1]->index);
+ bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
+ bemit8(0xE8 + attr->reg->index);
}
static void bemit_fucomfnstsw(const ir_node *node)
{
const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD); // fucom
- bemit8(0xE0 + attr->x87[1]->index);
- bemit_fnstsw();
-}
-
-static void bemit_fucompfnstsw(const ir_node *node)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD); // fucomp
- bemit8(0xE8 + attr->x87[1]->index);
+ bemit8(0xDD); // fucom[p]
+ bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
bemit_fnstsw();
}
static void bemit_fxch(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xD9);
- bemit8(0xC8 + attr->x87[0]->index);
-}
-
-/**
- * The type of a emitter function.
- */
-typedef void (*emit_func) (const ir_node *);
-
-/**
- * Set a node emitter. Make it a bit more type safe.
- */
-static void register_emitter(ir_op *op, emit_func func)
-{
- op->ops.generic = (op_func) func;
+ bemit_fop_reg(node, 0xD9, 0xC8);
}
static void ia32_register_binary_emitters(void)
{
/* first clear the generic function pointer for all ops */
- clear_irp_opcodes_generic_func();
+ ir_clear_opcodes_generic_func();
/* benode emitter */
- register_emitter(op_be_Copy, bemit_copy);
- register_emitter(op_be_CopyKeep, bemit_copy);
- register_emitter(op_be_IncSP, bemit_incsp);
- register_emitter(op_be_Perm, bemit_perm);
- register_emitter(op_be_Return, bemit_return);
- register_emitter(op_ia32_Adc, bemit_adc);
- register_emitter(op_ia32_Add, bemit_add);
- register_emitter(op_ia32_AddMem, bemit_addmem);
- register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
- register_emitter(op_ia32_And, bemit_and);
- register_emitter(op_ia32_AndMem, bemit_andmem);
- register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
- register_emitter(op_ia32_Breakpoint, bemit_int3);
- register_emitter(op_ia32_CMovcc, bemit_cmovcc);
- register_emitter(op_ia32_Call, bemit_call);
- register_emitter(op_ia32_Cltd, bemit_cltd);
- register_emitter(op_ia32_Cmc, bemit_cmc);
- register_emitter(op_ia32_Cmp, bemit_cmp);
- register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
- register_emitter(op_ia32_Const, bemit_mov_const);
- register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
- register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
- register_emitter(op_ia32_CopyB_i, bemit_copybi);
- register_emitter(op_ia32_Cwtl, bemit_cwtl);
- register_emitter(op_ia32_Dec, bemit_dec);
- register_emitter(op_ia32_DecMem, bemit_decmem);
- register_emitter(op_ia32_Div, bemit_div);
- register_emitter(op_ia32_FldCW, bemit_fldcw);
- register_emitter(op_ia32_FnstCW, bemit_fnstcw);
- register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
- register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
- register_emitter(op_ia32_Fucomi, bemit_fucomi);
- register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
- register_emitter(op_ia32_Fucompi, bemit_fucomip);
- register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
- register_emitter(op_ia32_IDiv, bemit_idiv);
- register_emitter(op_ia32_IJmp, bemit_ijmp);
- register_emitter(op_ia32_IMul, bemit_imul);
- register_emitter(op_ia32_IMul1OP, bemit_imul1op);
- register_emitter(op_ia32_Inc, bemit_inc);
- register_emitter(op_ia32_IncMem, bemit_incmem);
- register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
- register_emitter(op_ia32_Jmp, bemit_jump);
- register_emitter(op_ia32_LdTls, bemit_ldtls);
- register_emitter(op_ia32_Lea, bemit_lea);
- register_emitter(op_ia32_Leave, bemit_leave);
- register_emitter(op_ia32_Load, bemit_load);
- register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
- register_emitter(op_ia32_Mul, bemit_mul);
- register_emitter(op_ia32_Neg, bemit_neg);
- register_emitter(op_ia32_NegMem, bemit_negmem);
- register_emitter(op_ia32_Not, bemit_not);
- register_emitter(op_ia32_NotMem, bemit_notmem);
- register_emitter(op_ia32_Or, bemit_or);
- register_emitter(op_ia32_OrMem, bemit_ormem);
- register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
- register_emitter(op_ia32_Pop, bemit_pop);
- register_emitter(op_ia32_PopEbp, bemit_pop);
- register_emitter(op_ia32_PopMem, bemit_popmem);
- register_emitter(op_ia32_Push, bemit_push);
- register_emitter(op_ia32_RepPrefix, bemit_rep);
- register_emitter(op_ia32_Rol, bemit_rol);
- register_emitter(op_ia32_RolMem, bemit_rolmem);
- register_emitter(op_ia32_Ror, bemit_ror);
- register_emitter(op_ia32_RorMem, bemit_rormem);
- register_emitter(op_ia32_Sahf, bemit_sahf);
- register_emitter(op_ia32_Sar, bemit_sar);
- register_emitter(op_ia32_SarMem, bemit_sarmem);
- register_emitter(op_ia32_Sbb, bemit_sbb);
- register_emitter(op_ia32_Setcc, bemit_setcc);
- register_emitter(op_ia32_Shl, bemit_shl);
- register_emitter(op_ia32_ShlD, bemit_shld);
- register_emitter(op_ia32_ShlMem, bemit_shlmem);
- register_emitter(op_ia32_Shr, bemit_shr);
- register_emitter(op_ia32_ShrD, bemit_shrd);
- register_emitter(op_ia32_ShrMem, bemit_shrmem);
- register_emitter(op_ia32_Stc, bemit_stc);
- register_emitter(op_ia32_Store, bemit_store);
- register_emitter(op_ia32_Store8Bit, bemit_store);
- register_emitter(op_ia32_Sub, bemit_sub);
- register_emitter(op_ia32_SubMem, bemit_submem);
- register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
- register_emitter(op_ia32_SubSP, bemit_subsp);
- register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
- register_emitter(op_ia32_Test, bemit_test);
- register_emitter(op_ia32_Test8Bit, bemit_test8bit);
- register_emitter(op_ia32_Xor, bemit_xor);
- register_emitter(op_ia32_Xor0, bemit_xor0);
- register_emitter(op_ia32_XorMem, bemit_xormem);
- register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
- register_emitter(op_ia32_fabs, bemit_fabs);
- register_emitter(op_ia32_fadd, bemit_fadd);
- register_emitter(op_ia32_faddp, bemit_faddp);
- register_emitter(op_ia32_fchs, bemit_fchs);
- register_emitter(op_ia32_fdiv, bemit_fdiv);
- register_emitter(op_ia32_fdivp, bemit_fdivp);
- register_emitter(op_ia32_fdivr, bemit_fdivr);
- register_emitter(op_ia32_fdivrp, bemit_fdivrp);
- register_emitter(op_ia32_fild, bemit_fild);
- register_emitter(op_ia32_fist, bemit_fist);
- register_emitter(op_ia32_fistp, bemit_fistp);
- register_emitter(op_ia32_fld, bemit_fld);
- register_emitter(op_ia32_fld1, bemit_fld1);
- register_emitter(op_ia32_fldz, bemit_fldz);
- register_emitter(op_ia32_fmul, bemit_fmul);
- register_emitter(op_ia32_fmulp, bemit_fmulp);
- register_emitter(op_ia32_fpop, bemit_fpop);
- register_emitter(op_ia32_fpush, bemit_fpush);
- register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
- register_emitter(op_ia32_fst, bemit_fst);
- register_emitter(op_ia32_fstp, bemit_fstp);
- register_emitter(op_ia32_fsub, bemit_fsub);
- register_emitter(op_ia32_fsubp, bemit_fsubp);
- register_emitter(op_ia32_fsubr, bemit_fsubr);
- register_emitter(op_ia32_fsubrp, bemit_fsubrp);
- register_emitter(op_ia32_fxch, bemit_fxch);
+ be_set_emitter(op_be_Copy, bemit_copy);
+ be_set_emitter(op_be_CopyKeep, bemit_copy);
+ be_set_emitter(op_be_IncSP, bemit_incsp);
+ be_set_emitter(op_be_Perm, bemit_perm);
+ be_set_emitter(op_be_Return, bemit_return);
+ be_set_emitter(op_ia32_Adc, bemit_adc);
+ be_set_emitter(op_ia32_Add, bemit_add);
+ be_set_emitter(op_ia32_AddMem, bemit_addmem);
+ be_set_emitter(op_ia32_And, bemit_and);
+ be_set_emitter(op_ia32_AndMem, bemit_andmem);
+ be_set_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
+ be_set_emitter(op_ia32_Breakpoint, bemit_int3);
+ be_set_emitter(op_ia32_Bsf, bemit_bsf);
+ be_set_emitter(op_ia32_Bsr, bemit_bsr);
+ be_set_emitter(op_ia32_Bswap, bemit_bswap);
+ be_set_emitter(op_ia32_Bt, bemit_bt);
+ be_set_emitter(op_ia32_CMovcc, bemit_cmovcc);
+ be_set_emitter(op_ia32_Call, bemit_call);
+ be_set_emitter(op_ia32_Cltd, bemit_cltd);
+ be_set_emitter(op_ia32_Cmc, bemit_cmc);
+ be_set_emitter(op_ia32_Cmp, bemit_cmp);
+ be_set_emitter(op_ia32_Const, bemit_mov_const);
+ be_set_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
+ be_set_emitter(op_ia32_CopyB_i, bemit_copybi);
+ be_set_emitter(op_ia32_Cwtl, bemit_cwtl);
+ be_set_emitter(op_ia32_Dec, bemit_dec);
+ be_set_emitter(op_ia32_DecMem, bemit_decmem);
+ be_set_emitter(op_ia32_Div, bemit_div);
+ be_set_emitter(op_ia32_FldCW, bemit_fldcw);
+ be_set_emitter(op_ia32_FnstCW, bemit_fnstcw);
+ be_set_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
+ be_set_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
+ be_set_emitter(op_ia32_Fucomi, bemit_fucomi);
+ be_set_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
+ be_set_emitter(op_ia32_IDiv, bemit_idiv);
+ be_set_emitter(op_ia32_IJmp, bemit_ijmp);
+ be_set_emitter(op_ia32_IMul, bemit_imul);
+ be_set_emitter(op_ia32_IMul1OP, bemit_imul1op);
+ be_set_emitter(op_ia32_Inc, bemit_inc);
+ be_set_emitter(op_ia32_IncMem, bemit_incmem);
+ be_set_emitter(op_ia32_Jcc, bemit_ia32_jcc);
+ be_set_emitter(op_ia32_Jmp, bemit_jump);
+ be_set_emitter(op_ia32_LdTls, bemit_ldtls);
+ be_set_emitter(op_ia32_Lea, bemit_lea);
+ be_set_emitter(op_ia32_Leave, bemit_leave);
+ be_set_emitter(op_ia32_Load, bemit_load);
+ be_set_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
+ be_set_emitter(op_ia32_Mul, bemit_mul);
+ be_set_emitter(op_ia32_Neg, bemit_neg);
+ be_set_emitter(op_ia32_NegMem, bemit_negmem);
+ be_set_emitter(op_ia32_Not, bemit_not);
+ be_set_emitter(op_ia32_NotMem, bemit_notmem);
+ be_set_emitter(op_ia32_Or, bemit_or);
+ be_set_emitter(op_ia32_OrMem, bemit_ormem);
+ be_set_emitter(op_ia32_Pop, bemit_pop);
+ be_set_emitter(op_ia32_PopEbp, bemit_pop);
+ be_set_emitter(op_ia32_PopMem, bemit_popmem);
+ be_set_emitter(op_ia32_Popcnt, bemit_popcnt);
+ be_set_emitter(op_ia32_Push, bemit_push);
+ be_set_emitter(op_ia32_RepPrefix, bemit_rep);
+ be_set_emitter(op_ia32_Rol, bemit_rol);
+ be_set_emitter(op_ia32_RolMem, bemit_rolmem);
+ be_set_emitter(op_ia32_Ror, bemit_ror);
+ be_set_emitter(op_ia32_RorMem, bemit_rormem);
+ be_set_emitter(op_ia32_Sahf, bemit_sahf);
+ be_set_emitter(op_ia32_Sar, bemit_sar);
+ be_set_emitter(op_ia32_SarMem, bemit_sarmem);
+ be_set_emitter(op_ia32_Sbb, bemit_sbb);
+ be_set_emitter(op_ia32_Sbb0, bemit_sbb0);
+ be_set_emitter(op_ia32_Setcc, bemit_setcc);
+ be_set_emitter(op_ia32_Shl, bemit_shl);
+ be_set_emitter(op_ia32_ShlD, bemit_shld);
+ be_set_emitter(op_ia32_ShlMem, bemit_shlmem);
+ be_set_emitter(op_ia32_Shr, bemit_shr);
+ be_set_emitter(op_ia32_ShrD, bemit_shrd);
+ be_set_emitter(op_ia32_ShrMem, bemit_shrmem);
+ be_set_emitter(op_ia32_Stc, bemit_stc);
+ be_set_emitter(op_ia32_Store, bemit_store);
+ be_set_emitter(op_ia32_Sub, bemit_sub);
+ be_set_emitter(op_ia32_SubMem, bemit_submem);
+ be_set_emitter(op_ia32_SubSP, bemit_subsp);
+ be_set_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
+ be_set_emitter(op_ia32_Test, bemit_test);
+ be_set_emitter(op_ia32_Xor, bemit_xor);
+ be_set_emitter(op_ia32_Xor0, bemit_xor0);
+ be_set_emitter(op_ia32_XorMem, bemit_xormem);
+ be_set_emitter(op_ia32_fabs, bemit_fabs);
+ be_set_emitter(op_ia32_fadd, bemit_fadd);
+ be_set_emitter(op_ia32_fchs, bemit_fchs);
+ be_set_emitter(op_ia32_fdiv, bemit_fdiv);
+ be_set_emitter(op_ia32_ffreep, bemit_ffreep);
+ be_set_emitter(op_ia32_fild, bemit_fild);
+ be_set_emitter(op_ia32_fist, bemit_fist);
+ be_set_emitter(op_ia32_fisttp, bemit_fisttp);
+ be_set_emitter(op_ia32_fld, bemit_fld);
+ be_set_emitter(op_ia32_fld1, bemit_fld1);
+ be_set_emitter(op_ia32_fldz, bemit_fldz);
+ be_set_emitter(op_ia32_fmul, bemit_fmul);
+ be_set_emitter(op_ia32_fpop, bemit_fpop);
+ be_set_emitter(op_ia32_fpush, bemit_fpush);
+ be_set_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
+ be_set_emitter(op_ia32_fst, bemit_fst);
+ be_set_emitter(op_ia32_fsub, bemit_fsub);
+ be_set_emitter(op_ia32_fxch, bemit_fxch);
/* ignore the following nodes */
- register_emitter(op_ia32_ProduceVal, emit_Nothing);
- register_emitter(op_be_Barrier, emit_Nothing);
- register_emitter(op_be_Keep, emit_Nothing);
- register_emitter(op_be_Start, emit_Nothing);
- register_emitter(op_Phi, emit_Nothing);
- register_emitter(op_Start, emit_Nothing);
+ be_set_emitter(op_Phi, be_emit_nothing);
+ be_set_emitter(op_be_Keep, be_emit_nothing);
+ be_set_emitter(op_be_Start, be_emit_nothing);
+ be_set_emitter(op_ia32_ProduceVal, be_emit_nothing);
+ be_set_emitter(op_ia32_Unknown, be_emit_nothing);
}
static void gen_binary_block(ir_node *block)
{
- ir_node *node;
-
ia32_emit_block_header(block);
/* emit the contents of the block */
}
}
-void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
+void ia32_gen_binary_routine(ir_graph *irg)
{
- ir_entity *entity = get_irg_entity(irg);
- int i, n;
+ ir_entity *entity = get_irg_entity(irg);
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ ir_node **blk_sched = irg_data->blk_sched;
+ size_t i, n;
+ parameter_dbg_info_t *infos;
- cg = ia32_cg;
- isa = cg->isa;
+ isa = (ia32_isa_t*) arch_env;
ia32_register_binary_emitters();
- be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
+ infos = construct_parameter_infos(irg);
+ be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
+ NULL);
+ xfree(infos);
/* we use links to point to target blocks */
ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
/* initialize next block links */
- n = ARR_LEN(cg->blk_sched);
+ n = ARR_LEN(blk_sched);
for (i = 0; i < n; ++i) {
- ir_node *block = cg->blk_sched[i];
- ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
+ ir_node *block = blk_sched[i];
+ ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
set_irn_link(block, prev);
}
for (i = 0; i < n; ++i) {
- ir_node *block = cg->blk_sched[i];
+ ir_node *block = blk_sched[i];
gen_binary_block(block);
}
be_gas_emit_function_epilog(entity);
- be_dbg_method_end();
- be_emit_char('\n');
- be_emit_write_line();
ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
}
-
-
void ia32_init_emitter(void)
{
lc_opt_entry_t *be_grp;
projects / libfirm / blobdiff