/*
- * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
- *
* This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
*/
/**
#include "bedwarf.h"
#include "beemitter.h"
#include "begnuas.h"
-#include "beirg.h"
+#include "beutil.h"
#include "ia32_emitter.h"
#include "ia32_common_transform.h"
*/
static void emit_8bit_register(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
|| reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
- be_emit_char(reg_name[1]); /* get the basic name of the register */
+ be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('l');
}
*/
static void emit_8bit_register_high(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
|| reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
- be_emit_char(reg_name[1]); /* get the basic name of the register */
+ be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('h');
}
static void emit_16bit_register(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
-
be_emit_char('%');
- be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
+ be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
}
/**
*/
static void emit_register(const arch_register_t *reg, const ir_mode *mode)
{
- const char *reg_name;
-
if (mode != NULL) {
int size = get_mode_size_bits(mode);
switch (size) {
assert(mode_is_float(mode) || size == 32);
}
- reg_name = arch_register_get_name(reg);
-
be_emit_char('%');
- be_emit_string(reg_name);
+ be_emit_string(reg->name);
}
static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
case 'A': {
switch (*fmt++) {
case 'F':
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- goto emit_AM;
- } else {
- assert(get_ia32_op_type(node) == ia32_Normal);
- ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
- arch_register_t const *const in1 = x87_attr->x87[0];
- arch_register_t const * in = x87_attr->x87[1];
- arch_register_t const * out = x87_attr->x87[2];
- if (out == NULL) {
- out = in1;
- } else if (out == in) {
- in = in1;
- }
- be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
+ be_emit_irprintf(fmt, attr->reg->name);
break;
+ } else {
+ goto emit_AM;
}
emit_AM:
case 'R':
reg = va_arg(ap, const arch_register_t*);
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- goto emit_AM;
- } else {
+ if (get_ia32_op_type(node) == ia32_Normal) {
goto emit_R;
+ } else {
+ goto emit_AM;
}
case 'S':
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ goto emit_S;
+ } else {
++fmt;
goto emit_AM;
- } else {
- assert(get_ia32_op_type(node) == ia32_Normal);
- goto emit_S;
}
default: goto unknown;
if (is_ia32_Immediate(imm)) {
emit_ia32_Immediate(imm);
be_emit_cstring(", ");
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- ia32_emit_am(node);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ goto destination_operand;
} else {
- assert(get_ia32_op_type(node) == ia32_Normal);
- reg = arch_get_irn_register_in(node, n_ia32_binary_left);
- emit_register(reg, get_ia32_ls_mode(node));
+ ia32_emit_am(node);
}
} else {
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- ia32_emit_am(node);
- } else {
- assert(get_ia32_op_type(node) == ia32_Normal);
+ if (get_ia32_op_type(node) == ia32_Normal) {
reg = arch_get_irn_register_in(node, n_ia32_binary_right);
emit_register(reg, get_ia32_ls_mode(node));
+ } else {
+ ia32_emit_am(node);
}
be_emit_cstring(", ");
+destination_operand:
reg = arch_get_irn_register_in(node, n_ia32_binary_left);
emit_register(reg, get_ia32_ls_mode(node));
}
break;
case 'D':
- if (*fmt < '0' || '9' <= *fmt)
+ if (*fmt < '0' || '9' < *fmt)
goto unknown;
reg = arch_get_irn_register_out(node, *fmt++ - '0');
goto emit_R;
case 'F':
if (*fmt == 'M') {
- ++fmt;
ia32_emit_x87_mode_suffix(node);
+ } else if (*fmt == 'P') {
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ if (attr->pop)
+ be_emit_char('p');
+ } else if (*fmt == 'R') {
+ /* NOTE: Work around a gas quirk for non-commutative operations if the
+ * destination register is not %st0. In this case r/non-r is swapped.
+ * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
+ * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
+ * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
+ * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
+ * In fact this corresponds to the encoding of the instruction:
+ * - The r suffix selects whether %st0 is on the left (no r) or on the
+ * right (r) side of the executed operation.
+ * - The placement of %st0 selects whether the result is written to
+ * %st0 (right) or the other register (left).
+ * This means that it is sufficient to test whether the operands are
+ * permuted. In particular it is not necessary to consider wether the
+ * result is to be placed into the explicit register operand. */
+ if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
+ be_emit_char('r');
} else if (*fmt == 'X') {
- ++fmt;
ia32_emit_xmm_mode_suffix(node);
- } else if ('0' <= *fmt && *fmt <= '3') {
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ } else if (*fmt == '0') {
be_emit_char('%');
- be_emit_string(attr->x87[*fmt++ - '0']->name);
+ be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
} else {
goto unknown;
}
+ ++fmt;
break;
case 'I':
} else if ('0' <= *fmt && *fmt <= '9') {
cc = get_ia32_condcode(node);
cc = determine_final_cc(node, *fmt - '0', cc);
+ ++fmt;
} else {
goto unknown;
}
case 'S': {
unsigned pos;
- if (*fmt < '0' || '9' <= *fmt)
+ if (*fmt < '0' || '9' < *fmt)
goto unknown;
pos = *fmt++ - '0';
default:
unknown:
- panic("unknown format conversion in ia32_emitf()");
+ panic("unknown format conversion");
}
}
if (is_ia32_Sahf(flags)) {
ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
- if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
- || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
+ if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
inc_irg_visited(current_ir_graph);
cmp = find_original_value(cmp);
assert(cmp != NULL);
- assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
- || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
+ assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
}
flags_attr = get_ia32_attr_const(cmp);
be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
}
-/**
- * Returns the Proj with projection number proj and NOT mode_M
- */
-static ir_node *get_proj(const ir_node *node, long proj)
-{
- ir_node *src;
-
- assert(get_irn_mode(node) == mode_T && "expected mode_T node");
-
- foreach_out_edge(node, edge) {
- src = get_edge_src_irn(edge);
-
- assert(is_Proj(src) && "Proj expected");
- if (get_irn_mode(src) == mode_M)
- continue;
-
- if (get_Proj_proj(src) == proj)
- return src;
- }
- return NULL;
-}
-
static int can_be_fallthrough(const ir_node *node)
{
ir_node *target_block = get_cfop_target_block(node);
{
int need_parity_label = 0;
ia32_condition_code_t cc = get_ia32_condcode(node);
- const ir_node *proj_true;
- const ir_node *proj_false;
cc = determine_final_cc(node, 0, cc);
/* get both Projs */
- proj_true = get_proj(node, pn_ia32_Jcc_true);
+ ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
assert(proj_true && "Jcc without true Proj");
- proj_false = get_proj(node, pn_ia32_Jcc_false);
+ ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
assert(proj_false && "Jcc without false Proj");
if (can_be_fallthrough(proj_true)) {
case 0:
ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
be_emit_char('%');
- return s + 1;
+ return s;
+
case '%':
be_emit_char('%');
return s + 1;
return s;
}
+ /* Emit the register. */
if (asm_reg->memory) {
be_emit_char('(');
- }
-
- /* emit it */
- if (modifier != 0) {
+ emit_register(reg, NULL);
+ be_emit_char(')');
+ } else {
switch (modifier) {
- case 'b':
- emit_8bit_register(reg);
- break;
- case 'h':
- emit_8bit_register_high(reg);
- break;
- case 'w':
- emit_16bit_register(reg);
- break;
- default:
- panic("Invalid asm op modifier");
+ case '\0': emit_register(reg, asm_reg->mode); break;
+ case 'b': emit_8bit_register(reg); break;
+ case 'h': emit_8bit_register_high(reg); break;
+ case 'w': emit_16bit_register(reg); break;
+ default: panic("Invalid asm op modifier");
}
- } else {
- emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
- }
-
- if (asm_reg->memory) {
- be_emit_char(')');
}
return s;
if (in == out) {
return;
}
- /* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
ia32_emitf(node, "movl %R, %R", in, out);
static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
- const arch_register_class_t *cls0, *cls1;
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
- cls0 = arch_register_get_class(in0);
- cls1 = arch_register_get_class(in1);
-
- assert(cls0 == cls1 && "Register class mismatch at Perm");
+ arch_register_class_t const *const cls0 = in0->reg_class;
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
ia32_emitf(node, "xchg %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
}
}
-static void emit_Nothing(const ir_node *node)
-{
- (void) node;
-}
-
/**
* Enters the emitter functions for handled nodes into the generic
*/
static void ia32_register_emitters(void)
{
-#define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
-#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
-#define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
-#define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
-#define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
+#define IA32_EMIT(a) be_set_emitter(op_ia32_##a, emit_ia32_##a)
+#define EMIT(a) be_set_emitter(op_##a, emit_##a)
+#define IGN(a) be_set_emitter(op_##a, be_emit_nothing)
+#define BE_EMIT(a) be_set_emitter(op_be_##a, emit_be_##a)
+#define BE_IGN(a) be_set_emitter(op_be_##a, be_emit_nothing)
/* first clear the generic function pointer for all ops */
ir_clear_opcodes_generic_func();
#undef IA32_EMIT
}
-typedef void (*emit_func_ptr) (const ir_node *);
-
/**
* Assign and emit an exception label if the current instruction can fail.
*/
*/
static void ia32_emit_node(ir_node *node)
{
- ir_op *op = get_irn_op(node);
-
DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
if (is_ia32_irn(node)) {
}
}
}
- if (op->ops.generic) {
- emit_func_ptr func = (emit_func_ptr) op->ops.generic;
- be_dwarf_location(get_irn_dbg_info(node));
-
- (*func) (node);
- } else {
- emit_Nothing(node);
- ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
- abort();
- }
+ be_emit_node(node);
if (sp_relative) {
int sp_change = arch_get_sp_bias(node);
static int should_align_block(const ir_node *block)
{
static const double DELTA = .0001;
- ir_graph *irg = get_irn_irg(block);
- ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
- ir_node *prev = get_prev_block_sched(block);
- double block_freq;
- double prev_freq = 0; /**< execfreq of the fallthrough block */
- double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
- int i, n_cfgpreds;
-
- if (exec_freq == NULL)
- return 0;
+ ir_node *prev = get_prev_block_sched(block);
+ double prev_freq = 0; /**< execfreq of the fallthrough block */
+ double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
+ double block_freq;
+ int i, n_cfgpreds;
+
if (ia32_cg_config.label_alignment_factor <= 0)
return 0;
- block_freq = get_block_execfreq(exec_freq, block);
+ block_freq = get_block_execfreq(block);
if (block_freq < DELTA)
return 0;
n_cfgpreds = get_Block_n_cfgpreds(block);
for (i = 0; i < n_cfgpreds; ++i) {
const ir_node *pred = get_Block_cfgpred_block(block, i);
- double pred_freq = get_block_execfreq(exec_freq, pred);
+ double pred_freq = get_block_execfreq(pred);
if (pred == prev) {
prev_freq += pred_freq;
*/
static void ia32_emit_block_header(ir_node *block)
{
- ir_graph *irg = current_ir_graph;
- int need_label = block_needs_label(block);
-
+ ir_graph *const irg = get_Block_irg(block);
if (block == get_irg_end_block(irg))
return;
}
}
+ int const need_label = block_needs_label(block);
be_gas_begin_block(block, need_label);
}
return cc & 0xf;
}
-/** Sign extension bit values for binops */
-enum SignExt {
- UNSIGNED_IMM = 0, /**< unsigned immediate */
- SIGNEXT_IMM = 2, /**< sign extended immediate */
+enum OpSize {
+ OP_8 = 0x00, /* 8bit operation. */
+ OP_16_32 = 0x01, /* 16/32bit operation. */
+ OP_MEM_SRC = 0x02, /* The memory operand is in the soruce position. */
+ OP_IMM8 = 0x02, /* 8bit immediate, which gets sign extended for 16/32bit operation. */
+ OP_16_32_IMM8 = 0x03, /* 16/32bit operation with sign extended 8bit immediate. */
+ OP_EAX = 0x04, /* Short form of instruction with al/ax/eax as operand. */
};
/** The mod encoding of the ModR/M */
}
}
-/**
- * Emit a binop with a immediate operand.
- *
- * @param node the node to emit
- * @param opcode_eax the opcode for the op eax, imm variant
- * @param opcode the opcode for the reg, imm variant
- * @param ruval the opcode extension for opcode
- */
-static void bemit_binop_with_imm(
- const ir_node *node,
- unsigned char opcode_ax,
- unsigned char opcode, unsigned char ruval)
-{
- /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
- const ir_node *op = get_irn_n(node, n_ia32_binary_right);
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
- unsigned size;
-
- /* Some instructions (test) have no short form with 32bit value + 8bit
- * immediate. */
- if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
- size = 4;
- } else {
- /* check for sign extension */
- size = get_signed_imm_size(attr->offset);
- }
-
- switch (size) {
- case 1:
- bemit8(opcode | SIGNEXT_IMM);
- /* cmp has this special mode */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit_mod_am(ruval, node);
- } else {
- const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
- bemit_modru(reg, ruval);
- }
- bemit8((unsigned char)attr->offset);
- return;
- case 2:
- case 4:
- /* check for eax variant: this variant is shorter for 32bit immediates only */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit8(opcode);
- bemit_mod_am(ruval, node);
- } else {
- const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
- if (reg->index == REG_GP_EAX) {
- bemit8(opcode_ax);
- } else {
- bemit8(opcode);
- bemit_modru(reg, ruval);
- }
- }
- bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
- return;
- }
- panic("invalid imm size?!?");
-}
-
-/**
- * Emits a binop.
- */
-static void bemit_binop_2(const ir_node *node, unsigned code)
-{
- const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
- bemit8(code);
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
- bemit_modrr(op2, out);
- } else {
- bemit_mod_am(reg_gp_map[out->index], node);
- }
-}
-
-/**
- * Emit a binop.
- */
-static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
-{
- ir_node *right = get_irn_n(node, n_ia32_binary_right);
- if (is_ia32_Immediate(right)) {
- bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
- } else {
- bemit_binop_2(node, opcodes[0]);
- }
-}
-
/**
* Emit an unop.
*/
bemit_mod_am(ext, node);
}
+static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
+{
+ bemit8(0x0F);
+ bemit_unop_reg(node, code, input);
+}
+
static void bemit_immediate(const ir_node *node, bool relative)
{
const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
if (in == out)
return;
- /* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
- assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
+ assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
bemit8(0x8B);
bemit_modrr(in, out);
}
{
const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
- const arch_register_class_t *cls0 = arch_register_get_class(in0);
+ const arch_register_class_t *cls0 = in0->reg_class;
- assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
if (in0->index == REG_GP_EAX) {
//ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
//ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
//ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
}
/**
- * Creates a function for a Binop with 3 possible encodings.
+ * Emit a binop.
*/
-#define BINOP(op, op0, op1, op2, op2_ext) \
-static void bemit_ ## op(const ir_node *node) { \
- static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
- bemit_binop(node, op ## _codes); \
-}
-
-/* insn def eax,imm imm */
-BINOP(add, 0x03, 0x05, 0x81, 0)
-BINOP(or, 0x0B, 0x0D, 0x81, 1)
-BINOP(adc, 0x13, 0x15, 0x81, 2)
-BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
-BINOP(and, 0x23, 0x25, 0x81, 4)
-BINOP(sub, 0x2B, 0x2D, 0x81, 5)
-BINOP(xor, 0x33, 0x35, 0x81, 6)
-BINOP(test, 0x85, 0xA9, 0xF7, 0)
-
-#define BINOPMEM(op, ext) \
-static void bemit_##op(const ir_node *node) \
-{ \
- ir_node *val; \
- unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
- if (size == 16) \
- bemit8(0x66); \
- val = get_irn_n(node, n_ia32_unary_op); \
- if (is_ia32_Immediate(val)) { \
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
- int offset = attr->offset; \
- if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
- bemit8(0x83); \
- bemit_mod_am(ext, node); \
- bemit8(offset); \
- } else { \
- bemit8(0x81); \
- bemit_mod_am(ext, node); \
- if (size == 16) { \
- bemit16(offset); \
- } else { \
- bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
- } \
- } \
- } else { \
- bemit8(ext << 3 | 1); \
- bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
- } \
-} \
- \
-static void bemit_##op##8bit(const ir_node *node) \
-{ \
- ir_node *val = get_irn_n(node, n_ia32_unary_op); \
- if (is_ia32_Immediate(val)) { \
- bemit8(0x80); \
- bemit_mod_am(ext, node); \
- bemit8(get_ia32_immediate_attr_const(val)->offset); \
- } else { \
- bemit8(ext << 3); \
- bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
- } \
+static void bemit_binop(ir_node const *const node, unsigned const code)
+{
+ ir_mode *const ls_mode = get_ia32_ls_mode(node);
+ unsigned size = ls_mode ? get_mode_size_bits(ls_mode) : 32;
+ if (size == 16)
+ bemit8(0x66);
+
+ unsigned op = size == 8 ? OP_8 : OP_16_32;
+ ir_node *const right = get_irn_n(node, n_ia32_binary_right);
+ if (is_ia32_Immediate(right)) {
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
+ /* Try to use the short form with 8bit sign extended immediate. */
+ if (op != OP_8 && !attr->symconst && get_signed_imm_size(attr->offset) == 1) {
+ op = OP_16_32_IMM8;
+ size = 8;
+ }
+
+ /* Emit the main opcode. */
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_binary_left);
+ /* Try to use the shorter al/ax/eax form. */
+ if (dst->index == REG_GP_EAX && op != OP_16_32_IMM8) {
+ bemit8(code << 3 | OP_EAX | op);
+ } else {
+ bemit8(0x80 | op);
+ bemit_modru(dst, code);
+ }
+ } else {
+ bemit8(0x80 | op);
+ bemit_mod_am(code, node);
+ }
+
+ /* Emit the immediate. */
+ switch (size) {
+ case 8: bemit8(attr->offset); break;
+ case 16: bemit16(attr->offset); break;
+ case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
+ }
+ } else {
+ bemit8(code << 3 | OP_MEM_SRC | op);
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_binary_left);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ arch_register_t const *const src = arch_get_irn_register(right);
+ bemit_modrr(src, dst);
+ } else {
+ bemit_mod_am(reg_gp_map[dst->index], node);
+ }
+ }
}
+/**
+ * Create a function for a binop.
+ */
+#define BINOP(op, code) \
+ static void bemit_##op(ir_node const *const node) \
+ { \
+ bemit_binop(node, code); \
+ }
+
+/* insn opcode */
+BINOP(add, 0)
+BINOP(or, 1)
+BINOP(adc, 2)
+BINOP(sbb, 3)
+BINOP(and, 4)
+BINOP(sub, 5)
+BINOP(xor, 6)
+BINOP(cmp, 7)
+
+static void bemit_binop_mem(ir_node const *const node, unsigned const code)
+{
+ unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
+ if (size == 16)
+ bemit8(0x66);
+
+ unsigned op = size == 8 ? OP_8 : OP_16_32;
+ ir_node *const val = get_irn_n(node, n_ia32_unary_op);
+ if (is_ia32_Immediate(val)) {
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(val);
+ /* Try to use the short form with 8bit sign extended immediate. */
+ if (op != OP_8 && !attr->symconst && get_signed_imm_size(attr->offset) == 1) {
+ op = OP_16_32_IMM8;
+ size = 8;
+ }
+
+ /* Emit the main opcode. */
+ bemit8(0x80 | op);
+ bemit_mod_am(code, node);
+
+ /* Emit the immediate. */
+ switch (size) {
+ case 8: bemit8(attr->offset); break;
+ case 16: bemit16(attr->offset); break;
+ case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
+ }
+ } else {
+ bemit8(code << 3 | op);
+ bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node);
+ }
+}
+
+#define BINOPMEM(op, code) \
+ static void bemit_##op(ir_node const *const node) \
+ { \
+ bemit_binop_mem(node, code); \
+ }
+
BINOPMEM(addmem, 0)
BINOPMEM(ormem, 1)
BINOPMEM(andmem, 4)
}
}
+static void bemit_sbb0(ir_node const *const node)
+{
+ arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
+ unsigned char const reg = reg_gp_map[out->index];
+ bemit8(0x1B);
+ bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
+}
+
/**
* binary emitter for setcc.
*/
}
}
+static void bemit_bsf(ir_node const *const node)
+{
+ bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
+}
+
+static void bemit_bsr(ir_node const *const node)
+{
+ bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
+}
+
+static void bemit_bswap(ir_node const *const node)
+{
+ bemit8(0x0F);
+ bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
+}
+
+static void bemit_bt(ir_node const *const node)
+{
+ bemit8(0x0F);
+ arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
+ ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
+ if (is_ia32_Immediate(right)) {
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
+ int const offset = attr->offset;
+ assert(!attr->symconst);
+ assert(get_signed_imm_size(offset) == 1);
+ bemit8(0xBA);
+ bemit_modru(lreg, 4);
+ bemit8(offset);
+ } else {
+ bemit8(0xA3);
+ bemit_modrr(lreg, arch_get_irn_register(right));
+ }
+}
+
static void bemit_cmovcc(const ir_node *node)
{
const ia32_attr_t *attr = get_ia32_attr_const(node);
}
}
-static void bemit_cmp(const ir_node *node)
+static void bemit_test(ir_node const *const node)
{
- unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
- ir_node *right;
-
- if (ls_size == 16)
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ if (size == 16)
bemit8(0x66);
- right = get_irn_n(node, n_ia32_binary_right);
- if (is_ia32_Immediate(right)) {
- /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
- const ir_node *op = get_irn_n(node, n_ia32_binary_right);
- const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
- unsigned size;
-
- if (attr->symconst != NULL) {
- size = 4;
- } else {
- /* check for sign extension */
- size = get_signed_imm_size(attr->offset);
- }
-
- switch (size) {
- case 1:
- bemit8(0x81 | SIGNEXT_IMM);
- /* cmp has this special mode */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit_mod_am(7, node);
- } else {
- const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
- bemit_modru(reg, 7);
- }
- bemit8((unsigned char)attr->offset);
- return;
- case 2:
- case 4:
- /* check for eax variant: this variant is shorter for 32bit immediates only */
- if (get_ia32_op_type(node) == ia32_AddrModeS) {
- bemit8(0x81);
- bemit_mod_am(7, node);
- } else {
- const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
- if (reg->index == REG_GP_EAX) {
- bemit8(0x3D);
- } else {
- bemit8(0x81);
- bemit_modru(reg, 7);
- }
- }
- if (ls_size == 16) {
- bemit16(attr->offset);
- } else {
- bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
- }
- return;
- }
- panic("invalid imm size?!?");
- } else {
- const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
- bemit8(0x3B);
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
- bemit_modrr(op2, out);
- } else {
- bemit_mod_am(reg_gp_map[out->index], node);
- }
- }
-}
-
-static void bemit_cmp8bit(const ir_node *node)
-{
- ir_node *right = get_irn_n(node, n_ia32_binary_right);
+ unsigned const op = size == 8 ? OP_8 : OP_16_32;
+ ir_node *const right = get_irn_n(node, n_ia32_Test_right);
if (is_ia32_Immediate(right)) {
+ /* Emit the main opcode. */
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
- if (out->index == REG_GP_EAX) {
- bemit8(0x3C);
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_Test_left);
+ /* Try to use the shorter al/ax/eax form. */
+ if (dst->index == REG_GP_EAX) {
+ bemit8(0xA8 | op);
} else {
- bemit8(0x80);
- bemit_modru(out, 7);
+ bemit8(0xF6 | op);
+ bemit_modru(dst, 0);
}
} else {
- bemit8(0x80);
- bemit_mod_am(7, node);
- }
- bemit8(get_ia32_immediate_attr_const(right)->offset);
- } else {
- const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
- bemit8(0x3A);
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
- bemit_modrr(out, in);
- } else {
- bemit_mod_am(reg_gp_map[out->index], node);
+ bemit8(0xF6 | op);
+ bemit_mod_am(0, node);
}
- }
-}
-static void bemit_test8bit(const ir_node *node)
-{
- ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
- if (is_ia32_Immediate(right)) {
- if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
- if (out->index == REG_GP_EAX) {
- bemit8(0xA8);
- } else {
- bemit8(0xF6);
- bemit_modru(out, 0);
- }
- } else {
- bemit8(0xF6);
- bemit_mod_am(0, node);
+ /* Emit the immediate. */
+ ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
+ switch (size) {
+ case 8: bemit8(attr->offset); break;
+ case 16: bemit16(attr->offset); break;
+ case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
}
- bemit8(get_ia32_immediate_attr_const(right)->offset);
} else {
- const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
- bemit8(0x84);
+ bemit8(0x84 | op);
+ arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_Test_left);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
- bemit_modrr(out, in);
+ arch_register_t const *const src = arch_get_irn_register(right);
+ bemit_modrr(src, dst);
} else {
- bemit_mod_am(reg_gp_map[out->index], node);
+ bemit_mod_am(reg_gp_map[dst->index], node);
}
}
}
bemit32(imm);
}
} else {
- bemit8(0x0F);
- bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
+ bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
}
}
static void bemit_conv_i2i(const ir_node *node)
{
- ir_mode *smaller_mode = get_ia32_ls_mode(node);
- unsigned opcode;
-
- bemit8(0x0F);
/* 8 16 bit source
* movzx B6 B7
- * movsx BE BF
- */
- opcode = 0xB6;
+ * movsx BE BF */
+ ir_mode *const smaller_mode = get_ia32_ls_mode(node);
+ unsigned opcode = 0xB6;
if (mode_is_signed(smaller_mode)) opcode |= 0x08;
if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
- bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
+ bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
+}
+
+static void bemit_popcnt(ir_node const *const node)
+{
+ bemit8(0xF3);
+ bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
}
/**
static void bemit_ia32_jcc(const ir_node *node)
{
ia32_condition_code_t cc = get_ia32_condcode(node);
- const ir_node *proj_true;
- const ir_node *proj_false;
const ir_node *dest_true;
const ir_node *dest_false;
cc = determine_final_cc(node, 0, cc);
/* get both Projs */
- proj_true = get_proj(node, pn_ia32_Jcc_true);
+ ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
assert(proj_true && "Jcc without true Proj");
- proj_false = get_proj(node, pn_ia32_Jcc_false);
+ ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
assert(proj_false && "Jcc without false Proj");
if (can_be_fallthrough(proj_true)) {
}
}
-static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
+static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
{
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
if (get_ia32_op_type(node) == ia32_Normal) {
- const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
- const arch_register_t *in1 = x87_attr->x87[0];
- const arch_register_t *in = x87_attr->x87[1];
- const arch_register_t *out = x87_attr->x87[2];
-
- if (out == NULL) {
- out = in1;
- } else if (out == in) {
- in = in1;
- }
+ assert(!attr->pop || attr->res_in_reg);
- if (out->index == 0) {
- bemit8(0xD8);
- bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
- } else {
- bemit8(0xDC);
- bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
- }
+ unsigned char op0 = 0xD8;
+ if (attr->res_in_reg) op0 |= 0x04;
+ if (attr->pop) op0 |= 0x02;
+ bemit8(op0);
+
+ bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
} else {
- if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
- bemit8(0xD8);
- } else {
- bemit8(0xDC);
- }
- bemit_mod_am(code, node);
+ assert(!attr->reg);
+ assert(!attr->pop);
+
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ bemit8(size == 32 ? 0xD8 : 0xDC);
+ bemit_mod_am(op, node);
}
}
-static void bemit_fbinopp(const ir_node *node, unsigned const code)
+static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
{
- const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
- const arch_register_t *out = x87_attr->x87[2];
- bemit8(0xDE);
- bemit8(code + out->index);
+ bemit8(op0);
+ bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
}
static void bemit_fabs(const ir_node *node)
bemit_fbinop(node, 0, 0);
}
-static void bemit_faddp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xC0);
-}
-
static void bemit_fchs(const ir_node *node)
{
(void)node;
bemit_fbinop(node, 6, 7);
}
-static void bemit_fdivp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xF8);
-}
-
-static void bemit_fdivr(const ir_node *node)
-{
- bemit_fbinop(node, 7, 6);
-}
-
-static void bemit_fdivrp(const ir_node *node)
+static void bemit_ffreep(ir_node const *const node)
{
- bemit_fbinopp(node, 0xF0);
+ bemit_fop_reg(node, 0xDF, 0xC0);
}
static void bemit_fild(const ir_node *node)
static void bemit_fist(const ir_node *node)
{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 16:
- bemit8(0xDF); // fists
- break;
-
- case 32:
- bemit8(0xDB); // fistl
- break;
-
- default:
- panic("invalid mode size");
+ unsigned op;
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ switch (size) {
+ case 16: bemit8(0xDF); op = 2; break; // fist[p]s
+ case 32: bemit8(0xDB); op = 2; break; // fist[p]l
+ case 64: bemit8(0xDF); op = 6; break; // fistpll
+ default: panic("invalid mode size");
}
- bemit_mod_am(2, node);
+ if (get_ia32_x87_attr_const(node)->pop)
+ ++op;
+ // There is only a pop variant for 64 bit integer store.
+ assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
+ bemit_mod_am(op, node);
}
-static void bemit_fistp(const ir_node *node)
+static void bemit_fisttp(ir_node const *const node)
{
switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 16:
- bemit8(0xDF); // fistps
- bemit_mod_am(3, node);
- return;
-
- case 32:
- bemit8(0xDB); // fistpl
- bemit_mod_am(3, node);
- return;
-
- case 64:
- bemit8(0xDF); // fistpll
- bemit_mod_am(7, node);
- return;
-
- default:
- panic("invalid mode size");
+ case 16: bemit8(0xDF); break; // fisttps
+ case 32: bemit8(0xDB); break; // fisttpl
+ case 64: bemit8(0xDD); break; // fisttpll
+ default: panic("Invalid mode size");
}
+ bemit_mod_am(1, node);
}
static void bemit_fld(const ir_node *node)
bemit_fbinop(node, 1, 1);
}
-static void bemit_fmulp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xC8);
-}
-
static void bemit_fpop(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD);
- bemit8(0xD8 + attr->x87[0]->index);
+ bemit_fop_reg(node, 0xDD, 0xD8);
}
static void bemit_fpush(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xD9);
- bemit8(0xC0 + attr->x87[0]->index);
+ bemit_fop_reg(node, 0xD9, 0xC0);
}
static void bemit_fpushcopy(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xD9);
- bemit8(0xC0 + attr->x87[0]->index);
+ bemit_fop_reg(node, 0xD9, 0xC0);
}
static void bemit_fst(const ir_node *node)
{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 32:
- bemit8(0xD9); // fsts
- break;
-
- case 64:
- bemit8(0xDD); // fstl
- break;
-
- default:
- panic("invalid mode size");
- }
- bemit_mod_am(2, node);
-}
-
-static void bemit_fstp(const ir_node *node)
-{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 32:
- bemit8(0xD9); // fstps
- bemit_mod_am(3, node);
- return;
-
- case 64:
- bemit8(0xDD); // fstpl
- bemit_mod_am(3, node);
- return;
-
- case 80:
- case 96:
- bemit8(0xDB); // fstpt
- bemit_mod_am(7, node);
- return;
-
- default:
- panic("invalid mode size");
+ unsigned op;
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ switch (size) {
+ case 32: bemit8(0xD9); op = 2; break; // fst[p]s
+ case 64: bemit8(0xDD); op = 2; break; // fst[p]l
+ case 80:
+ case 96: bemit8(0xDB); op = 6; break; // fstpt
+ default: panic("invalid mode size");
}
+ if (get_ia32_x87_attr_const(node)->pop)
+ ++op;
+ // There is only a pop variant for long double store.
+ assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
+ bemit_mod_am(op, node);
}
static void bemit_fsub(const ir_node *node)
bemit_fbinop(node, 4, 5);
}
-static void bemit_fsubp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xE8);
-}
-
-static void bemit_fsubr(const ir_node *node)
-{
- bemit_fbinop(node, 5, 4);
-}
-
-static void bemit_fsubrp(const ir_node *node)
-{
- bemit_fbinopp(node, 0xE0);
-}
-
static void bemit_fnstcw(const ir_node *node)
{
bemit8(0xD9); // fnstcw
static void bemit_fucomi(const ir_node *node)
{
const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDB); // fucomi
- bemit8(0xE8 + attr->x87[1]->index);
-}
-
-static void bemit_fucomip(const ir_node *node)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDF); // fucomip
- bemit8(0xE8 + attr->x87[1]->index);
+ bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
+ bemit8(0xE8 + attr->reg->index);
}
static void bemit_fucomfnstsw(const ir_node *node)
{
const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD); // fucom
- bemit8(0xE0 + attr->x87[1]->index);
- bemit_fnstsw();
-}
-
-static void bemit_fucompfnstsw(const ir_node *node)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD); // fucomp
- bemit8(0xE8 + attr->x87[1]->index);
+ bemit8(0xDD); // fucom[p]
+ bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
bemit_fnstsw();
}
static void bemit_fxch(const ir_node *node)
{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xD9);
- bemit8(0xC8 + attr->x87[0]->index);
-}
-
-/**
- * The type of a emitter function.
- */
-typedef void (*emit_func) (const ir_node *);
-
-/**
- * Set a node emitter. Make it a bit more type safe.
- */
-static void register_emitter(ir_op *op, emit_func func)
-{
- op->ops.generic = (op_func) func;
+ bemit_fop_reg(node, 0xD9, 0xC8);
}
static void ia32_register_binary_emitters(void)
ir_clear_opcodes_generic_func();
/* benode emitter */
- register_emitter(op_be_Copy, bemit_copy);
- register_emitter(op_be_CopyKeep, bemit_copy);
- register_emitter(op_be_IncSP, bemit_incsp);
- register_emitter(op_be_Perm, bemit_perm);
- register_emitter(op_be_Return, bemit_return);
- register_emitter(op_ia32_Adc, bemit_adc);
- register_emitter(op_ia32_Add, bemit_add);
- register_emitter(op_ia32_AddMem, bemit_addmem);
- register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
- register_emitter(op_ia32_And, bemit_and);
- register_emitter(op_ia32_AndMem, bemit_andmem);
- register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
- register_emitter(op_ia32_Breakpoint, bemit_int3);
- register_emitter(op_ia32_CMovcc, bemit_cmovcc);
- register_emitter(op_ia32_Call, bemit_call);
- register_emitter(op_ia32_Cltd, bemit_cltd);
- register_emitter(op_ia32_Cmc, bemit_cmc);
- register_emitter(op_ia32_Cmp, bemit_cmp);
- register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
- register_emitter(op_ia32_Const, bemit_mov_const);
- register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
- register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
- register_emitter(op_ia32_CopyB_i, bemit_copybi);
- register_emitter(op_ia32_Cwtl, bemit_cwtl);
- register_emitter(op_ia32_Dec, bemit_dec);
- register_emitter(op_ia32_DecMem, bemit_decmem);
- register_emitter(op_ia32_Div, bemit_div);
- register_emitter(op_ia32_FldCW, bemit_fldcw);
- register_emitter(op_ia32_FnstCW, bemit_fnstcw);
- register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
- register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
- register_emitter(op_ia32_Fucomi, bemit_fucomi);
- register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
- register_emitter(op_ia32_Fucompi, bemit_fucomip);
- register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
- register_emitter(op_ia32_IDiv, bemit_idiv);
- register_emitter(op_ia32_IJmp, bemit_ijmp);
- register_emitter(op_ia32_IMul, bemit_imul);
- register_emitter(op_ia32_IMul1OP, bemit_imul1op);
- register_emitter(op_ia32_Inc, bemit_inc);
- register_emitter(op_ia32_IncMem, bemit_incmem);
- register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
- register_emitter(op_ia32_Jmp, bemit_jump);
- register_emitter(op_ia32_LdTls, bemit_ldtls);
- register_emitter(op_ia32_Lea, bemit_lea);
- register_emitter(op_ia32_Leave, bemit_leave);
- register_emitter(op_ia32_Load, bemit_load);
- register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
- register_emitter(op_ia32_Mul, bemit_mul);
- register_emitter(op_ia32_Neg, bemit_neg);
- register_emitter(op_ia32_NegMem, bemit_negmem);
- register_emitter(op_ia32_Not, bemit_not);
- register_emitter(op_ia32_NotMem, bemit_notmem);
- register_emitter(op_ia32_Or, bemit_or);
- register_emitter(op_ia32_OrMem, bemit_ormem);
- register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
- register_emitter(op_ia32_Pop, bemit_pop);
- register_emitter(op_ia32_PopEbp, bemit_pop);
- register_emitter(op_ia32_PopMem, bemit_popmem);
- register_emitter(op_ia32_Push, bemit_push);
- register_emitter(op_ia32_RepPrefix, bemit_rep);
- register_emitter(op_ia32_Rol, bemit_rol);
- register_emitter(op_ia32_RolMem, bemit_rolmem);
- register_emitter(op_ia32_Ror, bemit_ror);
- register_emitter(op_ia32_RorMem, bemit_rormem);
- register_emitter(op_ia32_Sahf, bemit_sahf);
- register_emitter(op_ia32_Sar, bemit_sar);
- register_emitter(op_ia32_SarMem, bemit_sarmem);
- register_emitter(op_ia32_Sbb, bemit_sbb);
- register_emitter(op_ia32_Setcc, bemit_setcc);
- register_emitter(op_ia32_Shl, bemit_shl);
- register_emitter(op_ia32_ShlD, bemit_shld);
- register_emitter(op_ia32_ShlMem, bemit_shlmem);
- register_emitter(op_ia32_Shr, bemit_shr);
- register_emitter(op_ia32_ShrD, bemit_shrd);
- register_emitter(op_ia32_ShrMem, bemit_shrmem);
- register_emitter(op_ia32_Stc, bemit_stc);
- register_emitter(op_ia32_Store, bemit_store);
- register_emitter(op_ia32_Store8Bit, bemit_store);
- register_emitter(op_ia32_Sub, bemit_sub);
- register_emitter(op_ia32_SubMem, bemit_submem);
- register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
- register_emitter(op_ia32_SubSP, bemit_subsp);
- register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
- register_emitter(op_ia32_Test, bemit_test);
- register_emitter(op_ia32_Test8Bit, bemit_test8bit);
- register_emitter(op_ia32_Xor, bemit_xor);
- register_emitter(op_ia32_Xor0, bemit_xor0);
- register_emitter(op_ia32_XorMem, bemit_xormem);
- register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
- register_emitter(op_ia32_fabs, bemit_fabs);
- register_emitter(op_ia32_fadd, bemit_fadd);
- register_emitter(op_ia32_faddp, bemit_faddp);
- register_emitter(op_ia32_fchs, bemit_fchs);
- register_emitter(op_ia32_fdiv, bemit_fdiv);
- register_emitter(op_ia32_fdivp, bemit_fdivp);
- register_emitter(op_ia32_fdivr, bemit_fdivr);
- register_emitter(op_ia32_fdivrp, bemit_fdivrp);
- register_emitter(op_ia32_fild, bemit_fild);
- register_emitter(op_ia32_fist, bemit_fist);
- register_emitter(op_ia32_fistp, bemit_fistp);
- register_emitter(op_ia32_fld, bemit_fld);
- register_emitter(op_ia32_fld1, bemit_fld1);
- register_emitter(op_ia32_fldz, bemit_fldz);
- register_emitter(op_ia32_fmul, bemit_fmul);
- register_emitter(op_ia32_fmulp, bemit_fmulp);
- register_emitter(op_ia32_fpop, bemit_fpop);
- register_emitter(op_ia32_fpush, bemit_fpush);
- register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
- register_emitter(op_ia32_fst, bemit_fst);
- register_emitter(op_ia32_fstp, bemit_fstp);
- register_emitter(op_ia32_fsub, bemit_fsub);
- register_emitter(op_ia32_fsubp, bemit_fsubp);
- register_emitter(op_ia32_fsubr, bemit_fsubr);
- register_emitter(op_ia32_fsubrp, bemit_fsubrp);
- register_emitter(op_ia32_fxch, bemit_fxch);
+ be_set_emitter(op_be_Copy, bemit_copy);
+ be_set_emitter(op_be_CopyKeep, bemit_copy);
+ be_set_emitter(op_be_IncSP, bemit_incsp);
+ be_set_emitter(op_be_Perm, bemit_perm);
+ be_set_emitter(op_be_Return, bemit_return);
+ be_set_emitter(op_ia32_Adc, bemit_adc);
+ be_set_emitter(op_ia32_Add, bemit_add);
+ be_set_emitter(op_ia32_AddMem, bemit_addmem);
+ be_set_emitter(op_ia32_And, bemit_and);
+ be_set_emitter(op_ia32_AndMem, bemit_andmem);
+ be_set_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
+ be_set_emitter(op_ia32_Breakpoint, bemit_int3);
+ be_set_emitter(op_ia32_Bsf, bemit_bsf);
+ be_set_emitter(op_ia32_Bsr, bemit_bsr);
+ be_set_emitter(op_ia32_Bswap, bemit_bswap);
+ be_set_emitter(op_ia32_Bt, bemit_bt);
+ be_set_emitter(op_ia32_CMovcc, bemit_cmovcc);
+ be_set_emitter(op_ia32_Call, bemit_call);
+ be_set_emitter(op_ia32_Cltd, bemit_cltd);
+ be_set_emitter(op_ia32_Cmc, bemit_cmc);
+ be_set_emitter(op_ia32_Cmp, bemit_cmp);
+ be_set_emitter(op_ia32_Const, bemit_mov_const);
+ be_set_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
+ be_set_emitter(op_ia32_CopyB_i, bemit_copybi);
+ be_set_emitter(op_ia32_Cwtl, bemit_cwtl);
+ be_set_emitter(op_ia32_Dec, bemit_dec);
+ be_set_emitter(op_ia32_DecMem, bemit_decmem);
+ be_set_emitter(op_ia32_Div, bemit_div);
+ be_set_emitter(op_ia32_FldCW, bemit_fldcw);
+ be_set_emitter(op_ia32_FnstCW, bemit_fnstcw);
+ be_set_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
+ be_set_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
+ be_set_emitter(op_ia32_Fucomi, bemit_fucomi);
+ be_set_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
+ be_set_emitter(op_ia32_IDiv, bemit_idiv);
+ be_set_emitter(op_ia32_IJmp, bemit_ijmp);
+ be_set_emitter(op_ia32_IMul, bemit_imul);
+ be_set_emitter(op_ia32_IMul1OP, bemit_imul1op);
+ be_set_emitter(op_ia32_Inc, bemit_inc);
+ be_set_emitter(op_ia32_IncMem, bemit_incmem);
+ be_set_emitter(op_ia32_Jcc, bemit_ia32_jcc);
+ be_set_emitter(op_ia32_Jmp, bemit_jump);
+ be_set_emitter(op_ia32_LdTls, bemit_ldtls);
+ be_set_emitter(op_ia32_Lea, bemit_lea);
+ be_set_emitter(op_ia32_Leave, bemit_leave);
+ be_set_emitter(op_ia32_Load, bemit_load);
+ be_set_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
+ be_set_emitter(op_ia32_Mul, bemit_mul);
+ be_set_emitter(op_ia32_Neg, bemit_neg);
+ be_set_emitter(op_ia32_NegMem, bemit_negmem);
+ be_set_emitter(op_ia32_Not, bemit_not);
+ be_set_emitter(op_ia32_NotMem, bemit_notmem);
+ be_set_emitter(op_ia32_Or, bemit_or);
+ be_set_emitter(op_ia32_OrMem, bemit_ormem);
+ be_set_emitter(op_ia32_Pop, bemit_pop);
+ be_set_emitter(op_ia32_PopEbp, bemit_pop);
+ be_set_emitter(op_ia32_PopMem, bemit_popmem);
+ be_set_emitter(op_ia32_Popcnt, bemit_popcnt);
+ be_set_emitter(op_ia32_Push, bemit_push);
+ be_set_emitter(op_ia32_RepPrefix, bemit_rep);
+ be_set_emitter(op_ia32_Rol, bemit_rol);
+ be_set_emitter(op_ia32_RolMem, bemit_rolmem);
+ be_set_emitter(op_ia32_Ror, bemit_ror);
+ be_set_emitter(op_ia32_RorMem, bemit_rormem);
+ be_set_emitter(op_ia32_Sahf, bemit_sahf);
+ be_set_emitter(op_ia32_Sar, bemit_sar);
+ be_set_emitter(op_ia32_SarMem, bemit_sarmem);
+ be_set_emitter(op_ia32_Sbb, bemit_sbb);
+ be_set_emitter(op_ia32_Sbb0, bemit_sbb0);
+ be_set_emitter(op_ia32_Setcc, bemit_setcc);
+ be_set_emitter(op_ia32_Shl, bemit_shl);
+ be_set_emitter(op_ia32_ShlD, bemit_shld);
+ be_set_emitter(op_ia32_ShlMem, bemit_shlmem);
+ be_set_emitter(op_ia32_Shr, bemit_shr);
+ be_set_emitter(op_ia32_ShrD, bemit_shrd);
+ be_set_emitter(op_ia32_ShrMem, bemit_shrmem);
+ be_set_emitter(op_ia32_Stc, bemit_stc);
+ be_set_emitter(op_ia32_Store, bemit_store);
+ be_set_emitter(op_ia32_Sub, bemit_sub);
+ be_set_emitter(op_ia32_SubMem, bemit_submem);
+ be_set_emitter(op_ia32_SubSP, bemit_subsp);
+ be_set_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
+ be_set_emitter(op_ia32_Test, bemit_test);
+ be_set_emitter(op_ia32_Xor, bemit_xor);
+ be_set_emitter(op_ia32_Xor0, bemit_xor0);
+ be_set_emitter(op_ia32_XorMem, bemit_xormem);
+ be_set_emitter(op_ia32_fabs, bemit_fabs);
+ be_set_emitter(op_ia32_fadd, bemit_fadd);
+ be_set_emitter(op_ia32_fchs, bemit_fchs);
+ be_set_emitter(op_ia32_fdiv, bemit_fdiv);
+ be_set_emitter(op_ia32_ffreep, bemit_ffreep);
+ be_set_emitter(op_ia32_fild, bemit_fild);
+ be_set_emitter(op_ia32_fist, bemit_fist);
+ be_set_emitter(op_ia32_fisttp, bemit_fisttp);
+ be_set_emitter(op_ia32_fld, bemit_fld);
+ be_set_emitter(op_ia32_fld1, bemit_fld1);
+ be_set_emitter(op_ia32_fldz, bemit_fldz);
+ be_set_emitter(op_ia32_fmul, bemit_fmul);
+ be_set_emitter(op_ia32_fpop, bemit_fpop);
+ be_set_emitter(op_ia32_fpush, bemit_fpush);
+ be_set_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
+ be_set_emitter(op_ia32_fst, bemit_fst);
+ be_set_emitter(op_ia32_fsub, bemit_fsub);
+ be_set_emitter(op_ia32_fxch, bemit_fxch);
/* ignore the following nodes */
- register_emitter(op_ia32_ProduceVal, emit_Nothing);
- register_emitter(op_be_Keep, emit_Nothing);
- register_emitter(op_be_Start, emit_Nothing);
- register_emitter(op_Phi, emit_Nothing);
- register_emitter(op_Start, emit_Nothing);
+ be_set_emitter(op_Phi, be_emit_nothing);
+ be_set_emitter(op_be_Keep, be_emit_nothing);
+ be_set_emitter(op_be_Start, be_emit_nothing);
+ be_set_emitter(op_ia32_ProduceVal, be_emit_nothing);
+ be_set_emitter(op_ia32_Unknown, be_emit_nothing);
}
static void gen_binary_block(ir_node *block)
projects / libfirm / blobdiff