*/
static void emit_8bit_register(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
|| reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
- be_emit_char(reg_name[1]); /* get the basic name of the register */
+ be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('l');
}
*/
static void emit_8bit_register_high(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
|| reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
be_emit_char('%');
- be_emit_char(reg_name[1]); /* get the basic name of the register */
+ be_emit_char(reg->name[1]); /* get the basic name of the register */
be_emit_char('h');
}
static void emit_16bit_register(const arch_register_t *reg)
{
- const char *reg_name = arch_register_get_name(reg);
-
be_emit_char('%');
- be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
+ be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
}
/**
*/
static void emit_register(const arch_register_t *reg, const ir_mode *mode)
{
- const char *reg_name;
-
if (mode != NULL) {
int size = get_mode_size_bits(mode);
switch (size) {
assert(mode_is_float(mode) || size == 32);
}
- reg_name = arch_register_get_name(reg);
-
be_emit_char('%');
- be_emit_string(reg_name);
+ be_emit_string(reg->name);
}
static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
goto emit_AM;
} else {
assert(get_ia32_op_type(node) == ia32_Normal);
- ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
- arch_register_t const *const out = x87_attr->x87[2];
- arch_register_t const * in = x87_attr->x87[1];
- if (out == in)
- in = x87_attr->x87[0];
- be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
+ ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
+ char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
+ be_emit_irprintf(fmt, attr->reg->name);
break;
}
case 'F':
if (*fmt == 'M') {
- ++fmt;
ia32_emit_x87_mode_suffix(node);
} else if (*fmt == 'P') {
- ++fmt;
ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
if (attr->pop)
be_emit_char('p');
} else if (*fmt == 'R') {
- ++fmt;
/* NOTE: Work around a gas quirk for non-commutative operations if the
* destination register is not %st0. In this case r/non-r is swapped.
* %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
* right (r) side of the executed operation.
* - The placement of %st0 selects whether the result is written to
* %st0 (right) or the other register (left).
- * This results in testing whether the left operand register is %st0
- * instead of the expected test whether the output register equals the
- * left operand register. */
- ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
- if (get_ia32_op_type(node) == ia32_Normal ?
- attr->x87[0] != &ia32_registers[REG_ST0] :
- attr->attr.data.ins_permuted)
+ * This means that it is sufficient to test whether the operands are
+ * permuted. In particular it is not necessary to consider wether the
+ * result is to be placed into the explicit register operand. */
+ if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
be_emit_char('r');
} else if (*fmt == 'X') {
- ++fmt;
ia32_emit_xmm_mode_suffix(node);
- } else if ('0' <= *fmt && *fmt <= '2') {
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ } else if (*fmt == '0') {
be_emit_char('%');
- be_emit_string(attr->x87[*fmt++ - '0']->name);
+ be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
} else {
goto unknown;
}
+ ++fmt;
break;
case 'I':
if (is_ia32_Sahf(flags)) {
ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
- if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
- || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
+ if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
inc_irg_visited(current_ir_graph);
cmp = find_original_value(cmp);
assert(cmp != NULL);
- assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
- || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
+ assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
}
flags_attr = get_ia32_attr_const(cmp);
if (in == out) {
return;
}
- /* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
ia32_emitf(node, "movl %R, %R", in, out);
static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
- const arch_register_class_t *cls0, *cls1;
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
- cls0 = arch_register_get_class(in0);
- cls1 = arch_register_get_class(in1);
-
- assert(cls0 == cls1 && "Register class mismatch at Perm");
+ arch_register_class_t const *const cls0 = in0->reg_class;
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
ia32_emitf(node, "xchg %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
if (in == out)
return;
- /* copies of vf nodes aren't real... */
- if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
- assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
+ assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
bemit8(0x8B);
bemit_modrr(in, out);
}
{
const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
- const arch_register_class_t *cls0 = arch_register_get_class(in0);
+ const arch_register_class_t *cls0 = in0->reg_class;
- assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
+ assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
if (in0->index == REG_GP_EAX) {
//ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
//ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
//ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
{
ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
- arch_register_t const *const st0 = &ia32_registers[REG_ST0];
+ unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
if (get_ia32_op_type(node) == ia32_Normal) {
- arch_register_t const *const out = attr->x87[2];
- assert(out == attr->x87[0] || out == attr->x87[1]);
- assert(!attr->attr.data.ins_permuted);
+ assert(!attr->pop || attr->res_in_reg);
unsigned char op0 = 0xD8;
- if (out != st0) op0 |= 0x04;
- if (attr->pop) op0 |= 0x02;
+ if (attr->res_in_reg) op0 |= 0x04;
+ if (attr->pop) op0 |= 0x02;
bemit8(op0);
- unsigned op = op_rev;
- arch_register_t const *reg = attr->x87[0];
- if (reg == st0) {
- op = op_fwd;
- reg = attr->x87[1];
- }
- bemit8(MOD_REG | ENC_REG(op) | ENC_RM(reg->index));
+ bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
} else {
- assert(attr->x87[2] == st0);
+ assert(!attr->reg);
assert(!attr->pop);
unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
bemit8(size == 32 ? 0xD8 : 0xDC);
- bemit_mod_am(attr->attr.data.ins_permuted ? op_rev : op_fwd, node);
+ bemit_mod_am(op, node);
}
}
static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
{
bemit8(op0);
- bemit8(op1 + get_ia32_x87_attr_const(node)->x87[0]->index);
+ bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
}
static void bemit_fabs(const ir_node *node)
static void bemit_fist(const ir_node *node)
{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 16:
- bemit8(0xDF); // fists
- break;
-
- case 32:
- bemit8(0xDB); // fistl
- break;
-
- default:
- panic("invalid mode size");
- }
- bemit_mod_am(2, node);
-}
-
-static void bemit_fistp(const ir_node *node)
-{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 16:
- bemit8(0xDF); // fistps
- bemit_mod_am(3, node);
- return;
-
- case 32:
- bemit8(0xDB); // fistpl
- bemit_mod_am(3, node);
- return;
-
- case 64:
- bemit8(0xDF); // fistpll
- bemit_mod_am(7, node);
- return;
-
- default:
- panic("invalid mode size");
+ unsigned op;
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ switch (size) {
+ case 16: bemit8(0xDF); op = 2; break; // fist[p]s
+ case 32: bemit8(0xDB); op = 2; break; // fist[p]l
+ case 64: bemit8(0xDF); op = 6; break; // fistpll
+ default: panic("invalid mode size");
}
+ if (get_ia32_x87_attr_const(node)->pop)
+ ++op;
+ // There is only a pop variant for 64 bit integer store.
+ assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
+ bemit_mod_am(op, node);
}
static void bemit_fisttp(ir_node const *const node)
static void bemit_fst(const ir_node *node)
{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 32:
- bemit8(0xD9); // fsts
- break;
-
- case 64:
- bemit8(0xDD); // fstl
- break;
-
- default:
- panic("invalid mode size");
- }
- bemit_mod_am(2, node);
-}
-
-static void bemit_fstp(const ir_node *node)
-{
- switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
- case 32:
- bemit8(0xD9); // fstps
- bemit_mod_am(3, node);
- return;
-
- case 64:
- bemit8(0xDD); // fstpl
- bemit_mod_am(3, node);
- return;
-
- case 80:
- case 96:
- bemit8(0xDB); // fstpt
- bemit_mod_am(7, node);
- return;
-
- default:
- panic("invalid mode size");
+ unsigned op;
+ unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
+ switch (size) {
+ case 32: bemit8(0xD9); op = 2; break; // fst[p]s
+ case 64: bemit8(0xDD); op = 2; break; // fst[p]l
+ case 80:
+ case 96: bemit8(0xDB); op = 6; break; // fstpt
+ default: panic("invalid mode size");
}
+ if (get_ia32_x87_attr_const(node)->pop)
+ ++op;
+ // There is only a pop variant for long double store.
+ assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
+ bemit_mod_am(op, node);
}
static void bemit_fsub(const ir_node *node)
static void bemit_fucomi(const ir_node *node)
{
const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDB); // fucomi
- bemit8(0xE8 + attr->x87[1]->index);
-}
-
-static void bemit_fucomip(const ir_node *node)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDF); // fucomip
- bemit8(0xE8 + attr->x87[1]->index);
+ bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
+ bemit8(0xE8 + attr->reg->index);
}
static void bemit_fucomfnstsw(const ir_node *node)
{
const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD); // fucom
- bemit8(0xE0 + attr->x87[1]->index);
- bemit_fnstsw();
-}
-
-static void bemit_fucompfnstsw(const ir_node *node)
-{
- const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
- bemit8(0xDD); // fucomp
- bemit8(0xE8 + attr->x87[1]->index);
+ bemit8(0xDD); // fucom[p]
+ bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
bemit_fnstsw();
}
register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
register_emitter(op_ia32_Fucomi, bemit_fucomi);
- register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
- register_emitter(op_ia32_Fucompi, bemit_fucomip);
register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
register_emitter(op_ia32_IDiv, bemit_idiv);
register_emitter(op_ia32_IJmp, bemit_ijmp);
register_emitter(op_ia32_ffreep, bemit_ffreep);
register_emitter(op_ia32_fild, bemit_fild);
register_emitter(op_ia32_fist, bemit_fist);
- register_emitter(op_ia32_fistp, bemit_fistp);
register_emitter(op_ia32_fisttp, bemit_fisttp);
register_emitter(op_ia32_fld, bemit_fld);
register_emitter(op_ia32_fld1, bemit_fld1);
register_emitter(op_ia32_fpush, bemit_fpush);
register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
register_emitter(op_ia32_fst, bemit_fst);
- register_emitter(op_ia32_fstp, bemit_fstp);
register_emitter(op_ia32_fsub, bemit_fsub);
register_emitter(op_ia32_fxch, bemit_fxch);
projects / libfirm / blobdiff