if (in == out) {
return;
}
- /* copies of vf nodes aren't real... */
- if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
ia32_emitf(node, "movl %R, %R", in, out);
ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);
if (in == out)
return;
- /* copies of vf nodes aren't real... */
- if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+ /* copies of fp nodes aren't real... */
+ if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
return;
assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
//ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
//ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
//ia32_emitf(node, "xorpd %R, %R", in1, in0);
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* is a NOP */
- } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+ } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)", node);