/**
* This file implements the node emitter.
- *
+ * @author Christian Wuerdig
* $Id$
*/
#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
#include "ia32_map_regs.h"
+#include "bearch_ia32_t.h"
#define BLOCK_PREFIX(x) ".L" x
*/
void ia32_switch_section(FILE *F, section_t sec) {
static section_t curr_sec = NO_SECTION;
- static const char *text[ASM_MAX][SECTION_MAX] = {
+ static const char *text[ASM_MAX][SECTION_MAX] = {
{
".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
},
* |_| |_|
*************************************************************/
+static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
+ return \
+ REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
+ REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
+ REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
+}
+
/**
* returns true if a node has x87 registers
*/
-static int has_x87_register(const ir_node *n) {
+static INLINE int has_x87_register(const ir_node *n) {
return is_irn_machine_user(n, 0);
}
reg = &ia32_xmm_regs[REG_XMM0];
else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
reg = &ia32_vfp_regs[REG_VF0];
- else if (REGS_ARE_EQUAL(reg, &ia32_st_regs[REG_ST_UKNWN]))
- reg = &ia32_st_regs[REG_ST0];
return reg;
}
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
int nr = occ->width - 1;
- if (!X)
+ if (! irn)
return lc_appendable_snadd(app, "(null)", 6);
- buf = get_ia32_reg_name(X, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
+ buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
/* append the stupid % to register names */
lc_appendable_chadd(app, '%');
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
int nr = occ->width - 1;
ia32_attr_t *attr;
- if (!X)
+ if (! irn)
return lc_appendable_snadd(app, "(null)", 6);
- attr = get_ia32_attr(X);
+ attr = get_ia32_attr(irn);
buf = attr->x87[nr]->name;
lc_appendable_chadd(app, '%');
return lc_appendable_snadd(app, buf, strlen(buf));
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
- if (!X)
+ if (! irn)
return lc_arg_append(app, occ, "(null)", 6);
if (occ->conversion == 'C') {
- buf = get_ia32_cnst(X);
+ buf = get_ia32_cnst(irn);
}
else { /* 'O' */
- buf = get_ia32_am_offs(X);
+ buf = get_ia32_am_offs(irn);
}
return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
static int ia32_get_mode_suffix(lc_appendable_t *app,
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
- ir_node *X = arg->v_ptr;
- ir_mode *mode = get_irn_mode(X);
+ ir_node *irn = arg->v_ptr;
+ ir_mode *mode = get_irn_mode(irn);
if (mode == mode_T) {
- mode = is_ia32_AddrModeS(X) || is_ia32_AddrModeD(X) ? get_ia32_ls_mode(X) : get_ia32_res_mode(X);
+ mode = (is_ia32_Ld(irn) || is_ia32_St(irn)) ? get_ia32_ls_mode(irn) : get_ia32_res_mode(irn);
}
- if (!X)
+ if (! irn)
return lc_arg_append(app, occ, "(null)", 6);
if (mode_is_float(mode)) {
return env;
}
-static char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
+static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
switch(get_mode_size_bits(mode)) {
case 8:
return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
/**
* Emits registers and/or address mode of a binary operation.
*/
-char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
/* verify that this function is never called on non-AM supporting operations */
is_ia32_Store8Bit(n) || \
is_ia32_CondJmp(n) || \
is_ia32_xCondJmp(n) || \
+ is_ia32_CmpSet(n) || \
+ is_ia32_xCmpSet(n) || \
is_ia32_SwitchJmp(n)))
if (! buf) {
switch(get_ia32_op_type(n)) {
case ia32_Normal:
- if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ if (is_ia32_ImmConst(n)) {
lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
}
+ else if (is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
+ }
else {
const arch_register_t *in1 = get_in_reg(n, 2);
const arch_register_t *in2 = get_in_reg(n, 3);
get_ia32_cnst(n)); /* tell the assembler to store it's address. */
}
else {
- const arch_register_t *in1 = get_in_reg(n, 2);
- ir_mode *mode = get_ia32_res_mode(n);
- const char *in_name;
+ const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
+ ir_mode *mode = get_ia32_res_mode(n);
+ const char *in_name;
mode = mode ? mode : get_ia32_ls_mode(n);
in_name = ia32_get_reg_name_for_mode(env, mode, in1);
return buf;
}
+/**
+ * Returns the xxx PTR string for a given mode
+ *
+ * @param mode the mode
+ * @param x87_insn if non-zero returns the string for a x87 instruction
+ * else for a SSE instruction
+ */
+static const char *pointer_size(ir_mode *mode, int x87_insn)
+{
+ if (mode) {
+ switch (get_mode_size_bits(mode)) {
+ case 8: return "BYTE PTR";
+ case 16: return "WORD PTR";
+ case 32: return "DWORD PTR";
+ case 64:
+ if (x87_insn)
+ return "QWORD PTR";
+ return NULL;
+ case 80:
+ case 96: return "XWORD PTR";
+ default: return NULL;
+ }
+ }
+ return NULL;
+}
+
/**
* Emits registers and/or address mode of a binary operation.
*/
-char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
/* verify that this function is never called on non-AM supporting operations */
switch(get_ia32_op_type(n)) {
case ia32_Normal:
if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+ ir_mode *mode = get_ia32_ls_mode(n);
+ const char *p = pointer_size(mode, 1);
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
}
else {
ia32_attr_t *attr = get_ia32_attr(n);
assert(0 && "unsupported op type");
}
-#undef PRODUCES_RESULT
-
return buf;
}
/**
* Emits registers and/or address mode of a unary operation.
*/
-char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
if (! buf) {
lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
}
else {
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
+ if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
+ /* MulS and Mulh implicitly multiply by EAX */
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
+ }
+ else
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
}
break;
- case ia32_am_Dest:
- snprintf(buf, SNPRINTF_BUF_LEN, ia32_emit_am(n, env));
+ case ia32_AddrModeD:
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+ break;
+ case ia32_AddrModeS:
+ /*
+ Mulh is emitted via emit_unop
+ imul [MEM] means EDX:EAX <- EAX * [MEM]
+ */
+ assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
break;
default:
assert(0 && "unsupported op type");
/**
* Emits address mode.
*/
-char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
int had_output = 0;
- char *s;
- int size;
+ char *s;
+ const char *p;
static struct obstack *obst = NULL;
ir_mode *mode = get_ia32_ls_mode(n);
/* obstack_free with NULL results in an uninitialized obstack */
obstack_init(obst);
- if (mode) {
- switch (get_mode_size_bits(mode)) {
- case 8:
- obstack_printf(obst, "BYTE PTR ");
- break;
- case 16:
- obstack_printf(obst, "WORD PTR ");
- break;
- case 32:
- obstack_printf(obst, "DWORD PTR ");
- break;
- case 64:
- if (has_x87_register(n))
- /* ARGHHH: stupid gas x87 wants QWORD PTR but SSE must be WITHOUT */
- obstack_printf(obst, "QWORD PTR ");
- break;
- case 80:
- case 96:
- obstack_printf(obst, "XWORD PTR ");
- break;
- default:
- break;
- }
- }
+ p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
+ if (p)
+ obstack_printf(obst, "%s ", p);
/* emit address mode symconst */
if (get_ia32_am_sc(n)) {
if (had_output)
obstack_printf(obst, "] ");
- size = obstack_object_size(obst);
- s = obstack_finish(obst);
- s[size - 1] = '\0';
+ obstack_1grow(obst, '\0');
+ s = obstack_finish(obst);
return s;
}
+/**
+ * emit an address
+ */
+const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
+{
+ static char buf[SNPRINTF_BUF_LEN];
+ ir_mode *mode = get_ia32_ls_mode(irn);
+ const char *adr = get_ia32_cnst(irn);
+ const char *pref = pointer_size(mode, has_x87_register(irn));
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
+ return buf;
+}
/**
* Formated print of commands and comments.
{ "ne", pn_Cmp_Lg }, /* != */
{ "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
{ "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
- { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
- { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
- { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
- { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
- { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
- { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
+ { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
+ { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
+ { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
+ { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
+ { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
+ { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
{ NULL, pn_Cmp_True }, /* always true */
};
{ "ne", pn_Cmp_Lg }, /* != */
{ "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
{ "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
- { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
- { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
- { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
- { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
- { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
- { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
+ { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
+ { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
+ { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
+ { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
+ { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
+ { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
{ NULL, pn_Cmp_True }, /* always true */
};
return get_irn_link(block);
}
+/**
+ * Returns the Proj with projection number proj and NOT mode_M
+ */
+static ir_node *get_proj(const ir_node *irn, long proj) {
+ const ir_edge_t *edge;
+ ir_node *src;
+
+ assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
+
+ foreach_out_edge(irn, edge) {
+ src = get_edge_src_irn(edge);
+
+ assert(is_Proj(src) && "Proj expected");
+ if (get_irn_mode(src) == mode_M)
+ continue;
+
+ if (get_Proj_proj(src) == proj)
+ return src;
+ }
+ return NULL;
+}
+
/**
* Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
*/
static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
const ir_node *proj1, *proj2 = NULL;
const ir_node *block, *next_bl = NULL;
- const ir_edge_t *edge;
char buf[SNPRINTF_BUF_LEN];
char cmd_buf[SNPRINTF_BUF_LEN];
char cmnt_buf[SNPRINTF_BUF_LEN];
+ int is_unsigned;
/* get both Proj's */
- edge = get_irn_out_edge_first(irn);
- proj1 = get_edge_src_irn(edge);
- assert(is_Proj(proj1) && "CondJmp with a non-Proj");
+ proj1 = get_proj(irn, pn_Cond_true);
+ assert(proj1 && "CondJmp without true Proj");
- edge = get_irn_out_edge_next(irn, edge);
- if (edge) {
- proj2 = get_edge_src_irn(edge);
- assert(is_Proj(proj2) && "CondJmp with a non-Proj");
- }
+ proj2 = get_proj(irn, pn_Cond_false);
+ assert(proj2 && "CondJmp without false Proj");
/* for now, the code works for scheduled and non-schedules blocks */
block = get_nodes_block(irn);
- if (proj2) {
- /* we have a block schedule */
- next_bl = next_blk_sched(block);
-
- if (get_cfop_target_block(proj1) == next_bl) {
- /* exchange both proj's so the second one can be omitted */
- const ir_node *t = proj1;
- proj1 = proj2;
- proj2 = t;
- }
+
+ /* we have a block schedule */
+ next_bl = next_blk_sched(block);
+
+ if (get_cfop_target_block(proj1) == next_bl) {
+ /* exchange both proj's so the second one can be omitted */
+ const ir_node *t = proj1;
+ proj1 = proj2;
+ proj2 = t;
}
/* the first Proj must always be created */
+ is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
if (get_Proj_proj(proj1) == pn_Cond_true) {
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
- get_cmp_suffix(get_ia32_pncode(irn), !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
+ get_cmp_suffix(get_ia32_pncode(irn), is_unsigned),
get_cfop_target(proj1, buf));
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
}
else {
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
- get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode),
- !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
+ get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode), is_unsigned),
get_cfop_target(proj1, buf));
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
}
IA32_DO_EMIT(irn);
/* the second Proj might be a fallthrough */
- if (proj2) {
- if (get_cfop_target_block(proj2) != next_bl) {
- snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
- }
- else {
- cmd_buf[0] = '\0';
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrogh %s */", get_cfop_target(proj2, buf));
- }
- IA32_DO_EMIT(irn);
+ if (get_cfop_target_block(proj2) != next_bl) {
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
+ }
+ else {
+ cmd_buf[0] = '\0';
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
}
+ IA32_DO_EMIT(irn);
}
/**
finish_CondJmp(F, irn, get_ia32_res_mode(irn));
}
+/**
+ * Emits code for conditional SSE floating point jump with two variables.
+ */
+static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
+ lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+ IA32_DO_EMIT(irn);
+ finish_CondJmp(F, irn, mode_F);
+
+}
+
/**
* Emits code for conditional x87 floating point jump with two variables.
*/
if (reverse)
set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
- snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s", instr, reg);
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg);
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
IA32_DO_EMIT(irn);
-// lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %3D", irn);
lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
IA32_DO_EMIT(irn);
finish_CondJmp(F, irn, mode_Is);
}
+static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
+ int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
+ int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *in1, *in2, *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov));
+ in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov));
+
+ /* we have to emit the cmp first, because the destination register */
+ /* could be one of the compare registers */
+ if (is_ia32_CmpCMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+ }
+ else if (is_ia32_xCmpCMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+ }
+ else if (is_PsiCondCMov) {
+ /* omit compare because flags are already set by And/Or */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
+ }
+ else {
+ assert(0 && "unsupported CMov");
+ }
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ if (REGS_ARE_EQUAL(out, in2)) {
+ /* best case: default in == out -> do nothing */
+ }
+ else if (REGS_ARE_EQUAL(out, in1)) {
+ /* true in == out -> need complement compare and exchange true and default in */
+ ir_node *t = get_irn_n(irn, 2);
+ set_irn_n(irn, 2, get_irn_n(irn, 3));
+ set_irn_n(irn, 3, t);
+
+ cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), is_unsigned);
+
+ }
+ else {
+ /* out is different from in: need copy default -> out */
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
+ IA32_DO_EMIT(irn);
+ }
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
+ const char *reg8bit;
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
+
+ if (is_ia32_CmpSet(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
+ }
+ else if (is_ia32_xCmpSet(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
+ }
+ else if (is_ia32_PsiCondSet(irn)) {
+ /* omit compare because flags are already set by And/Or */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
+ }
+ else {
+ assert(0 && "unsupported Set");
+ }
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ /* use mov to clear target because it doesn't affect the eflags */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
+ IA32_DO_EMIT(irn);
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
+}
+
+static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
+}
+
+static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
+}
+
+static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ int sse_pnc = -1;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+
+ switch (get_ia32_pncode(irn)) {
+ case pn_Cmp_Leg: /* odered */
+ sse_pnc = 7;
+ break;
+ case pn_Cmp_Uo: /* unordered */
+ sse_pnc = 3;
+ break;
+ case pn_Cmp_Ue: /* == */
+ sse_pnc = 0;
+ break;
+ case pn_Cmp_Ul: /* < */
+ sse_pnc = 1;
+ break;
+ case pn_Cmp_Ule: /* <= */
+ sse_pnc = 2;
+ break;
+ case pn_Cmp_Ug: /* > */
+ sse_pnc = 6;
+ break;
+ case pn_Cmp_Uge: /* >= */
+ sse_pnc = 5;
+ break;
+ case pn_Cmp_Ne: /* != */
+ sse_pnc = 4;
+ break;
+ }
+
+ assert(sse_pnc >= 0 && "unsupported floating point compare");
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
+ IA32_DO_EMIT(irn);
+}
+
/*********************************************************
* _ _ _
* (_) | (_)
/* fill the table structure */
tbl.label = xmalloc(SNPRINTF_BUF_LEN);
- tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, "JMPTBL_");
+ tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
tbl.defProj = NULL;
tbl.num_branches = get_irn_n_edges(irn);
tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
/**
* Emit movsb/w instructions to make mov count divideable by 4
*/
-static void emit_CopyB_prolog(FILE *F, int rem, int size) {
+static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- fprintf(F, "\t/* memcopy %d bytes*/\n", size);
+ ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward*/");
- IA32_DO_EMIT(NULL);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
switch(rem) {
case 1:
+ IA32_DO_EMIT(NULL);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
break;
case 2:
+ IA32_DO_EMIT(NULL);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
break;
case 3:
+ IA32_DO_EMIT(NULL);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
IA32_DO_EMIT(NULL);
* Emit rep movsd instruction for memcopy.
*/
static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
- tarval *tv = get_ia32_Immop_tarval(irn);
- int rem = get_tarval_long(tv);
- ir_node *size_node = get_irn_n(irn, 2);
- int size;
+ FILE *F = emit_env->out;
+ tarval *tv = get_ia32_Immop_tarval(irn);
+ int rem = get_tarval_long(tv);
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- /* beware: size_node could be a be_Copy to fulfill constraints for ecx */
- size_node = be_is_Copy(size_node) ? be_get_Copy_op(size_node) : size_node;
- size = get_tarval_long(get_ia32_Immop_tarval(size_node));
-
- emit_CopyB_prolog(F, rem, size);
+ emit_CopyB_prolog(F, irn, rem);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
FILE *F = emit_env->out;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- emit_CopyB_prolog(F, size & 0x3, size);
+ emit_CopyB_prolog(F, irn, size & 0x3);
size >>= 2;
while (size--) {
assert(0 && "unsupported Conv_I2I");
}
- switch(get_ia32_op_type(irn)) {
+ switch(get_ia32_op_type(irn)) {
case ia32_Normal:
in_reg = get_in_reg(irn, 2);
out_reg = get_out_reg(irn, 0);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
}
else {
- lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "%1D", get_irn_n(irn, be_pos_Call_ptr));
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
}
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
}
/**
- * Emits code for Copy.
+ * Emits code for Copy/CopyKeep.
*/
-static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
+static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
+ FILE *F = emit_env->out;
const arch_env_t *aenv = emit_env->arch_env;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, be_get_Copy_op(irn))))
+ if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
+ be_is_unknown_reg(arch_get_irn_register(aenv, op)))
return;
if (mode_is_float(get_irn_mode(irn)))
IA32_DO_EMIT(irn);
}
+static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
+ Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
+}
+
+static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
+ Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
+}
+
/**
* Emits code for exchange.
*/
static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
FILE *F = emit_env->out;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *in1, *in2;
+ const arch_register_class_t *cls1, *cls2;
+
+ in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
+ in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
+
+ cls1 = arch_register_get_class(in1);
+ cls2 = arch_register_get_class(in2);
+
+ assert(cls1 == cls2 && "Register class mismatch at Perm");
+
+ if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
+ }
+ else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
+ "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
+ }
+ else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ assert(0 && "Perm with vfp should not happen");
+ }
+ else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
+ assert(0 && "Perm with st(X) should not happen");
+ }
- lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
IA32_DO_EMIT(irn);
}
* Emits code for Constant loading.
*/
static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
- FILE *F = env->out;
- char cmd_buf[256], cmnt_buf[256];
- const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ FILE *F = env->out;
+ char cmd_buf[256], cmnt_buf[256];
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
- if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
+ if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
const char *instr = "xor";
if (env->isa->opt_arch == arch_pentium_4) {
/* P4 prefers sub r, r, others xor r, r */
instr = "sub";
}
- lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
- }
- else {
- if (get_ia32_op_type(n) == ia32_SymConst) {
- lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
- }
+ lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
+ }
+ else {
+ if (get_ia32_op_type(n) == ia32_SymConst) {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
+ }
else {
- lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
}
- }
- lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
+ }
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
+}
+
+static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
}
IA32_EMIT(TestJmp);
IA32_EMIT(CJmp);
IA32_EMIT(CJmpAM);
+ IA32_EMIT(CmpCMov);
+ IA32_EMIT(PsiCondCMov);
+ IA32_EMIT(CmpSet);
+ IA32_EMIT(PsiCondSet);
IA32_EMIT(SwitchJmp);
IA32_EMIT(CopyB);
IA32_EMIT(CopyB_i);
IA32_EMIT(Conv_I2I);
IA32_EMIT(Conv_I2I8Bit);
IA32_EMIT(Const);
+ IA32_EMIT(xCmp);
+ IA32_EMIT(xCmpSet);
+ IA32_EMIT(xCmpCMov);
+ IA32_EMIT(xCondJmp);
IA32_EMIT2(fcomJmp, x87CondJmp);
IA32_EMIT2(fcompJmp, x87CondJmp);
IA32_EMIT2(fcomppJmp, x87CondJmp);
BE_EMIT(IncSP);
BE_EMIT(SetSP);
BE_EMIT(Copy);
+ BE_EMIT(CopyKeep);
BE_EMIT(Perm);
+ BE_EMIT(Return);
/* firm emitter */
EMIT(Jmp);
}
}
+/**
+ * Emits gas alignment directives
+ */
+static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
+ fprintf(F, "\t.p2align %u,,%u\n", align, skip);
+}
+
+/**
+ * Emits gas alignment directives for Functions depended on cpu architecture.
+ */
+static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
+ unsigned align; unsigned maximum_skip;
+
+ /* gcc doesn't emit alignment for p4 ?*/
+ if (cpu == arch_pentium_4)
+ return;
+
+ switch (cpu) {
+ case arch_i386:
+ align = 2; maximum_skip = 3;
+ break;
+ case arch_i486:
+ align = 4; maximum_skip = 15;
+ break;
+ case arch_k6:
+ align = 5; maximum_skip = 31;
+ break;
+ default:
+ align = 4; maximum_skip = 15;
+ }
+ ia32_emit_alignment(F, align, maximum_skip);
+}
+
+/**
+ * Emits gas alignment directives for Labels depended on cpu architecture.
+ */
+static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
+ unsigned align; unsigned maximum_skip;
+
+ /* gcc doesn't emit alignment for p4 ?*/
+ if (cpu == arch_pentium_4)
+ return;
+
+ switch (cpu) {
+ case arch_i386:
+ align = 2; maximum_skip = 3;
+ break;
+ case arch_i486:
+ align = 4; maximum_skip = 15;
+ break;
+ case arch_k6:
+ align = 5; maximum_skip = 7;
+ break;
+ default:
+ align = 4; maximum_skip = 7;
+ }
+ ia32_emit_alignment(F, align, maximum_skip);
+}
+
/**
* Walks over the nodes in a block connected by scheduling edges
* and emits code for each node.
need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
}
- if (need_label)
+ if (need_label) {
+ ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
+ }
sched_foreach(block, irn) {
ia32_emit_node(irn, env);
/**
* Emits code for function start.
*/
-static void ia32_emit_func_prolog(FILE *F, ir_graph *irg) {
+static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
entity *irg_ent = get_irg_entity(irg);
const char *irg_name = get_entity_ld_name(irg_ent);
fprintf(F, "\n");
ia32_switch_section(F, SECTION_TEXT);
+ ia32_emit_align_func(F, cpu);
if (get_entity_visibility(irg_ent) == visibility_external_visible) {
fprintf(F, ".globl %s\n", irg_name);
}
static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
- fprintf(F, "\tret\n");
ia32_dump_function_size(F, irg_name);
fprintf(F, "\n");
}
ia32_register_emitters();
- ia32_emit_func_prolog(F, irg);
+ ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
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